1447WhitewoodCtSaiCharanPaluru�+1984-255-4669

SanJose,CA–95131http://www.linkedin.com/in/saicharanpaluru�spaluru@ncsu.eduActivelyseekingfulltimepositionsinComputerArchitecture&ASICDesign/Verification

EMPLOYMENTMobileSystemsArchitectureIntern MicronTechnologyInc. May2016-Present

• InvolvedintheresearchofSOCgeneratedhardsilicontracestoanalyzememoryaccesspatternsinordertooptimizefutureDRAMandnon-DRAMmemoryarchitectures

• InvolvedinextensiveanalysisofLPDDR4trafficinordertoidentifyDRAMpagearchitecturalenhancementsSystemArchitecture–HardwareEngineer NvidiaInc. July2014-July2015

• InvolvedintheC-Modeldesignoftwoco-processorsnamelytheBootandPowerManagementprocessorandtheSafetyandCameraco-processorwhicharetobefeaturedinfutureTegraSOCs

• Primarylanguage:C++• InvolvedinthearchitecturereviewandimplementationofthenormalandpacketmodebasedI2CdeviceC-Model

whichisscheduledtobefeaturedinfutureTegraSOCs• InvolvedintheverificationoftheClockingandResetC-ModelinfrastructureonaNvidiaproprietaryfullchipsimulator• ImplementedtheDMAandAddressSpaceTranslationengineC-modelsinbothR5clustersonafutureTegraSOC

SystemArchitectureAnalyst,Intern NvidiaInc. July2013-December2013

• WasinvolvedintheC-ModeldesignoftheAMBAAPBBridgeforanextgenerationSOCwhichrequiredagoodworkingknowledgeoftheAPBProtocolandC++

• Wasinstrumentalintheperformancestudiesofanexistingchipinordertohelpreducebottlenecksinfuturechips.ThisinvolvedmeasuringvariousparameterslikememoryB/W,FPSandlatencyandcomparingthemwithexistingbenchmarks

• WasactivelyinvolvedintheredesignofthewiringsystembetweenthegraphicshostanditsclientsforanextgenerationSOC.Thisinvolvedaproperunderstandingofaproprietaryhardwaredebugtoolwhichmadeuseoftheobservationbus

LANGUAGESANDTECHNOLOGIES

• ProgrammingLanguages:C,C++,Python,Perl,Bashscripting,OpenMP,CUDA• Simulatorsworkedon:GPGPUSim,721Sim(Inhousecycleaccuratesuperscalarsimulator)• HardwareDescriptiveLanguages/VerificationLanguages:Verilog,SystemVerilog• DesignSoftwares:PSpice,Matlab,CadenceVirtuosa,LabView,KielUVision5,Modelsim,SynopsysDesignVision• AssemblyLanguages:LC3assemblylanguage,MASM611–8086assemblylanguage

EDUCATIONcurrent/pastRaleigh,NorthCarolinaNorthCarolinaStateUniversityGPA:4.0/4.0August2015-presentMSinComputerEngineering

• SpecializinginMicroarchitectureandASICDesign/VerificationwithafocusonGPUandCPUarchitecture• Graduatecoursework:ASICVerification,DigitalASICDesign,AdvancedMicroarchitecture,GPGPUArchitecture,

ArchitectureofParallelComputers,ComputerDesignTechnologyProjects

• LC3CPUASICVerification:Verifiedthedataandcontrolpathofapipelined5stageLC-3microcontrollerwithacomprehensiveinstructionset.OptimumfunctionalcoveragewasachievedbyConstrainedRandomTesting

• BellmanFordHWAccelerator:BuiltaVerilogbasedASIChardwareacceleratorforimplementingtheBellmanFordalgorithmonagivensetofinputsofsourcesanddestinationsandagivengraph

• SuperscalarProcessorRenamer:Pluggedarenamerclassintothegutsofaninhousecycleaccuratesuperscalarsimulator(721Sim)andmodelledindustrystandardstructuressuchastheArchitecturalmaptable,Renamemaptable,Freelist,ActivelistandShadowmaps

• TraceProcessor:Involvedinmodellingatraceprocessorontopofanexistinginhousecycleaccuratesuperscalarsimulator(721Sim)usingatracecacheandatracepredictorforthefrontendandadistributedexecutionparadigminthebackend

• GPGPUThreadBlockScheduling:ImplementedalternatethreadblockschedulingpolicieslikeLazyCTAandBlockCTAontheGPGPUSim

• DynamicInstructionSchedulinginanOutofOrderSuperscalarprocessor:ModelledaC++functionalsimulatorforanout-of-ordersuperscalarprocessorthatfetchesandissuesNinstructionspercycle.Perfectbranchpredictionandperfectcacheswereassumed

• GenericCacheSimulator:ImplementedagenericC++cachesimulatorinwhichusesaWriteBackWriteAllocatewithanLRUreplacementpolicyandcanimplementanylevelofmemoryhierarchyandvalidatedmodelwithexistingtracesandvalidationruns

• DynamicBranchPrediction:ModelledaC++branchpredictionsimulatorfordifferenttypesofpredictorslikegshare,bimodalandhybridpredictorsandusedinstructiontraceswithactualoutcomestostudytheireffectsonmispredictionratesofthevariouspredictors

• MultiprocessorCacheCoherence:ModelledasharedmultiprocessorsimulatorusingagenericC++cacheclassandimplementedcachecoherenceprotocolslikeMESI,MSIandDragoninthemultiprocessormemorysystem

Zuarinagar,Goa,IndiaBirlaInstituteOfTechnologyAndScience,Pilani,KKBirlaGoacampusGPA3.8/4.02010-2014BSinElectronicsandInstrumentation:Coursework:EmbeddedSystemDesign,AnalogandDigitalVLSIDesign,DigitalElectronics&ComputerOrganization,MicroelectronicCircuits,Signals&Systems,MicroprocessorsProgramming&Interfacing