Revision Slides for Computing

Systems andNetworks: Week 12

Graham White

Reading

The concept of adigital storedprogram computer

The von NeumannArchitecture

The CPU and thefetch-execute cycle

Some examples ofmachine code

Speed Disparities

Typical speeds ofcomputer components

Caching

The memory hierarchy

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Systems and Networks: Week 12Some Notes on Revision

Graham White

Electronic Engineering and Computer ScienceQueen Mary University of London

December 2012


Graham White

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Speed Disparities


Caching


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Notes on Reading

1 David A. Patterson and John L. Hennessy, ComputerOrganisation and Design, revised 4th edition (MorganKaufmann/Elsevier 2012). Website athttp://booksite.mkp.com/9780123838728/

2 Douglas E. Comer, Essentials of Computer Architecture(Pearson Prentice Hall 2005).

3 David A. Patterson and John L. Hennessy, ComputerArchitecture: A Quantitative Approach, 5th edition(Morgan Kaufmann/Elsevier 2012). (Goes beyond thematerial in this module, but it does have goodnumerical data.)


Graham White

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Speed Disparities


Caching


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Distinctions

The concept of a digital stored program computer

Digital means that data is represented by discrete,rather than continuous, values. The opposite isanalogue

Stored Program means that the program is stored incomputer memory and can be changed.

Implementation This doesnt say anything about howthe computer is implemented: a digital stored programcomputer could still be made of clockwork, likeBabbages machines


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Distinctions: Reading

Read Week 1 slidesSlides on Computers, Processors and DataRepresentationHennessy and Patterson, HistoricalPerspectives with References athttp://booksite.mkp.com/9780123838728/historical.php

Examples Think of examples of

1 a computer which is not digital2 a digital, electronic device which is not a

stored program computer


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Speed Disparities


Caching


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Where we are

1 Reading

2 The concept of a digital stored program computerThe von Neumann ArchitectureThe CPU and the fetch-execute cycleSome examples of machine code

3 Speed DisparitiesTypical speeds of computer componentsCachingThe memory hierarchy


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Speed Disparities


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The von Neumann Architecture

This is a description of the functional parts of amodern computer

1 control unit2 arithmetic unit3 memory4 data transfer and IO

Read Slides 20 and 21 of the Week 2 slidesWikipedia: http://en.wikipedia.org/wiki/Von_Neumann_architectureComer, Essentials of Computer Architecture, pp. 47f


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Function and Implementation

The von Neumann architecture was invented in the 40s and the functional parts of computers have stayed the

same (more or less) since then

but their implementation has changed hugelyRead Slides 1719, 2533 of the Week 2 slidesPatterson and Hennessy, Computer Organisation andDesign Chapter 1


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Speed Disparities


Caching


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Where we are

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Anatomy of the CPU

The CPU typically contains:

1 Circuits for doing arithmetic and for doing logicaloperations

2 Circuits for fetching instructions from memory

3 Circuits for fetching data from memory

4 Registers (fast memory locations in the CPU) forholding instructions and data

Read Comer, Essentials of Computer Architecture pp. 48ffPatterson and Hennessy, Computer Organisation andDesign, pp. 8087


Graham White

Reading





Speed Disparities


Caching


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The Fetch-Execute Cycle

This is the following algorithm:

Repeat forever {Fetch: Get the next instructionExecute: Execute that instruction}

Read Patterson and Hennessy, Computer Organisationand Design pp. 300316 (though this is very detailed)Comer, Essentials of Computer Architecture pp. 55fSlides 2227 of the Week 8 slidesNote that the fetch-execute cycle can have more orfewer steps, depending on how much detail we want


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The Program Counter

The CPU knows where the next instruction is bylooking in the program counter

The program counter is a register which contains theaddress of the next instruction

The CPU can execute jumps (branching, loops, etc) bychanging the value of the program counter

Read Slides 24ff. of the Week 8 slidesComer, Essentials of Computer Architecture, pp. 73fHennessy and Patterson, Computer Organisation andDesign, pp. 307ff, 383


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Pipelining

The fetch-execute cycle can be considerably optimisedby pipelining

Pipelining is an example of cachingRead Slides 2834 of the Week 8 slidesComer, Essentials of Computer Architecture pp. 299ffHennessy and Patterson, Computer Organisation andDesign pp. 330ff


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Where we are

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Assembler

Assembler allows you to write machine codeinstructions, but with

1 symbolic names for the instructions2 symbolic addresses for the memory locations

Assembler is compiled (strictly speaking assembled)and then loaded

1 compilation replaces the symbolic instruction nameswith binary machine code

2 loading replaces the symbolic addresses with binarymemory addresses

Read all of the Week 6 slides, and slides 134 of theWeek 8 slidesHennessy and Patterson, Computer Organisation andDesign, pp. 330ff, Appendix BComer, Essentials of Computer Architecture, pp. 116ff


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What Assembler Allows

Assembler allows you explicit control over what goesinto registers

You must load all data from RAM and decide whatregister to put it into

After you have done a calculation, you must store theresult in RAM

Read Comer, Essentials of Computer Architecturepp. 48ffPatterson and Hennessy, Computer Organisation andDesign, pp. 8087the Week 6 slides


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Example

The Java code

y = x + y;

corresponds to the following assembler

lw $t0 xlw $t1 yadd $t1 $t0 $t1sw $t1 y


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Where we are

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Units of Time

Remember the table on Slide 41 of the Week 8 slides It is the only thing in this module that you need to

memorise

but memorise it The thing to learn from it is the connection between

speed and scale:

1 If a component runs fast, it must be small2 If two components must be synchronised, then they

must be close together


Graham White

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Caching


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Where we are

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RAM and CPU

RAM is about 1001000 times as slow as the CPU We cache data which we fetch from the RAM that is, we put it in a small area of very fast memory

which is very close to (or in) the CPU

So, if the CPU can operate on data in the cache,things go well

That is, if the CPU gets more cache hits (when thedata it wants is in the cahce) than cache misses (whenthe data it wants isnt in the cache)

This usually works, because of data locality:consecutive pieces of data are usually found closetogether in the cache


Graham White

Reading





Speed Disparities


Caching


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RAM and CPU: Reading

Read Slides 3856 of the Week 8 slides, and theWeek 9 slides

Comer, Essentials of Computer Architecture,Chapter 12 (pp. 185ff)

Hennessy and Patterson, ComputerOrganisation and Design, Chapter 5(pp. 450ff)

There is a more quantitative, design-orienteddiscussion of caching in Hennessy andPatterson, Computer Architecture: AQuantitative Approach, Chapter 2 (pp. 72ff)


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Where we are

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The Memory Hierarchy

There are a lot of memory technologiesand there are also a lot of memory technologies thatare no longer used because they have been superceded

Fast memory technologies are expensive and (in theamounts you can afford) small

Large memory technologies are cheap but slow (eventhe advent of solid state disks has not changed thebasic picture)

So we use a selection of memory technologies together


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The Basic Strategy

The basic strategy is caching (or buffering, as it issometimes also known)

We keep most of our data on large, cheap devices but when we need it, we move some of it onto a small,

expensive device

this does not work in all cases, but if we have enoughmemory locality, it works most of the time

Read Slide 45 of the Week 8 slidesComer, Essentials of Computer Architecture, Chapter 9(pp. 137ff)Hennessy and Patterson, Computer Organisation andDesign, Chapter 5 (pp.450ff)

ReadingThe concept of a digital stored program computerThe von Neumann ArchitectureThe CPU and the fetch-execute cycleSome examples of machine code

Speed DisparitiesTypical speeds of computer componentsCachingThe memory hierarchy

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Revision Slides for Computing