Road to Chiplets: Architecture - events.meptec.org

Road to Chiplets: ArchitectureJuly 13 & 14, 2021

www.meptec.org

Road to Chiplets, and the Next 1000X

Ming Zhang

Strategy and System Architects, Synopsys

July 13, 2021

© 2021 Synopsys, Inc. 2

Outline

Why chiplets, and where

How architecture, design, and manufacturing are now different

How our industry can give wings to innovators of the next 1000X


Se

cu

re b

y D

es

ign

, if

Do

ne

Rig

ht

Why Chiplets

Faster

TTM

Chiplets on optimal

processes offer

best-in-class

functionality

Greater

system PPA

per volume

System of Chiplets

Integration

Partitioning of

large die results

in higher system

yield

Lower

unit cost

System on Chip

Disaggregation


Common Use Cases

Server & High-

Performance

Compute (HPC)

Ethernet Switches

& Networking

SoCs

Evolution of Optical

Modules (Co-

Packaged Optics)

Artificial

Intelligence (AI)

INT

EG

RA

TIO

ND

ISA

GG

RE

GA

TIO

N


Data Center & Networking Drive Growth

• ~$6B by 2024 (CAGR of

~10%)

• ~$60B by 2035

• Initially driven by HPC &

Data Center

• Wireless Communications

catching up

Source: IHS Markit, 2019

Overa l l Chip le t SAM by Market Segment

Ag

gre

ga

te

Pro

ce

ss

or M

ark

et

Bu

ilt w

ith

Ch

iple

ts

$(M

)

Computing & Data Storage

WirelessCommunication

s

IndustrialElectronics

WiredCommunications

Consumer Electronics

Automotive Electronics


Diverse Applications Demand Diverse Tech & IP “Menus”

Source: Synopsys Marketing Team, 2020

Appl ica t ion Technology Node Inter face Type


Advanced Packaging TrendC

ost &

Co

mp

lexity

Die/Package Size, Density & IO Count

Data Rates

Data Rate: 112Gbps

Organic Substrate

Hig

h S

pe

ed

Se

rial P

HY

Hig

h D

en

sity

Pa

ralle

l PH

Y

Data Rate: 56Gbps

Wafer Level

Packaging

Data Rate: 3.2 → 8Gbps

Silicon

Interposer

Data Rate: 4~6Gbps

Hybrid Bonding


Advanced Packaging LandscapeMapping of Players based on Technology

I/O

De

ns

ity

* (

I/O

pe

r m

m2)

1 5

2 0

1 0 0

3 0 0

> > 1 0 , 0 0 0

3 0 0 2 0 0 1 0 0 5 0 < 5 0

I /O P i tch (µm)

3D Stacked

Memor ies: TSV,

Micro -bumps

Embedded S i br idge

Hybr id Bonding: Bump - less

2 .5D In terposers

UHD FO

Source: Yole, 2020


How can We Help Chip Designers Innovate?

Recognize the ”new” design targets

Give them wings

Show them the road (to chiplets)


New Design Targets of The Chiplet Era

Traditional Design Target: PPA

New Target #1

Diversity of Design

Answ er

Verified and interoperable

blocks + manufacturing

models

Customer Want #1

Explore the “menu” of

functions and

manufacturing options

New Target #2

Velocity of Innovation

Answ er

End-to-end integrated

design flow supporting 3D

design

Customer Want #2

Napkin to product(s)

faster

New Target #3

Robustness of Products

Answ er

Silicon lifecycle

management

Customer Want #3

Products can tolerate

variations and partial

failures


• Substrate choice

• Chiplet / IP choice

• Early PPA /

Reliability / Cost

E X P LO R ET H O R O U G H L Y

• Cost (Yield)

• Time to Volume

• In-field Safety,

Security &

Reliability

M A N U FA C T U R ER O B U S T L Y

• Design IP, RTL to

GDS

• Optimization

• SKU Variation

D E S I G NR A P I D L Y

An Ideal Journey for Chiplet-Based Design


Total Solution = Interface IP + Design Platform + Manufacturing

E X P L O R E M A N U FA C T U R ED E S I G N

Architectural Analysis

D2D + HSIO IP

Customer IP + Chiplet

Substrate Model

Early DTCO

Implementation

Analysis

Verification

Homogeneous

Disaggregation

Heterogeneous

IntegrationChiplets

Silicon Lifecycle

Management

Substrate / Package

Test & Debug

Correct by Construction. Secure by Design.

Manufacturing Enablement Synopsys TechnologyKEY:




Give them wings



Enabling the New Design Targets

Diversity

of Design

Verified and

interoperable blocks +

manufacturing models

Velocity

of Innovation

End-to-end

integrated design flow

supporting 3D design

Robustness

of Products

Silicon lifecycle

management


Interface IPs Adapt to Diverse Manufacturing Options & Use Cases

Packaging

technology

2D – Substrate 2.5D – RDL Fanout 2.5D – Si-Interposer / Bridge 3D – Die Stacking

D2D architecture SerDes SerDes / Parallel Parallel Bumpless (Parallel)

Reach ~50mm ~5~15mm 4~5mm “0mm”

Bump Pitch 130um – 150um 40 - 55um ~10um

Data rate / lane40G / 56G – NRZ

112G → 224G – PAM48G → 16G DDR 4~6G DDR

Power efficiency 1~2 pJ/b 0.3~0.5 pJ/b 0.1~0.3 pJ/b

Latency 5~6 ns 4~5 ns <3 ns

StandardsOIF: CEI-112G-XSR/USR

JEDEC: JESD204x

OCP: OpenHBI, BoW

ChipsAlliance: AIBEmerging

Use Cases

• Heterogenous integration:

- 5G, ADC, Sensors

- SiPhotonics/CPO

• Low-cost Server/AI

• High radix Switches

• Mid-range/Edge compute

- Servers/AI

• Automotive

• High-end HPC

- AI training, Servers

- HBM memory

• High End HPC

• SRAM, memory access

• Mobile compute

Assembly Density / Optimal Integration

Range


Unified Design Platform from A to Z

3D Pathfinding

Thermal Integrity

Place & Route

Test

Extraction

Signal & Power Integrity

Timing Analysis

Physical Verification

3D DesignArchitecture


Long Live the ChipsSilicon monitoring and data analytics improve design quality

Design Chip Production System Bring-Up In-Field

On-Chip Sensor FeedbackYield / Test

Optimization

Rapid Debug

Reliability Improvement

Performance

Optimization

Predictive Maintenance

DVFSProc

Voltage CLK

P

V

T

Chip




Give them wings



Total Solution = Interface IP + Design Platform + Manufacturing

E X P L O R E M A N U FA C T U R ED E S I G N

Architectural Analysis

D2D + HSIO IP

Customer IP + Chiplet

Substrate Model

Early DTCO

Implementation

Analysis

Verification

Homogeneous

Disaggregation

Heterogeneous

IntegrationChiplets

Silicon Lifecycle

Management

Substrate / Package

Test & Debug

Correct by Construction. Secure by Design.

Manufacturing Enablement Synopsys TechnologyKEY:


Chiplets are the Road to the Next 1000X

• Holistic system optimization

across X, Y and Z

dimensions

• Heterogeneous integration

of 100+ best-in-class

chiplets

• Billion+ 3D interconnects

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COPYRIGHT NOTICE

This presentation in this publication was presented at the Road to Chiplets: Architecture Workshop(July 13 & 14, 2021). The content reflects the opinion of the author(s) and their respective companies. The inclusion of presentations in this publication does not constitute an endorsement by MEPTEC or the sponsors.

There is no copyright protection claimed by this publication. However, each presentation is the work of the authors and their respective companies and may contain copyrighted material. As such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author(s) or their companies.

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Road to Chiplets: Architecture - events.meptec.org