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Modeling of Large-Area nMOS Devices for Smart-Power Applications

Alberto Roncaglia Gian Carlo CardinaliSandro SolmiCNR-IMM,

Via Gobetti 101 I-40129 Bologna, ItalyTel. +39 051 639 91 22

roncaglia@lamel.bo.cnr.it

Nicol o Speciale Massimo RudanGuido Masetti DEIS ARCES,

Viale Risorgimento 2 I-40136 Bologna, ItalyTel. +39 051 209 37 77 nspeciale@deis.unibo.it

Abstract

Power devices operating in the medium voltage rangemay be obtained by making use of a simple nMOS tech-nology characterized by a rather thick gate oxide and of alarge-area layout topology, often including complex inter-digitated geometries.

The effect of interconnect resistances on these devicesis remarkable, due to the high W/L ratios employed, and has to be accounted for in order to correctly model their DC behaviour. In this work, a distributed SPICE modelis proposed for large area power nMOS devices, based on MOSFET model BSIM3v3 , that allows to describe thecomplex dependence that the drain current exhibits on thelayout geometry.

1. Introduction

Rapid advances in integrated circuit and power tech-nology have created new opportunities to develop inte-grated circuit families where power and control functionsare implemented on the same chip, allowing an increasedcircuit functionality. In this framework, the importance of MOS-based power technologies is gaining in importancethanks to the advantages they provide in terms of fabri-cation cost, reliability and simplicity in integrating on thesame die power and signal devices for the target of smart-

power applications. Following this approach power de-vices integrated with logic circuitry may be obtained usinga low cost nMOS technology with lateral power driversoperating in the medium voltage range and generally hav-ing a high W/L ratio [1] [2].A typical application of this kind of smart power technol-ogy is represented by thermal ink-jet printer heads, wherethe ink ejection system is commonly realized by an arrayof thermoelectrical actuators each activated by a powerdriver, operating as a switch, while the smart circuitry forthe control can be implemented with logic devices inte-grated on the same chip [3] [4] [5].

In the design of integrated circuits the availability of aproper modeling kit is fundamental to perform circuit sim-ulations in order to optimize the design.

Figure 1. Measured I d scaling upon W (V gs = 10 V).

For the case of MOS power devices, common low voltagecompact models cannot be applied straightforwardly dueto the particular features that a power device needs to havein order to meet specic requirements.An example is represented by the remarkable effect that

the distributed voltage drops on the source and drain re-gions exert on the DC operation of the device, due to itshigh W/L aspect ratio which is often needed to obtain alow on-resistance.Fig. 1 shows the measured I d scaling with W for a xed

bias ( V gs = 10 V, V ds = 0 .1V, V bs = 0V). It is worthnoting that the dependence of the drain current on W de-viates from the simple law predicted by a rst order MOSmodel (dashed line in gure).In the following, a SPICE-like distributed model suitedto describe the DC operation of large area nMOS devicescharacterized by high W/L ratio is proposed and compar-isons between measured and simulated currents for a widerange of different W values are shown.

2. The power device

A typical layout for a nMOS power device here con-sidered is reported in Fig. 2, which shows a six ngers,W = 756 m, L = 4 m transistor with an estimated

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Figure 2. Typical layout of a power nMOS six ngersdevice.

Figure 3. Schematic current ow within the driver in-terdigitated structure.

RON = 3 . In order to obtain a sufcient driving capa-bility, the device is designed with a very high W/L ratio.Moreover, several parallel gates (clearly visible in the g-ure) are realized and connected to each other (the layoutin gure features six gates) to give rise to a current multi-plication. The source and drain connections are interdig-itally shaped so that the complete device acts essentiallyas a parallel of six devices, each sharing the drain or thesource terminal with the adjacent one.The reason why the power device modeling cannot besolved by applying a standard MOS model is highlightedin Fig. 3, where the distribution of the current ow withinthe interdigitated structure of the driver is represented in asimplied way. Due to the high current levels occurring inthe operating conditions of interest, a distributed voltagedrop occurs on the metal ngers employed to contact thesource and drain diffusions. The electron injection intothe parallel device channels is thus inuenced by the dis-tributed polarization of the source and drain metals, bothin terms of load effect (variation of the local V ds , V gs ap-plied along the channel) and in terms of distributed bodyeffect: the variable source voltage V s induces a differentvalue of the threshold voltage on different positions in the

channels, due to the distribution of local V sb .

3. The proposed model

The proposed model is based on a well known idea tosubdivide the driver channels in portions [6] [7]. If the dis-tributed effects induced by the parasitics resistances canbe assumed to have a negligible effect on the modeling ac-curacy, each device portion can be described with lumpedcircuit components, both active (transistors) and passive(resistances). The implementation of the model is in prac-

tice constituted by a netlist of circuit components whosebase cell is shown in Fig. 4.In the gure the different considered elements of the

model are shown: the r c contact resistances (which modelthe effect of both the metal contact and the source-draindiffusion), the series resistances associated to the source-drain interconnects r s and the lumped transistors that rep-resent the active channels of the interdigitated MOS de-vice.The macro-model has a fully modular structure and maybe regarded as a matrix with horizontal rows and verti-cal columns. Each row represents a single nger of theinterdigitated structure, in which the source and drain ter-minals are alternate. The row is partitioned in N modules,each containing a lumped transistor with channel length Lequal to the actual channel length of the driver and a chan-nel width W = W T /N where W T is the actual channelwidth of the driver. In this case the discretization step of the channel is chosen to be equal to the physical distancebetween two adjacent contacts of the source-drain regions.This choice permits to describe the effect of the contact re-sistances in a straightforward manner, simply introducinga resistance r c between the node shared by two subsequentparasitic resistances rs and the transistor source (drain)terminals. By so doing, the effect of the contact on thecharge carriers which ow from the interconnects to thechannel through the contact can be simply described. Thevalue of parameter r c is meant to be equal to the actualvalue of the contact resistance for the adopted technology.As far as the interconnect resistances rs are concerned,they are calculated depending on the discretization step of the channel as r s = RT /N being RT the total resistanceof a single source-drain metal interconnect.

The complete netlist describing a large-area power devicehas a number of components depending on the channeldiscretization step; that number can be large, if the con-tacts are close to each other and the channel width is high.The simulation of the driver performed with this methodis thus a costly computational task, in particular if sev-eral drivers have to be included in the simulation. Never-theless, a different partition strategy could be applied byusing different values for interconnect and parasitic resis-tances and MOS aspect ratio, in order to reduce the modelcomplexity. On the other hand, the proposed model hasthe advantage to be straightforwardly self-adapting to anylayout geometry which may be adopted for the driver de-sign, because it does not contain geometry-dependent pa-rameters and any layout information is embedded withinthe netlist topology. Moreover, all the parameters in themodel have a physical meaning, and they could be esti-mated in advance by knowing the technological propertiesof the fabrication process, without making tting adapta-tion of the values on the basis of the device experimen-tal characterization. Finally, Section 4 describes how themodel allows to choose a parameter set which embeds allthe active device features, ensuring a unied descriptionfor the logic and the power devices, in terms of designkit, with great advantages with regard to its simplicity and

exibility in use.

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Figure 4. Distributed model base cell.

4. Parameter extraction

The extraction of the distributed model parameters wasperformed according to the following approach. As a rststep, a complete BSIM3v3 DC model card was extractedmaking use of a standard set of measurements from atest pattern shown in Fig. 5 (a) with different small sizegeometries (30x30, 30x4, 5x30 and 10x30). The obtainedvalues were adopted to model the MOSFET device of thedistributed model. As far as the series resistances are con-cerned, measurements made on the set of devices shownin Fig. 5 (b), were employed. In this extraction stage,MOS parameters in the model netlist were left unchangedas previously determined while the values of the resis-tances rc and rs were extracted by matching measuredI d (V gs ) curves in the linear region with V ds of 0.1 V andV sb of 0 V, with SPICE simulations performed with thenetlist model. In this operation, the various geometriesavailable in the pattern of Fig. 5(b) were considered, withsix ngers having L = 4 m and different channel widthsranging from 30 to 840 m.

The extraction procedure exploits the relative insensi-tivity of drain current to rc parameter for high channelwidths, and its almost complete insensitivity to r s param-eter for small channel widths. A rst r c value is extractedby tting the I d (V gs ) curves belonging to devices withthe W smallest sizes (90, 180, 360 m). Subsequently,the extracted value for r c is kept constant and a rst valuefor r s is extracted on the curves measured on the largerdevices (480, 600, 720, 840 m). Finally, the values of the two parameters are rened by performing another ex-traction on a group of characteristics including deviceswith both large and small size.Both obtained values ( r c = 44.56 , rs = 64.9 m)are physical referring to the contact and source-drain

diffusions resistances measured values ( r c ) and to themeasured metal interconnect sheet resistance ( r s ).

Figure 5. Test pattern for the extraction of (a) lowvoltage BSIM3v3 DC model card and (b) the modelseries resistances.

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Figure 6. I d (V gs ) curves measured (points) and simu-

lated (lines) power devices with different geometries.

5. Model validation

The agreement between the simulated curves and themeasurements obtained with the model is shown in Fig. 6,reporting the comparison of the simulated and measuredI d (V gs ) curves belonging to different drivers with chan-nel width from 90 to 840 m. Each device is simulatedwith the same parameters for the distributed model (bothwith regard to the MOS components and the resistancesincluded in Fig. 4), while the number of model sectionsis different for each device and calculated on the basis of the layout features according to the principles discussedabove.The good accordance obtained demonstrates the capabil-ity of the model to describe the DC behavior of the powerdevices in a layout-dependent fashion, by exploiting a pa-rameter set which does not need to be adapted on the lay-out geometry at all. Besides, all the parameters concern-ing the MOS model for the components included in thenetlist do not need to be extracted on the drivers measure-

ment and can be shared with the logic transistors obtainedwith the same technology within a smart-power scenario,thus allowing for a simple design kit to apply for all thedevices, both for power and signal applications.The device I d scaling prediction for different layouts isrepresented in Fig. 7, where measured and simulated cur-rent values for devices with different channel widths andfor a xed bias are reported. The unusual behavior of the drain current, which deviates from the simple pro-portionality that the rst-order MOS model would predict(Fig. 1), is fairly reproduced by the simulation. The effect,due to the distributed series resistance, is, as expected, in-

creasing with increasing channel widths, due to the higherresistance values of the longer source-drain metals andcurrent levels.

Figure 7. Comparison between measured (points) andsimulated (line) I d scaling with transistor width.

Acknowledgements

Olivetti I-JET Laboratory is greatfully acknowledgedfor providing the devices employed in the experiments.

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