Users M

anual

www.renesas.com

RX62N Group, RX621 GroupUsers Manual: Hardware

RENESAS 32-Bit MCURX Family / RX600 Series

Dec 2011

32

Rev.1.30

All information contained in these materials, including products and product specifications,represents information on the product at the time of publication and is subject to change byRenesas Electronics Corp. without notice. Please review the latest information published byRenesas Electronics Corp. through various means, including the Renesas Electronics Corp.website (http://www.renesas.com).

Preliminary SpecificationThis is a Preliminary specification and is subject to change.

Cover

Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: Standard, High Quality, and Specific. The recommended applications for each Renesas Electronics product depends on the products quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

Standard: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.

High Quality: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support.

Specific: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) Renesas Electronics product(s) means any product developed or manufactured by or for Renesas Electronics.

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

How to Use This Manual

1. Objective and Target UsersThis manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers.This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes.

The following documents have been prepared for the RX62N Group, RX621 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document.

When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes.

The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual.

Document Type Contents Document Title Document No.Short Sheet Overview of hardware

Data Sheet Overview of hardware and electrical characteristics RX62N Group, RX621 Group Data seet

R01DS0052EJ

Users manual: Hardware

Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation

RX62N Group, RX621 GroupUsers manual: Hardware

This Users manual

Users manual: Software

Detailed descriptions of the CPU and instruction set RX Family SeriesUsers manual: Software

RJJ09B0465

Application Note Examples of applications and sample programs

Renesas Technical Update

Preliminary report on the specifications of a product, document, etc.

2. Description of RegistersEach register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below.

X.X.X ... Register

(1) R/W: The bit or field is readable and writable.R/(W): The bit or field is readable and writable. However, writing to this bit or field has some

limitations. For details on the limitations, see the description or notes of respective registers.R: The bit or field is readable. Writing to this bit or field has no effect.

(2) Reserved. Make sure to use the specified value when writing to this bit or field; otherwise, the correct operation is not guaranteed.

(3) Setting prohibited. The correct operation is not guaranteed if such a setting is performed.

Address xxxx xxxxxh

b7 b6 b5 b4 b3 b2 b1 b0

... ... ... ...

Value after reset x 0 0 0 0 0 0 0

Bit Symbol Bit Name Description R/W

b0 ... 0 ... Bit 0: ......1: Setting prohibited

R/W

b3 to b1 Reserved The read value is 0. The write value should always be 0. R/W

b4 ... 4 ... Bit 0: ......1: ......

R

b6, b5 ... [1:0] ... Bi 0 0: ......0 1: ......Settings other than above are prohibited.

R/(W)*

b7 Reserved The read value is undefined. Writing to this bit has no effect. R

(1)(3)

(2)

(3)

3. List of Abbreviations and Acronyms

All trademarks and registered trademarks are the property of their respective owners.

Abbreviation Full FormACIA Asynchronous Communication Interface Adapterbps bits per secondCRC Cyclic Redundancy CheckDMA Direct Memory AccessDMAC Direct Memory Access ControllerGSM Global System for Mobile CommunicationsHi-Z High ImpedanceIEBus Inter Equipment BusI/O Input / OutputIrDA Infrared Data AssociationLSB Least Significant BitMSB Most Significant BitNC Non-ConnectPLL Phase Locked LoopPWM Pulse Width ModulationSIM Subscriber Identity ModuleUART Universal Asynchronous Receiver / TransmitterVCO Voltage Controlled Oscillator

1. Features.......................................................................................................................................... 44

1. Overview......................................................................................................................................... 451.1 Outline of Specifications ....................................................................................................... 451.2 List of Products ..................................................................................................................... 501.3 Block Diagram ...................................................................................................................... 521.4 Pin Assignments ................................................................................................................... 531.5 Pin Functions........................................................................................................................ 83

2. CPU ................................................................................................................................................ 902.1 Features................................................................................................................................ 902.2 Register Set of the CPU ....................................................................................................... 91

2.2.1 General-Purpose Registers (R0 to R15) ...................................................................................... 92

2.2.2 Control Registers ......................................................................................................................... 92

2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) ................................................... 93

2.2.2.2 Interrupt Table Register (INTB) ........................................................................................ 93

2.2.2.3 Program Counter (PC) ....................................................................................................... 93

2.2.2.4 Processor Status Word (PSW) ........................................................................................... 94

2.2.2.5 Backup PC (BPC) .............................................................................................................. 96

2.2.2.6 Backup PSW (BPSW) ....................................................................................................... 96

2.2.2.7 Fast Interrupt Vector Register (FINTV) ............................................................................ 96

2.2.2.8 Floating-Point Status Word (FPSW) ................................................................................. 97

2.2.3 Accumulator (ACC) .................................................................................................................... 99

2.3 Processor Mode.................................................................................................................. 1002.3.1 Supervisor Mode........................................................................................................................ 100

2.3.2 User Mode ................................................................................................................................. 100

2.3.3 Privileged Instruction ................................................................................................................ 100

2.3.4 Switching Between Processor Modes........................................................................................ 100

2.4 Data Types ......................................................................................................................... 1012.4.1 Integer........................................................................................................................................ 101

2.4.2 Floating-Point ............................................................................................................................ 101

2.4.3 Bitwise Operations .................................................................................................................... 102

2.4.4 Strings........................................................................................................................................ 102

2.5 Endian................................................................................................................................. 1032.5.1 Switching the Endian................................................................................................................. 103

2.5.2 Access to I/O Registers.............................................................................................................. 107

2.5.3 Notes on Access to I/O Registers .............................................................................................. 107

2.5.4 Data Arrangement...................................................................................................................... 108

2.5.4.1 Data Arrangement in Registers ....................................................................................... 108

2.5.4.2 Data Arrangement in Memory ......................................................................................... 108

2.5.5 Notes on the Allocation of Instruction Codes ........................................................................... 108

2.6 Vector Table ....................................................................................................................... 1092.6.1 Fixed Vector Table .................................................................................................................... 109

Contents

2.6.2 Relocatable Vector Table .......................................................................................................... 110

2.7 Operation of Instructions..................................................................................................... 1112.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions ............ 111

2.8 Pipeline ............................................................................................................................... 1122.8.1 Overview ................................................................................................................................... 112

2.8.2 Instructions and Pipeline Processing ......................................................................................... 113

2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing ............... 113

2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing .......... 115

2.8.2.3 Pipeline Basic Operation ................................................................................................. 118

2.8.3 Calculation of the Instruction Processing Time ........................................................................ 120

2.8.4 Numbers of Cycles for Response to Interrupts.......................................................................... 121

3. Operating Modes .......................................................................................................................... 1223.1 Operating Mode Types and Selection ................................................................................ 1223.2 Register Descriptions.......................................................................................................... 123

3.2.1 Mode Monitor Register (MDMONR) ....................................................................................... 123

3.2.2 Mode Status Register (MDSR).................................................................................................. 124

3.2.3 System Control Register 0 (SYSCR0)....................................................................................... 125

3.2.4 System Control Register 1 (SYSCR1)....................................................................................... 126

3.3 Details of Operating Modes ................................................................................................ 1273.3.1 Single-Chip Mode...................................................................................................................... 127

3.3.2 On-Chip ROM Enabled Extended Mode................................................................................... 127

3.3.3 On-Chip ROM Disabled Extended Mode ................................................................................. 127

3.3.4 Boot Mode ................................................................................................................................. 127

3.3.5 USB Boot Mode ........................................................................................................................ 127

3.4 Transitions of Operating Modes.......................................................................................... 1283.4.1 Operating Mode Transitions According to Mode Pin Setting................................................... 128

3.4.2 Operating Mode Transitions According to Register Setting ..................................................... 129

4. Address Space.............................................................................................................................. 1304.1 Address Space ................................................................................................................... 1304.2 External Address Space ..................................................................................................... 131

5. I/O Registers ................................................................................................................................. 1325.1 I/O Register Addresses (Address Order)............................................................................ 1345.2 I/O Register Bits.................................................................................................................. 170

6. Resets........................................................................................................................................... 2236.1 Overview............................................................................................................................. 2236.2 Register Descriptions.......................................................................................................... 226

6.2.1 Reset Status Register (RSTSR) ................................................................................................. 226

6.2.2 Reset Control/Status Register (RSTCSR) ................................................................................. 226

6.2.3 IWDT Status Register (IWDTSR)............................................................................................. 226

6.3 Operation ............................................................................................................................ 227

6.3.1 Pin Reset .................................................................................................................................... 227

6.3.2 Power-On Reset......................................................................................................................... 227

6.3.3 Voltage-Monitoring Reset ......................................................................................................... 228

6.3.4 Deep Software Standby Reset ................................................................................................... 228

6.3.5 Independent Watchdog Timer Reset ......................................................................................... 228

6.3.6 Watchdog Timer Reset .............................................................................................................. 228

6.4 Determination of Reset Generation Source........................................................................ 2296.5 Usage Notes....................................................................................................................... 229

6.5.1 Notes on Board Design.............................................................................................................. 229

7. Voltage Detection Circuit (LVD) .................................................................................................... 2307.1 Overview............................................................................................................................. 2307.2 Register Descriptions.......................................................................................................... 231

7.2.1 Reset Status Register (RSTSR) ................................................................................................. 231

7.2.2 Key Code Register for Low-Voltage Detection Control Register (LVDKEYR)...................... 231

7.2.3 Low-Voltage Detection Control Register (LVDCR)................................................................. 232

7.3 Voltage Detection Circuit .................................................................................................... 2347.3.1 Voltage Monitoring Reset ......................................................................................................... 234

7.3.2 Voltage Monitoring Interrupt .................................................................................................... 236

7.3.3 Cancellation of Deep Software Standby Mode by the Voltage Detection Circuit .................... 239

8. Clock Generation Circuit ............................................................................................................... 2408.1 Overview............................................................................................................................. 2408.2 Register Descriptions.......................................................................................................... 242

8.2.1 System Clock Control Register (SCKCR)................................................................................. 243

8.2.2 External Bus Clock Control Register (BCKCR) ....................................................................... 245

8.2.3 Oscillation Stop Detection Control Register (OSTDCR).......................................................... 246

8.2.4 Sub-Clock Oscillator Control Register (SUBOSCCR) ............................................................. 247

8.3 Main Clock Oscillator .......................................................................................................... 2488.3.1 Connecting a Crystal Resonator ................................................................................................ 248

8.3.2 External Clock Input.................................................................................................................. 249

8.4 Sub-Clock Oscillator ........................................................................................................... 2508.4.1 Connecting 32.768-kHz Crystal Resonator ............................................................................... 250

8.4.2 Handling of Pins when Sub-Clock is Not Used ........................................................................ 251

8.5 On-Chip Oscillator .............................................................................................................. 2518.6 Oscillation Stop Detection Circuit ....................................................................................... 2518.7 Internal Oscillation Circuit ................................................................................................... 2518.8 PLL Circuit .......................................................................................................................... 2518.9 Frequency Divider............................................................................................................... 2518.10 Internal Clock...................................................................................................................... 252

8.10.1 System Clock (ICLK)................................................................................................................ 252

8.10.2 Peripheral Module Clock (PCLK)............................................................................................. 252

8.10.3 External Bus Clock (BCLK)...................................................................................................... 253

8.10.4 SDRAM Clock (SDCLK).......................................................................................................... 253

8.10.5 Dedicated USB Clock (UCLK) ................................................................................................. 253

8.10.6 Dedicated RTC Clock (SUBCLK) ............................................................................................ 253

8.10.7 On-Chip Oscillator Clock (IWDTCLK).................................................................................... 253

8.11 Oscillation Stop Detection Function.................................................................................... 2548.11.1 Detection of Oscillation Stop and Operation after the Detection.............................................. 254

8.11.2 Oscillation Stop Detection Interrupt.......................................................................................... 255

8.11.3 Note on Oscillation Stop Detection Function............................................................................ 255

8.12 Usage Notes....................................................................................................................... 2568.12.1 Notes on Clock Generation Circuit ........................................................................................... 256

8.12.2 Notes on Resonator.................................................................................................................... 257

8.12.3 Notes on Board Design.............................................................................................................. 257

9. Low Power Consumption .............................................................................................................. 2589.1 Overview............................................................................................................................. 2589.2 Register Descriptions.......................................................................................................... 261

9.2.1 Standby Control Register (SBYCR).......................................................................................... 263

9.2.2 Module Stop Control Register A (MSTPCRA)......................................................................... 265

9.2.3 Module Stop Control Register B (MSTPCRB) ......................................................................... 267

9.2.4 Module Stop Control Register C (MSTPCRC) ......................................................................... 269

9.2.5 Deep Standby Control Register (DPSBYCR) ........................................................................... 270

9.2.6 Deep Standby Wait Control Register (DPSWCR) .................................................................... 272

9.2.7 Deep Standby Interrupt Enable Register (DPSIER).................................................................. 273

9.2.8 Deep Standby Interrupt Flag Register (DPSIFR) ...................................................................... 274

9.2.9 Deep Standby Interrupt Edge Register (DPSIEGR).................................................................. 276

9.2.10 Reset Status Register (RSTSR) ................................................................................................. 277

9.2.11 Deep Standby Backup Register (DPSBKRy) (y = 0 to 31)....................................................... 279

9.3 Multi-Clock Function ........................................................................................................... 2809.4 Module Stop Function......................................................................................................... 2809.5 Low Power Consumption Modes........................................................................................ 281

9.5.1 Sleep Mode................................................................................................................................ 281

9.5.1.1 Transition to Sleep Mode ................................................................................................ 281

9.5.1.2 Canceling Sleep Mode ..................................................................................................... 281

9.5.2 All-Module Clock Stop Mode ................................................................................................... 282

9.5.2.1 Transition to All-Module Clock Stop Mode ................................................................... 282

9.5.2.2 Canceling All-Module Clock Stop Mode ........................................................................ 283

9.5.3 Software Standby Mode ............................................................................................................ 284

9.5.3.1 Transition to Software Standby Mode ............................................................................. 284

9.5.3.2 Canceling Software Standby Mode ................................................................................. 285

9.5.3.3 Setting Oscillation Settling Time after Software Standby Mode is Canceled ................. 286

9.5.3.4 Example of Software Standby Mode Application ........................................................... 287

9.5.4 Deep Software Standby Mode................................................................................................... 288

9.5.4.1 Transition to Deep Software Standby Mode ................................................................... 288

9.5.4.2 Canceling Deep Software Standby Mode ........................................................................ 289

9.5.4.3 Pin States when Deep Software Standby Mode is Canceled ........................................... 290

9.5.4.4 Setting Oscillation Settling Time after Deep Software Standby Mode is Canceled ....... 291

9.5.4.5 Canceling Deep Software Standby Mode by USB .......................................................... 292

9.5.4.6 Example of Deep Software Standby Mode Application ................................................. 292

9.5.4.7 Flowchart to Use Deep Software Standby Mode ............................................................ 294

9.6 BCLK and SDCLK Output Control ...................................................................................... 2959.7 Usage Notes....................................................................................................................... 296

9.7.1 I/O Port States............................................................................................................................ 296

9.7.2 Module Stop State of the DMACA, DTC, EXDMAC, and EDMAC....................................... 296

9.7.3 On-Chip Peripheral Module Interrupts...................................................................................... 296

9.7.4 Write-Access to MSTPCRA, MSTPCRB, and MSTPCRC...................................................... 296

9.7.5 Input Buffer Control by DIRQnE Bit (n = 3 to 0) ..................................................................... 296

9.7.6 Conflict between Transition to Deep Software Standby Mode and Interrupt ........................... 296

9.7.7 Timing of Wait Instructions ...................................................................................................... 296

10. Exceptions .................................................................................................................................... 29710.1 Types of Exceptions ........................................................................................................... 297

10.1.1 Undefined Instruction Exception............................................................................................... 298

10.1.2 Privileged Instruction Exception ............................................................................................... 298

10.1.3 Access Exceptions ..................................................................................................................... 298

10.1.4 Floating-Point Exceptions ......................................................................................................... 298

10.1.5 Reset .......................................................................................................................................... 298

10.1.6 Non-Maskable Interrupt ............................................................................................................ 298

10.1.7 Interrupts.................................................................................................................................... 298

10.1.8 Unconditional Trap.................................................................................................................... 298

10.2 Exception Handling Procedure ........................................................................................... 29910.3 Acceptance of Exceptions .................................................................................................. 301

10.3.1 Timing of Acceptance and Saved PC Values............................................................................ 301

10.3.2 Vector and Site for Saving the Values in the PC and PSW....................................................... 302

10.4 Hardware Processing for Accepting and Returning from Exceptions ................................. 30310.5 Hardware Pre-Processing................................................................................................... 304

10.5.1 Undefined Instruction Exception............................................................................................... 304

10.5.2 Privileged Instruction Exception ............................................................................................... 304

10.5.3 Floating-Point Exceptions ......................................................................................................... 304

10.5.4 Access Exceptions ..................................................................................................................... 304

10.5.5 Reset .......................................................................................................................................... 304

10.5.6 Non-Maskable Interrupt ............................................................................................................ 304

10.5.7 Interrupts.................................................................................................................................... 306

10.5.8 Unconditional Trap.................................................................................................................... 306

10.6 Return from Exception Processing Routines ...................................................................... 30710.7 Order of Priority for Exceptions........................................................................................... 307

11. Interrupt Control Unit (ICUa) ......................................................................................................... 30811.1 Overview ............................................................................................................................ 30811.2 Register Descriptions.......................................................................................................... 310

11.2.1 Interrupt Request Register i (IRi) (i = interrupt vector number) ............................................... 320

11.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) ............................................... 322

11.2.3 Interrupt Priority Register m (IPRm) (m = 00h to 8Fh) ............................................................ 323

11.2.4 Fast Interrupt Register (FIR) ..................................................................................................... 324

11.2.5 Software Interrupt Activation Register (SWINTR)................................................................... 325

11.2.6 DTC Activation Enable Register n (DTCERn) (n = interrupt vector number) ......................... 326

11.2.7 DMACA Activation Source Select Register n (DMRSRn) (n = DMACA channel number) ... 327

11.2.8 IRQ Control Register n (IRQCRn) (n = 0 to 15)....................................................................... 328

11.2.9 Non-Maskable Interrupt Status Register (NMISR) ................................................................... 329

11.2.10 Non-Maskable Interrupt Enable Register (NMIER) ................................................................. 331

11.2.11 Non-Maskable Interrupt Clear Register (NMICLR) ................................................................. 332

11.2.12 NMI Pin Interrupt Control Register (NMICR).......................................................................... 333

11.3 Vector Table ....................................................................................................................... 33411.3.1 Interrupt Vector Table ............................................................................................................... 334

11.3.2 Fast Interrupt Vector.................................................................................................................. 339

11.3.3 Non-maskable Interrupt Vector ................................................................................................. 339

11.4 Interrupt Operation.............................................................................................................. 34011.4.1 Detecting Interrupts ................................................................................................................... 340

11.4.1.1 Operation of Status Flags for Edge-Detected Interrupts ................................................. 340

11.4.1.2 Operation of Status Flags for Level-Detected Interrupts ................................................ 342

11.4.2 Enabling and Disabling Interrupt Sources................................................................................. 343

11.4.3 Selecting Interrupt Request Destinations .................................................................................. 344

11.4.4 Determining Priority.................................................................................................................. 346

11.4.5 Fast Interrupt.............................................................................................................................. 346

11.4.6 External Pin Interrupts............................................................................................................... 346

11.5 Non-maskable Interrupt Operation ..................................................................................... 34711.6 Return from Power-Down States ....................................................................................... 348

11.6.1 Return from Sleep Mode ........................................................................................................... 348

11.6.2 Return from All-Module Clock Stop Mode .............................................................................. 348

11.6.3 Return from Software Standby Mode........................................................................................ 348

11.7 Usage Notes....................................................................................................................... 349

12. Buses ............................................................................................................................................ 35212.1 Overview............................................................................................................................. 35212.2 Description of Buses........................................................................................................... 354

12.2.1 CPU Buses................................................................................................................................. 354

12.2.2 Memory Buses........................................................................................................................... 354

12.2.3 Internal Main Buses................................................................................................................... 354

12.2.4 Internal Peripheral Buses........................................................................................................... 355

12.2.5 External Bus .............................................................................................................................. 356

12.2.6 Parallel Operation ...................................................................................................................... 358

12.2.7 Limitations................................................................................................................................. 358

12.3 Register Descriptions.......................................................................................................... 35912.3.1 CSn Control Register (CSnCR) (n = 0 to 7).............................................................................. 361

12.3.2 CSn Recovery Cycle Register (CSnREC) (n = 0 to 7) .............................................................. 362

12.3.3 CSn Mode Register (CSnMOD) (n = 0 to 7)............................................................................. 364

12.3.4 CSn Wait Control Register 1 (CSnWCR1) (n = 0 to 7) ............................................................ 366

12.3.5 CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 7) ............................................................ 369

12.3.6 SDC Control Register (SDCCR) ............................................................................................... 372

12.3.7 SDC Mode Register (SDCMOD).............................................................................................. 373

12.3.8 SDRAM Access Mode Register (SDAMOD)........................................................................... 373

12.3.9 SDRAM Self-Refresh Control Register (SDSELF) .................................................................. 374

12.3.10 SDRAM Refresh Control Register (SDRFCR) ......................................................................... 375

12.3.11 SDRAM Auto-Refresh Control Register (SDRFEN)................................................................ 376

12.3.12 SDRAM Initialization Sequence Control Register (SDICR) .................................................... 377

12.3.13 SDRAM Initialization Register (SDIR) .................................................................................... 378

12.3.14 SDRAM Address Register (SDADR) ....................................................................................... 380

12.3.15 SDRAM Timing Register (SDTR) ............................................................................................ 381

12.3.16 SDRAM Mode Register (SDMOD) .......................................................................................... 383

12.3.17 SDRAM Status Register (SDSR) .............................................................................................. 384

12.3.18 Bus Error Status Clear Register (BERCLR).............................................................................. 385

12.3.19 Bus Error Monitoring Enable Register (BEREN) ..................................................................... 385

12.3.20 Bus Error Status Register 1 (BERSR1) ..................................................................................... 386

12.3.21 Bus Error Status Register 2 (BERSR2) ..................................................................................... 387

12.4 Endian and Data Alignment ................................................................................................ 38812.4.1 Data Alignment Control for CS Area ........................................................................................ 388

12.4.2 Data Alignment Control for SDRAM Area............................................................................... 394

12.5 Operation of CS Area Controller......................................................................................... 40212.5.1 Timing of CS Area Access ........................................................................................................ 402

12.5.2 External Wait Function.............................................................................................................. 418

12.5.3 No Access State ......................................................................................................................... 420

12.5.4 Insertion of Recovery Cycles .................................................................................................... 420

12.5.5 Write Buffer Function ............................................................................................................... 421

12.5.6 Notes on Usage.......................................................................................................................... 422

12.6 SDRAM Area Controller Operation..................................................................................... 42412.6.1 Enabling/Disabling SDRAM Access and Setting SDRAM Bus Width .................................... 424

12.6.2 No Access State ......................................................................................................................... 424

12.6.3 Insertion of Recovery Cycles .................................................................................................... 424

12.6.4 Write Buffer Function ............................................................................................................... 425

12.6.5 SDRAM Commands.................................................................................................................. 425

12.6.6 Conditions for Setting SDRAMC Registers.............................................................................. 426

12.6.7 Self-Refresh ............................................................................................................................... 427

12.6.8 Auto-Refresh ............................................................................................................................. 430

12.6.9 Initialization Sequencer ............................................................................................................. 432

12.6.10 Read/Write Access .................................................................................................................... 433

12.6.11 Setting Mode Register ............................................................................................................... 436

12.6.12 SDRAMC Setting Examples ..................................................................................................... 437

12.6.12.1 SDRAMC Access Procedure .......................................................................................... 437

12.6.12.2 Procedure for Transition to and Recovery from Self-Refresh Mode .............................. 438

12.6.12.3 Timing Register Settings and Access Timing ................................................................. 440

12.6.13 Address Multiplexing ................................................................................................................ 449

12.6.14 Examples for Connecting with SDRAMs ................................................................................. 450

12.6.14.1 32-Bit Bus Space ............................................................................................................. 450

12.6.14.2 16-Bit Bus Space ............................................................................................................. 453

12.6.15 Restrictions ................................................................................................................................ 456

12.7 Bus Error Monitoring Section.............................................................................................. 45712.7.1 Types of Bus Error .................................................................................................................... 457

12.7.1.1 Illegal Address Access .................................................................................................... 457

12.7.1.2 Timeout ............................................................................................................................ 457

12.7.2 Operations When a Bus Error Occurs ....................................................................................... 457

12.7.3 Conditions Leading to Bus Errors ............................................................................................. 458

13. Memory-Protection Unit (MPU)..................................................................................................... 46013.1 Overview............................................................................................................................. 460

13.1.1 Types of Access Control............................................................................................................ 462

13.1.2 Regions for Access Control....................................................................................................... 462

13.1.3 Background Region ................................................................................................................... 462

13.1.4 Overlap between Regions.......................................................................................................... 462

13.1.5 Instructions and Data that Span Regions................................................................................... 462

13.2 Register Descriptions.......................................................................................................... 46313.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) .............................................. 464

13.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) ............................................... 465

13.2.3 Memory-Protection Enable Register (MPEN) .......................................................................... 466

13.2.4 Background Access Control Register (MPBAC) ...................................................................... 467

13.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) .............................................. 468

13.2.6 Memory-Protection Error Status Register (MPESTS) .............................................................. 469

13.2.7 Data Memory-Protection Error Address Register (MPDEA).................................................... 470

13.2.8 Region Search Address Register (MPSA)................................................................................. 471

13.2.9 Region Search Operation Register (MPOPS)............................................................................ 471

13.2.10 Region Invalidation Operation Register (MPOPI) .................................................................... 472

13.2.11 Instruction-Hit Region Register (MHITI) ................................................................................. 473

13.2.12 Data-Hit Region Register(MHITD)........................................................................................... 475

13.3 Functions ............................................................................................................................ 47713.3.1 Memory Protection .................................................................................................................... 477

13.3.2 Region Search............................................................................................................................ 477

13.3.3 Protection of Registers Related to the Memory-Protection Unit............................................... 477

13.3.4 Flow for Determination of Access by the Memory-Protection Function.................................. 478

13.4 Procedures for Using Memory Protection........................................................................... 48013.4.1 Setting Access-Control Information.......................................................................................... 480

13.4.2 Enabling Memory Protection..................................................................................................... 480

13.4.3 Transition to User Mode............................................................................................................ 480

13.4.4 Processing in Response to Memory-Protection Errors.............................................................. 480

14. DMA Controller (DMACA) ............................................................................................................. 48214.1 Overview............................................................................................................................. 48214.2 Register Descriptions.......................................................................................................... 484

14.2.1 DMA Source Address Register (DMSAR) ............................................................................... 486

14.2.2 DMA Destination Address Register (DMDAR) ....................................................................... 486

14.2.3 DMA Transfer Count Register (DMCRA)................................................................................ 487

14.2.4 DMA Block Transfer Count Register (DMCRB)...................................................................... 488

14.2.5 DMA Transfer Mode Register (DMTMD)................................................................................ 489

14.2.6 DMA Interrupt Setting Register (DMINT) ............................................................................... 490

14.2.7 DMA Address Mode Register (DMAMD)................................................................................ 492

14.2.8 DMA Offset Register (DMOFR)............................................................................................... 495

14.2.9 DMA Transfer Enable Register (DMCNT)............................................................................... 496

14.2.10 DMA Software Start Register (DMREQ) ................................................................................. 497

14.2.11 DMA Status Register (DMSTS)................................................................................................ 498

14.2.12 DMA Activation Source Flag Control Register (DMCSL)....................................................... 500

14.2.13 DMA Module Start Register (DMAST).................................................................................... 501

14.3 Operation ............................................................................................................................ 50214.3.1 Transfer Mode ........................................................................................................................... 502

14.3.2 Extended Repeat Area Function ................................................................................................ 506

14.3.3 Address Update Function using Offset...................................................................................... 508

14.3.4 Activation Sources..................................................................................................................... 512

14.3.5 Activating the DMACA............................................................................................................. 514

14.3.6 Starting DMA Transfer.............................................................................................................. 515

14.3.7 Registers during DMA Transfer ................................................................................................ 515

14.3.8 Channel Priority......................................................................................................................... 517

14.3.9 Operation Timing ...................................................................................................................... 517

14.3.10 DMACA Execution Cycles ....................................................................................................... 518

14.4 Ending DMA Transfer ......................................................................................................... 51914.4.1 Transfer End by Completion of Specified Total Number of Transfer Operations.................... 519

14.4.2 Transfer End by Repeat Size End Interrupt............................................................................... 519

14.4.3 Transfer End by Interrupt on Extended Repeat Area Overflow................................................ 519

14.5 Interrupts............................................................................................................................. 52014.6 Low-Power Consumption Function..................................................................................... 52214.7 Usage Notes....................................................................................................................... 523

14.7.1 DMA Transfer to External Devices........................................................................................... 523

14.7.2 DMA Transfer to Peripheral Modules....................................................................................... 523

14.7.3 Access to the Registers during DMACA Transfer .................................................................... 523

14.7.4 DMA Transfer to Reserved Areas ............................................................................................. 523

14.7.5 Interrupt Request by the DMACA Activation Source Flag Control Register (DMCSL) at the End of each Transfer............................................................................................................ 523

14.7.6 Setting of DMACA Activation Source Select Register of the Interrupt Control Unit (ICU.DMRSRn) .............................................................................. 523

14.7.7 Suspending or Restarting DMACA Activation ......................................................................... 523

14.7.8 DMA Controller (DMACA)...................................................................................................... 523

15. EXDMA Controller (EXDMAC)...................................................................................................... 52415.1 Overview............................................................................................................................. 52415.2 Register Descriptions.......................................................................................................... 526

15.2.1 EXDMA Source Address Register (EDMSAR)........................................................................ 527

15.2.2 EXDMA Destination Address Register (EDMDAR)................................................................ 527

15.2.3 EXDMA Transfer Count Register (EDMCRA) ........................................................................ 528

15.2.4 EXDMA Block Transfer Count Register (EDMCRB).............................................................. 530

15.2.5 EXDMA Transfer Mode Register (EDMTMD)........................................................................ 531

15.2.6 EXDMA Output Setting Register (EDMOMD)........................................................................ 532

15.2.7 EXDMA Interrupt Setting Register (EDMINT)........................................................................ 533

15.2.8 EXDMA Address Mode Register (EDMAMD)........................................................................ 535

15.2.9 EXDMA Offset Register (EDMOFR)....................................................................................... 539

15.2.10 EXDMA Transfer Enable Register (EDMCNT) ....................................................................... 540

15.2.11 EXDMA Software Start Register (EDMREQ).......................................................................... 541

15.2.12 EXDMA Status Register (EDMSTS) ........................................................................................ 542

15.2.13 EXDMA External Request Sense Mode Register (EDMRMD) ............................................... 544

15.2.14 EXDMA External Request Flag Register (EDMERF).............................................................. 545

15.2.15 EXDMA Peripheral Request Flag Register (EDMPRF) ........................................................... 546

15.2.16 EXDMA Module Start Register (EDMAST) ........................................................................... 547

15.2.17 Cluster Buffer Register i (CLSBRi) (i = 0 to 6) ........................................................................ 548

15.3 Operation ............................................................................................................................ 54915.3.1 Transfer Mode ........................................................................................................................... 549

15.3.2 Extended Repeat Area Function ................................................................................................ 555

15.3.3 Address Update Function using Offset...................................................................................... 557

15.3.4 Address Modes .......................................................................................................................... 561

15.4 Transfer Operation.............................................................................................................. 56215.4.1 Normal/Repeat Transfer Operation ........................................................................................... 562

15.4.2 Block Transfer Operation .......................................................................................................... 564

15.4.3 Cluster Transfer Operation ........................................................................................................ 566

15.5 Activation Sources and Procedures for Activation.............................................................. 56915.5.1 Activation Sources..................................................................................................................... 569

15.5.2 Activating the EXDMAC .......................................................................................................... 571

15.5.3 Starting DMA Transfer.............................................................................................................. 572

15.5.4 Registers during DMA Transfer ................................................................................................ 572

15.5.5 Channel Priority......................................................................................................................... 573

15.6 Ending DMA Transfer ......................................................................................................... 57415.6.1 Transfer End by Completion of Specified Total Number of Transfer Operations.................... 574

15.6.2 Transfer End by Repeat Size End Interrupt............................................................................... 575

15.6.3 Transfer End by Interrupt on Extended Repeat Area Overflow................................................ 575

15.7 Interrupts............................................................................................................................. 57615.8 Low-Power Consumption Function..................................................................................... 57815.9 EDACK Operation in Single Address Mode........................................................................ 579

15.9.1 EDACK Operation Example in Normal-Transfer (CS Area) Single Address Mode ................ 579

15.9.2 EDACK Operation Example in Normal-Transfer (SDRAM Area) Single Address Mode....... 581

15.9.3 EDACK Operation Example in Block-Transfer (CS Area) Single Address Mode................... 583

15.9.4 EDACK Operation Example in Block-Transfer (SDRAM Area) Single Address Mode ......... 585

15.10 Usage Notes....................................................................................................................... 58815.10.1 Cluster Buffers........................................................................................................................... 588

15.10.2 Access to the Registers during DMA Transfer.......................................................................... 588

15.10.3 DMA Transfer to Reserved Areas ............................................................................................. 588

16. Data Transfer Controller (DTCa)................................................................................................... 58916.1 Overview............................................................................................................................. 58916.2 Register Descriptions.......................................................................................................... 591

16.2.1 DTC Mode Register A (MRA).................................................................................................. 592

16.2.2 DTC Mode Register B (MRB) .................................................................................................. 593

16.2.3 DTC Transfer Source Address register (SAR) .......................................................................... 594

16.2.4 DTC Transfer Destination Address Register (DAR)................................................................. 594

16.2.5 DTC Transfer Count Register A (CRA).................................................................................... 595

16.2.6 DTC Transfer Count Register B (CRB) .................................................................................... 596

16.2.7 DTC Control Register (DTCCR)............................................................................................... 596

16.2.8 DTC Vector Base Register (DTCVBR) .................................................................................... 597

16.2.9 DTC Address Mode Register (DTCADMOD).......................................................................... 597

16.2.10 DTC Module Start Register (DTCST)....................................................................................... 598

16.2.11 DTC Status Register (DTCSTS)................................................................................................ 599

16.3 Sources of Activation .......................................................................................................... 60016.3.1 Allocating Transfer Data and DTC Vector Table ..................................................................... 600

16.3.2 Startup source and Vector Address ........................................................................................... 602

16.4 Operation ............................................................................................................................ 60516.4.1 Transfer Data Read Skip Function ............................................................................................ 608

16.4.2 Transfer Data Write-Back Skip Function.................................................................................. 608

16.4.3 Normal Transfer Mode .............................................................................................................. 609

16.4.4 Repeat Transfer Mode ............................................................................................................... 610

16.4.5 Block Transfer Mode................................................................................................................. 611

16.4.6 Chain Transfer ........................................................................................................................... 612

16.4.7 Operation Timing ...................................................................................................................... 613

16.4.8 Execution Cycle of the DTC ..................................................................................................... 616

16.4.9 DTC Bus Mastership Release Timing ....................................................................................... 616

16.5 DTC Setting Procedure....................................................................................................... 61716.6 Examples of DTC Usage .................................................................................................... 618

16.6.1 Normal Transfer ........................................................................................................................ 618

16.6.2 Chain Transfer ........................................................................................................................... 619

16.6.3 Chain Transfer when Counter = 0 ............................................................................................. 621

16.7 Interrupt Source.................................................................................................................. 62216.8 Low-Power Consumption Function..................................................................................... 62216.9 Usage Notes....................................................................................................................... 623

16.9.1 Transfer Information Data Start Address .................................................................................. 623

16.9.2 Allocating Transfer Data ........................................................................................................... 623

16.9.3 Setting the DTC Activation Enable Register (ICU.DTCERi) of the Interrupt Control Unit .... 624

16.9.4 Selecting Communication Function Interrupt as DTC Activation Source ................................ 624

17. I/O Ports........................................................................................................................................ 62517.1 I/O Ports [for 176-Pin LFBGA] ............................................................................................ 625

17.1.1 Overview ................................................................................................................................... 625

17.1.2 Register Descriptions................................................................................................................. 632

17.1.2.1 Data Direction Register (DDR) ....................................................................................... 638

17.1.2.2 Data Register (DR) .......................................................................................................... 639

17.1.2.3 Port Register (PORT) ...................................................................................................... 640

17.1.2.4 Input Buffer Control Register (ICR) ............................................................................... 641

17.1.2.5 Open Drain Control Register (ODR) ............................................................................... 642

17.1.2.6 Pull-Up Resistor Control Register (PCR) ........................................................................ 643

17.1.2.7 Port Function Control Register 0 (PF0CSE) ................................................................... 645

17.1.2.8 Port Function Control Register 1 (PF1CSS) ................................................................... 646

17.1.2.9 Port Function Control Register 2 (PF2CSS) ................................................................... 647

17.1.2.10 Port Function Control Register 3 (PF3BUS) ................................................................... 648

17.1.2.11 Port Function Control Register 4 (PF4BUS) ................................................................... 649

17.1.2.12 Port Function Control Register 5 (PF5BUS) ................................................................... 650

17.1.2.13 Port Function Control Register 6 (PF6BUS) ................................................................... 651

17.1.2.14 Port Function Control Register 7 (PF7DMA) ................................................................. 652

17.1.2.15 Port Function Control Register 8 (PF8IRQ) .................................................................... 653

17.1.2.16 Port Function Control Register 9 (PF9IRQ) .................................................................... 654

17.1.2.17 Port Function Control Register A (PFAADC) ................................................................ 655

17.1.2.18 Port Function Control Register B (PFBTMR) ................................................................. 655

17.1.2.19 Port Function Control Register C (PFCMTU) ................................................................ 656

17.1.2.20 Port Function Control Register D (PFDMTU) ................................................................ 657

17.1.2.21 Port Function Control Register E (PFENET) .................................................................. 658

17.1.2.22 Port Function Control Register F (PFFSCI) .................................................................... 660

17.1.2.23 Port Function Control Register G (PFGSPI) ................................................................... 661

17.1.2.24 Port Function Control Register H (PFHSPI) ................................................................... 663

17.1.2.25 Port Function Control Register J (PFJCAN) ................................................................... 665

17.1.2.26 Port Function Control Register K (PFKUSB) ................................................................. 666

17.1.2.27 Port Function Control Register L (PFLUSB) .................................................................. 668

17.1.2.28 Port Function Control Register M (PFMPOE) ................................................................ 670

17.1.2.29 Port Function Control Register N (PFNPOE) ................................................................. 671

17.1.3 Settings of Ports......................................................................................................................... 672

17.1.4 List of Output Enable Settings................................................................................................... 673

17.1.5 Treatment of Unused Pins ......................................................................................................... 693

17.2 I/O Ports [for 145-Pin TFLGA/144-Pin LQFP]..................................................................... 69417.2.1 Overview ................................................................................................................................... 694

17.2.2 Register Descriptions................................................................................................................. 700

17.2.2.1 Data Direction Register (DDR) ....................................................................................... 706

17.2.2.2 Data Register (DR) .......................................................................................................... 707

17.2.2.3 Port Register (PORT) ...................................................................................................... 708

17.2.2.4 Input Buffer Control Register (ICR) ............................................................................... 709

17.2.2.5 Open Drain Control Register (ODR) ............................................................................... 710

17.2.2.6 Pull-Up Resistor Control Register (PCR) ........................................................................ 711

17.2.2.7 Port Function Control Register 0 (PF0CSE) ................................................................... 713

17.2.2.8 Port Function Control Register 1 (PF1CSS) ................................................................... 714

17.2.2.9 Port Function Control Register 2 (PF2CSS) ................................................................... 715

17.2.2.10 Port Function Control Register 3 (PF3BUS) ................................................................... 716

17.2.2.11 Port Function Control Register 4 (PF4BUS) ................................................................... 717

17.2.2.12 Port Function Control Register 5 (PF5BUS) ................................................................... 718

17.2.2.13 Port Function Control Register 6 (PF6BUS) ................................................................... 719

17.2.2.14 Port Function Control Register 7 (PF7DMA) ................................................................. 720

17.2.2.15 Port Function Control Register 8 (PF8IRQ) .................................................................... 721

17.2.2.16 Port Function Control Register 9 (PF9IRQ) .................................................................... 722

17.2.2.17 Port Function Control Register A (PFAADC) ................................................................ 723

17.2.2.18 Port Function Control Register B (PFBTMR) ................................................................. 724

17.2.2.19 Port Function Control Register C (PFCMTU) ................................................................ 725

17.2.2.20 Port Function Control Register D (PFDMTU) ................................................................ 726

17.2.2.21 Port Function Control Register E (PFENET) .................................................................. 727

17.2.2.22 Port Function Control Register F (PFFSCI) .................................................................... 729

17.2.2.23 Port Function Control Register G (PFGSPI) ................................................................... 730

17.2.2.24 Port Function Control Register H (PFHSPI) ................................................................... 732

17.2.2.25 Port Function Control Register J (PFJCAN) ................................................................... 734

17.2.2.26 Port Function Control Register K (PFKUSB) ................................................................. 735

17.2.2.27 Port Function Control Register M (PFMPOE) ................................................................ 737

17.2.2.28 Port Function Control Register N (PFNPOE) ................................................................. 738

17.2.3 Settings of Ports......................................................................................................................... 739

17.2.4 List of Output Enable Settings................................................................................................... 740

17.2.5 Treatment of Unused Pins ......................................................................................................... 758

17.3 I/O Ports [for 100-Pin