Sabir Ahmed 2514-101 Avent Ferry Rd, Raleigh, NC-27606 ● +1-919-800-8489 ● sahmed12@ncsu.edu ● www.linkedin.com/in/sahmed7

SUMMARY

Graduate student looking for full-time opportunities in the fields of Computer Architecture and ASIC Design and Verification

TECHNICAL SKILLS

Programing/Scripting: C, C++, OpenCL, CUDA, Linux shell, Python

Hardware Design: Verilog, System Verilog

Full System Simulator: GPGPUSim, GEM5

API: LLVM compiler design libraries, RTX real time kernel

Tools: Synopsys Design compiler, Modelsim, GitHub, GDB, Altera OpenCL SDK, Virtuoso, HSPICE

EDUCATION

North Carolina State University May 2016 Master of Science in Computer Engineering GPA: 3.88/4.0 Delhi College of Engineering, University of Delhi May 2012 Bachelor of Engineering in Electrical Engineering GPA: 3.7/4.0

COURSE WORK:

Computer Architecture: ECE506 Architecture of Parallel Computers ECE521 Computer Design and Technology ECE706 Advanced Parallel Computer Architecture

ECE721 Advanced Microarchitecture ECE786 Advanced Computer Architecture (GPGPU)

ASIC Design and Verification: ECE520 Digital ASIC Design ECE745 ASIC Verification Software and Systems: ECE561 Embedded System Design ECE566 Code Generation and Optimization

PROJECTS

Computer Architecture: Modelling a Trace Processor with hierarchical register management system along with a Trace Cache and study the improvement over

a generic Out of Order Superscalar. Implementing Register-File Management, Register Renaming and Exception/Branch Mis-prediction Recovery in a Physical Register File

based custom Out of Order Superscalar pipeline simulator. Modelling a two level memory hierarchy (L1, L2 with Victim Cache) and study cache performance for different configurations. Modelling Bi-Modal, GShared and Hybrid branch predictors and study performance (prediction accuracy) for different configurations. Modelling a ROB based N-way Out of Order Super Scalar Pipeline and studying the performance (IPC) for different superscalar width

and issue queue size. Implementing cache coherence (MSI, MESI, MOESI, Dragon) in a given multi-core bus based memory hierarchy simulator. Implementing Full Convolution in CUDA and optimize the code with respect thread-block recuse utilization, using shared memory and

coalescing global memory accesses. Modifying GPGPUSim for evaluation of CAPRI: Prediction of Compaction Adequacy for Handling Control Divergence in GPGPU

Architecture

Modifying the SLICC coherence protocol for the RUBY memory subsystem of the GEM5 simulator to add support for Victim Migration in the Two Level MESI protocol.

Modifying the GEM5 simulator RUBY memory subsystem interface to evaluate the performance of the research paper ” Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors”

ASIC Design RTL design in Verilog and gate level synthesis for an ASIC accelerator for calculating the nodal voltages in a power system using the

Jacobi Iterative Sparse Matrix Solver.

ASIC Verification Developing a modular test bench (generator, driver, receiver and scoreboards for the given dut) and the golden reference module in

System Verilog for verifying individual pipeline stages and control path for a pipelined LC3 microcontroller.

Compiler Optimization Using LLVM for implementation of various IR level compiler code optimization passes (LICM, CSE, GCM).

INDEPENDENT RESEARCH

Currently working under Dr. Huiyang Zhou to implement the OpenCl kernels of Rodinia, a heterogeneous multicore benchmark on an FPGA using the ALTERA OpenCl SDK and study the performance and optimization bottlenecks for the same as compared to the GPU implementation.

WORK EXPERIENCE

Mahindra & Mahindra, Pune, India. Senior Engineer, Two Wheeler Research and Development (July 2012 to May 2014)

Software development and testing for AC and DC CDI systems for ignition timing control in carburetor engines.

Board level hardware design, testing and support for software development of a Two Wheeler Anti-theft System.

Embedded software and hardware prototype development and testing for proof of concept of various in-house projects.