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SMART Atmel-11217A-ATARM-SAMA5D3x-High-Speed-Simulation-Using-IBIS-Models-ApplicationNote_31-Jul-14 Scope This application note serves as a guide on how to use the I/O Buffer Information Specification (IBIS) models of Atmel ® | SMART SAMA5D3x eMPUs and the external peripherals to perform board-level simulation with the HyperLynx ® Signal Integrity (SI) software to address SI issues. The SAMA5D3 series is based on the ARM ® Cortex™-A5 Processor, with a CPU frequency of up to 536 MHz and a system speed of up to 166 MHz when interfacing with high-speed interfaces such as DDR2, LPDDR, and LPDDR2. Since the high-speed signal wires usually create SI and EMC (electromagnetic compliance) issues, if the PCB layout is not suitable to ensure SI quality, the board risks design flaws or failure to pass the CE/FCC certification. Therefore, performing PCB simulation is very important before production. Reference Documents Document Type Document Title Datasheet SAMA5D3 Series Datasheet (Atmel literature No. 11121) APPLICATION NOTE SAMA5D3x High-Speed Simulation Using IBIS Models Atmel | SMART SAMA5D3 Series

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  • SMART

    APPLICATION NOTE

    SAMA5D3x High-Speed Simulation Using IBIS Models

    Atmel | SMART SAMA5D3 Series

    Scope

    This application note serves as a guide on how to use the I/O Buffer InformationSpecification (IBIS) models of Atmel® | SMART SAMA5D3x eMPUs and theexternal peripherals to perform board-level simulation with the HyperLynx® SignalIntegrity (SI) software to address SI issues.

    The SAMA5D3 series is based on the ARM® Cortex™-A5 Processor, with a CPUfrequency of up to 536 MHz and a system speed of up to 166 MHz wheninterfacing with high-speed interfaces such as DDR2, LPDDR, and LPDDR2.Since the high-speed signal wires usually create SI and EMC (electromagneticcompliance) issues, if the PCB layout is not suitable to ensure SI quality, theboard risks design flaws or failure to pass the CE/FCC certification. Therefore,performing PCB simulation is very important before production.

    Reference Documents

    Document Type Document Title

    Datasheet SAMA5D3 Series Datasheet (Atmel literature No. 11121)

    Atmel-11217A-ATARM-SAMA5D3x-High-Speed-Simulation-Using-IBIS-Models-ApplicationNote_31-Jul-14

  • 1. SI Fundamentals and SAMA5D3x Signals

    1.1 SI Fundamentals SI

    For digital systems, signal integrity means the quality of the data pulse including the rising edge and falling edge.Generally, we can find distortion and noise when probing the data pulse, especially when the bit rate is high (e.g.,beyond 100 MHz). Signal integrity becomes important for PCB design because signal edge distortion will affect thedownstream processing. Transmission line

    At low frequencies, a trace can be viewed as a resistor. As the frequency increases, the trace begins to act like acapacitor, and when at the highest frequencies, the trace’s inductance plays a large role.

    At high frequencies, components and PCB traces are no longer ideal. They have parasitic parameters and thetraces behave as transmission lines as shown in Figure 1-1. Transmission line model

    Figure 1-1. Transmission Line Model

    The signals do not travel across the transmission line instantaneously. The propagation delay (D) down thetransmission line could be calculated by:

    where

    L = the inductance of the trace per inch

    C = the capacitor of the trace per inch to GND plane

    In air the propagation delay is about 85 ps/inch and the dielectric constant is 1.0. In FR-4 PCBs, the propagationdelay is about 140 to 180 ps/inch and the dielectric constant is 2.8 to 4.5. That means in FR-4 PCBs a striplinepropagation velocity is about 5.8 inch/ns. Characteristic impedance

    For the ideal transmission line without resistive loss, the characteristic impedance is:

    where

    L = the inductance of the trace per inch

    C = the capacitor of the trace per inch to GND plane

    The discontinuities of the impedance along the signal path will create reflections, which will degrade the signaledges.

    To decrease the reflection impact, the trace impedance should match the IC output impedance. There are severalmethods to improve it, including adding serial termination, parallel termination.

    D L C×=

    Z0 L C÷=

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  • 1.2 SAMA5D3x SignalsDDR2 I/O lines have on-die termination (ODT) and the output driver impedance value can be changed byconfiguring the value of the RIDV field in the MPDDRC I/O Calibration Register as shown in Table 1-1.

    Figure 1-2 shows the standard stub series terminated logic (SSTL) data signal of DDR2. The voltages in the figureare the following:

    VDDQ: 1.8V

    VREF: 0.9V

    VIHmin(ac): 1.15V

    VILmax(ac): 0.65V

    Table 1-1. Output Impedance Configuration

    LPDDR2 Impedance Values

    MPDDRC_IO_CALIBR.RDIV Value Name Description

    0 – Reserved

    1 RZQ_34_3 RZQ = 34.3 ohms

    2 RZQ_40 RZQ = 40 ohms

    3 RZQ_48 RZQ = 48 ohms

    4 RZQ_60 RZQ = 60 ohms

    5 – Reserved

    6 RZQ_80 RZQ = 80 ohms

    7 RZQ_120 RZQ = 120 ohms

    DDR2/LPDDR1 Impedance Values

    MPDDRC_IO_CALIBR.RDIV Value Name Description

    0 – Reserved

    1 – Reserved

    2 RZQ_33_3 RZQ = 33.3 ohms

    3 RZQ_40 RZQ = 40 ohms

    4 RZQ_50 RZQ = 50 ohms

    5 – Reserved

    6 RZQ_66_7 RZQ = 66.7 ohms

    7 RZQ_100 RZQ = 100 ohms

    3SAMA5D3x High-Speed Simulation Using IBIS Models [APPLICATION NOTE]Atmel-11217A-ATARM-SAMA5D3x-High-Speed-Simulation-Using-IBIS-Models-ApplicationNote_31-Jul-14

  • Figure 1-2. SSTL Signal Waveform

    1.3 IBIS ModelThe IBIS model gives the Input/Output Buffer Information in text format.

    It consists of a number of tables that capture the Current vs. Voltage and the Voltage vs. Time characteristics ofthe I/O buffer, as well as the values of certain parasitic components.

    As shown in Figure 1-3 and Figure 1-4, you can use HyperLynx Visual IBIS Editor to open the DDR2(MT47H128M16RT) and view the characteristics such as the rising and the falling waveforms.

    Figure 1-3. IBIS Editor

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  • Figure 1-4. View IBIS Data

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  • 2. Application ExampleThis section provides an example of how to design the PCB and how to perform simulation with the HyperLynxsimulation tool.

    The example uses a CPU board with the Atmel SAMA5D3x MPU. The critical signal is the DDR2 data line.

    The following sequence describes the steps for design and simulation:Step 1. Schematic design

    The schematic shown in Figure 2-1 is from the SAMA5D3x-CM (computer module), which expands the DDR2 capacity to 512 MB by combining two DDR2 devices (MT47H128M16RT).

    Figure 2-1. DDR2 SDRAM Schematic

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  • Step 2. PCB design

    Allegro® PCB Designer is a PCB design tool from Cadence®.

    Figure 2-2 shows the PCB design of the CPU board with Allegro PCB Editor where the two DDR2 chips are placed close to the SAMA5D3x device.

    Figure 2-2. Allegro PCB

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  • Step 3. Translate PCB board file to simulation file

    The SI simulation tool from Mentor Graphics® has the functions of PCB board simulation and IBIS model edit.

    Run HyperLynx and open the SAMA5D3X-CM_REVD.brd file, and then translate it to SAMA5D3X-CM_REVD.hpy file for simulation as shown in Figure 2-3.

    Figure 2-3. Board File Translation

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  • Step 4. Select the signal to simulateStep 4.1. Open the SAMA5D3X-CM_REVD.hyp file.

    Figure 2-4. Open Hyp File

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  • Step 4.2. Select the signal you want to simulate (e.g., DDR2 DQS0).

    Figure 2-5. Select Signal

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  • Step 5. Assign IBIS model for ICs

    The IBIS model (.ibs file) can usually be found on the manufacturer’s website. After downloading the model, add it to the HyperLynx lib path, afterwhich it can be selected in the list as shown in Figure 2-6.

    Figure 2-6. Assign IBIS Model

    11SAMA5D3x High-Speed Simulation Using IBIS Models [APPLICATION NOTE]Atmel-11217A-ATARM-SAMA5D3x-High-Speed-Simulation-Using-IBIS-Models-ApplicationNote_31-Jul-14

  • Step 6. Export the selected signal to the free-form schematic and configure the stackup information.

    Figure 2-7. Free Form SCH

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  • Step 7. Configure and start the simulation.

    Set the frequency to 166 MHz and the Duty to 50% (see Figure 2-8).

    Figure 2-8. Waveform 1

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  • Step 8. Compare and analyze the results by changing parameters

    In the previous steps, we set the SAMA5D3x output impedance to 50 ohm and we can see that the rising edge cannot reach the required level, due to the mismatch between the trace impedance and the IC output impedance. The two blue dotted horizontal lines closest to the VREF (900 mV) in Figure 2-9 are the DDR2 input thresholds.

    To make the impedance more matchable, we change the trace impedance from 29.5 ohm (green line) to 49.8 ohm (red line). When comparing the two results, we can see that the red waveform reaches the required level whereas the green waveform does not.

    Figure 2-9. Waveform 2

    3. ConclusionBefore the PCB routing, we usually perform board simulation with simulation tools. Through parameteradjustments, the PCB design can be optimized so that the high-speed signal can meet the SI requirement and therisk of design flaws or EMC issues are avoided in production.

    Volta

    ge (m

    V)

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  • 4. Revision History

    Table 4-1. Revision History

    Doc. Rev. Date Changes

    A 31-Jul-14 First release

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    ScopeReference Documents1. SI Fundamentals and SAMA5D3x Signals1.1 SI Fundamentals1.2 SAMA5D3x Signals1.3 IBIS Model

    2. Application Example3. Conclusion4. Revision History