Scaling Effects in MOS Devices

7/30/2019 Scaling Effects in MOS Devices

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MOSFET models

As mentioned earlier, an enhancement mode MOSFET can be modeled as a simple

switch, through which current can flow in either direction. A slightly more

complex model could be to consider the device to act as a resistor on its output,and a capacitor at its input. More sophisticated models can be readily derived, butthe two mentioned above are useful for logic and approximate timing simulations

of the behavior of a MOS integrated circuit.

A number of circuit simulation programs have been written which allow thesimulation of MOS integrated circuits with a wide range of transistor models.

Some of the more sophisticated models have many parameters which can be

varied, and can produce quite accurate simulation results. Most of these circuitsimulators have been derived from the SPICE circuit simulation program,

developed at UCB. SPICE has 3 sophisticated models for MOS transistors, and isgenerally considered to be quite an accurate circuit simulator.

We can derive the simplest (and least accurate) of the SPICE models from simple

physics; this exercise is useful because it provides some ``rules of thumb'' for the

design of VLSI devices. In particular, it allows us to see how devices ``scale''; thatis, how important properties such as the switching speed of a transistor vary withthe linear dimensions of the transistor.

One of the most important parameters for a transistor is its ``switching time''. We

might expect this to be related to the transit time, , for a charge carrier (anelectron, for an N channel MOSFET or a hole, for a P channel MOSFET) to crossthe channel region from the source to the drain region . If we consider a transistor

as shown in Figure , the transit time, , is simply where v is the average

speed of the charge carrier.

Figure:

Under simple conditions, we can calculate the average speed, v, for a charge

carrier. If no nuclei were present in the channel region, and there was no voltageapplied between the source and the drain ( i.e., no applied electric field) across thechannel, then the average velocity would be zero. If there was an electric field in

the channel region, the charge carriers would accelerate with an
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acceleration , where e is the charge of the charge carrier, E is the

magnitude of the applied electric field, and m is the mass of the charge carrier.(The quantity e is equal in magnitude to the charge of an electron). For free charge

carriers, the average speed would be , where t is the time for the chargecarrier to travel across the channel region. In reality, however, the charge carrierswill collide with the nuclei in the channel region quite frequently. This collision isinelastic, the charge carrier gives up some of its energy to the nucleus. We will

assume that the collisions are totally inelastic, and that each collision brings thecharge carrier to a stop. The electron, therefore, accelerates only in the intervalbetween collisions with nuclei. There will be an ``average time between

collisions'', , and the average speed of the charge carrier will be given by

The parameter is called the ``mobility''; there is an ``electron mobility'', , and a

corresponding ``hole mobility``, . For silicon,

and, . (Actually, there are two types of mobility; a ``bulk''

mobility and a ``surface'' mobility. For MOSFET's, the surface mobility isimportant, and corresponds to the values quoted. For bipolar transistors, the bulk

mobility is important.)

So, the characteristic time, , for the transistor is

Although this is not a rigorous derivation, there are two important things to note:

1. The characteristic time is proportional to the square of the channellength.

2. is inversely proportional to .These are ``scaling rules'' for MOS devices, and are believed to be approximatelyvalid for device sizes (channel dimensions) down to about 0.5 microns.


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We can also calculate, approximately, some of the important electrical propertiesof the MOS transistor; e.g., the current which can flow through the channel region,

and the impedance of the channel. These will be functions of both the size of the

channel region and of the voltages applied to the gate ( ), drain ( ) and source (

) of the device.

Figure:

Referring to Figure , the charge, Q, which will be available at the oxide/channel

boundary is simply where C is the capacitance of the

capacitor formed between the gate and the substrate, is the gate-to-source

voltage, and is the threshold voltage. (The quantity is the

``effective'' voltage applied to the gate). For a parallel plate capacitor,

where A = LW is the area of the gate over the channel of width W andlength L, D is the distance between the gate and the substrate ( i.e., the oxide

thickness) and is the permittivity of the material (for .) So,

The current flowing in the channel is

(Note that this analysis neglects some important effects; for example, it implicitlyassumes that there is a uniform electric field in the entire channel region.) A moresophisticated analysis gives slightly different values for the current in the channel

region:
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in the linear (ohmic) region, and

in the saturation region. These expressions are often written in terms of the

``process transconductance parameter'', , where where is

the capacitance per unit area of the oxide. The gate capacitance .

The quantity is a SPICE parameter for MOS transistors.

We can now calculate the effective impedance of the channel region as:

if the transistor is operated in the linear region, and

in the saturation region.

The fact that the impedance, Z, for a MOS transistor is proportional to the

ratio in both their linear and saturated regions means that we can use thesetransistors as resistors; the relative resistances scale with the device size. This is

true for both P- and N- channel devices, as well as for both enhancement and

depletion mode transistors. In fact, a ``permanently turned on'' transistor is oftenused as a resistor, for example as a ``pull-up resistor'' for a logic gate, to provide a

current limit for the gate output.

We can also calculate the time constant for a transistor to charge the gate ofanother identical transistor. This time is very important, since it will be related to

the ``gate delay'' for a logic device.


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assuming that the transistor providing the charge is operating in its saturationregion. Although this result is not rigorously correct, it is worth noting that the

delay time for a transistor to switch on a second transistor has a simple relationshipto the transit time .

Figure shows a plot of the current in the channel region of a MOS

transistor , the current between the source and drain) against the potential

difference across the channel for various values of the applied gate

current, for a typical MOS transistor .

Figure:

Note that three different regions are distinguished; the ``cutoff'' region, in which

the transistor effectively passes no current; the ``linear'' region, in which the

behavior is ohmic, and the ``saturation'' region, in which the current is nearlyconstant.

Effectively, then, we have modelled the current in the channel region of a MOS

transistor (either enhancement mode or depletion mode, P- or N- channel) as

The quantity is often written as , and is called the ``gain factor'' for a

MOS transistor. Note that is proportional to .

Actually, in the saturation region, the drain current, is not completely

independent of , partly because ``depletes'' charge carriers from the

vicinity of the well as shown in Figure . This effect both shortens the effectivechannel length and adds more charge carriers to the channel region.
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Figure:

These effects, which increase the drain current are usually modelled

empirically by the parameter , the ``channel length modulation factor'', giving thefollowing expression for the saturation current

is typically quite small, . It is a Level 1 SPICE parameter. The

term is often included with the expression for in the linear region

as well, to ensure that is continuous from the linear to the saturation region.

One remaining parameter for MOS devices which can readily be derived usingsimple physical reasoning is , the threshold voltage .

We start by looking again at a schematic of the cross-section of an NMOSenhancement mode transistor, as in Figure (similar arguments apply for a PMOS

transistor.)

Figure:

Note that if no charge is applied to the gate, the source and drain regions are

separated by reverse biased PN junctions, and no current can flow between the
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where is the permittivity of silicon, q is the charge of a single charge carrier (|q|

= e, the charge of an electron), and is the density of P-type ions in thesubstrate.

The quantity of charge per unit area in the channel region due to the immobile ionswhich have been stripped of their charge carriers (in this case, ions which havebeen stripped of their mobile holes) is

The threshold is defined as , i.e., the induced surface potential is equal in

magnitude to the original, unbiased surface potential; the density of mobilenegative charge carriers (electrons) at the surface is equal to the density of holes in

the original, unbiased substrate. In effect, the channel region has been `ìnduced'' tobecome as strongly N-doped as it was originally P-doped.

In order to calculate the gate voltage required to attain threshold, we need to

know the concentration of charge carriers N in the unbiased substrate. This isnormally equal to the dopant concentration of the substrate.

We can define the equilibrium (electrostatic) potential inside a semiconductor

as

where or are the equilibrium concentrations of P or N type mobile charge

carriers ( i.e. the dopant concentration) in the substrate, and is the equilibrium

mobile charge concentration for pure (or `ìntrinsic'') silicon, at

room temperature. Note that the potential is a surface potential, possibly arisingfrom the diffusion of charge carriers across a surface. This potential is, of course,

present independent of the gate voltage . Moreover, it must be `òvercome''

by to allow conduction in the channel.

If the substrate is not biased by any ``substrate body bias'' then the

immobile charge in the depletion region at threshold is


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If the substrate is biased by a voltage between the source and body, the

surface potential required to produce inversion is , and

We can now calculate the gate voltage required to produce inversion, the threshold

voltage . The threshold voltage consists of several components:

1. A voltage , to change the surface potential and offsetthe immobile depletion layer charge . is the capacitance per unit

area of the gate oxide;

2.

A voltage representing the difference in the work function between thegate material and the channel material . For

silicon gate devices, .

3. Additional charge at the oxide-semiconductor interface due toimpurities, etc. This is modelled as .

Therefore the threshold voltage is given by

Since the last term in the previous expression is difficult to evaluate it is usual toexpress the threshold voltage as a function of the substrate bias voltage, andmeasure the unbiased threshold voltage:

where . The parameter is the zero bias threshold voltage

and is called the ``body effect coefficient factor''.

We have now derived the most important relationships used in the simplest of the

SPICE models (Level 1) of the MOS transistor. The following table lists estimates

of these parameters for the CMOS3DLM and CMOS4S processes available to us:


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Circuit simulators include the capacitance between the various elements of the

transistor as components of the models. SPICE calculates the nonlinear capacitance

between the gate and channel region. SPICE uses a set of parasitic capacitances

modeled as constant capacitors as shown in Figure , in which the parasiticcapacitors are named as in the SPICE parameter list. Also shown are the

capacitances between the source and body, and the drain and body. These are each

considered as two separate nonlinear capacitors, a bottom capacitance and asidewall capacitance, calculated from the perimeters of the source and drain areas.

Figure:
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FULL FORM OF MOBILE RELATED WORDS

1G - First Generation

2.5G - Second and a half generation

2G - Second Generation

3G - Third Generation3GPP - 3rd Generation Partnership Project

3GPP2 - 3rd Generation Partnership Project

4G - Fourth Generation

AAA - Authentication Authorization, Account

ACC - Analog Control Channel

AMPS - Advanced Mobile Phone Service

AUC - Authentication Center

BC - Billing Center

BCH - Broadcast Channel

BER - Bit Error Rate

BS - Base Station

BSC - Base Station Controller

BTS - Base Transceiver Station

CBR - Constant Bit Rate

CDG - CDMA Development Group

CDMA - Code Division Multiple Access

CDMA2000 - Code Division Multiple Access

CDR - Call Detail Record

CN - Core Network

D/R - Distance to Reuse Ratio

DAMPS - Digital Advance Mobile Phone Service

DCC - Digital Color Code

DTA - Data Transfer Adapter

DTC - Digital Traffic Channel

EDGE - Enhanced Data for Global Evolution

EDI - Electronic Data Interchange

EIR - Equipment Identity Register

ESMR - Enhanced Specialized Mobile Radio

ETACS - Extended TACS

ETDMA - Extended Time Division Multiple Access

FDD - Frequency Division Duplex

FDM - Frequency Division Multiplexing

FDMA - Frequency Division Multiple Access

FM - Frequency Modulation

FSK - Frequency Shift Keying

FTMD - Full Track Music Download

GGSN - Gateway GPRS Support Node

GMSC - Gateway Mobile Switching Center

GMSK - Gaussian Minimum Shift Keying

GPRS - General Packet Radio Service

GPS - Global Positioning System

GSM - Global System for Mobile Communication

GSN - GPRS Support Node

HLR - Home Location Register

IC - Interchange CarrieriDEN - Integrated Dispatch Enhanced Network


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IMEI - International Mobile Equipment Identity

IMSI - International Mobile Subscriber Identity

ITU - International Telecommunication Union

IVRS - Interactive Voice Response System

IWF Inter Working Function

LBS - Location-Based Services

LMR - Land Mobile Radio

MC - Message Center

MC Multi Carrier Mode

MCS - Mobile Cellular System

ME - Mobile Equipment

MIN - Mobile Identification Number

MIRS - Motorola Integrated Radio system

MSC - Mobile Station Class

MSC - Mobile Switching Center

MTS - Mobile Telephone Service

NAMPS - Narrowband Advanced Mobile Phone Service

NMT - Nordic Mobile Telephone

NPDB - Number Portability Database

NTACS - Narrowband Total Access Communication Service

PAD - Packet Assembler And Disassembler

PCM - Pulse Coded Modulation

PCN - Personal Communications Network

PCS - Personal Communication Services

PDA - Personal Digital Assistant

PDC - Personal Digital Cellular

PDSN - Packet Data Switched Network

PM - phase modulation

PM - pulse modulation

PN - Packet Number

PN - pseudorandom noise

PPDN - Public Packet Data Network

PSTN - Public Switched Telephone Network

PTT - Post Telephone and Telegraph

PTT - Push to Talk

QoS - Quality of Service

RAN - Radio Access Network

RNC - Radio Network Controller

SCH - Synchronization Channel

SDMA - Spatial Division Multiple Access

SGSN - Serving GPRS Support Node

SIM - Subscriber Identity Module

SIS - Subscriber Identity Security

SMS - Short Message Service

SMSC - Short Message Service Center

TACS - Total Access Communications System

TCH - traffic channel

TD-SCDMA - Time Division Synchronous CodTDD - Time Division Duplex


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TDMA - Time Division Multiple Access

TFT - Thin Film Transistor

TIA - Telecommunications Industry Association

UE - User EquipmentUMTS - Universal Mobile Telecommunication System

UPR - User Performance Requirements

USB - Universal Serial Bus

VLR - Visitor Location Register

VMS - Voice Mail System

WCDMA - Wideband Code Division Multiple Access

WLAN - Wireless Local Area Network

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Scaling Effects in MOS Devices