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CMOSCMOS INTEGRATED CIRCUIT DESIGN TECHNIQUESINTEGRATED CIRCUIT DESIGN TECHNIQUES
University of University of IoanninaIoannina
ClockingClockingSchemesSchemesClockingClockingSchemesSchemes
Y. Tsiatouhas
Dept. of Computer Science and EngineeringDept. of Computer Science and Engineering
OverviewOverview
CMOS Integrated Circuit Design TechniquesCMOS Integrated Circuit Design Techniques
1.1. JitterJitter‐‐Skew Skew –– ThroughputThroughput‐‐LatencyLatency
2.2. Pipeline structuresPipeline structures
3.3. Clocking schemesClocking schemes
4.4. Skew tolerant designSkew tolerant design
55 Slack BorrowingSlack Borrowing5.5. Slack Borrowing Slack Borrowing
6.6. Time stealingTime stealing
VLSI Systemsand Computer Architecture Lab
2
Clock Jitter Clock Jitter –– Clock SkewClock Skew
Clock Jitter
Clock jitter is a temporal variation (uncertainty) of the clock period at a given point in the chip. The clock period can reduce or expand on a cycle‐by‐cyclepoint in the chip. The clock period can reduce or expand on a cycle by cycle basis. Clock jitter is the inherent inaccuracy of the clock generation circuitry
(e.g. PLLs).
Clock Skew
Clock skew is a variation on the arrival time of a clock signal transition due to static mismatches and process variations in the clock paths and differences in
Clocking Schemes 3
the clock load. Clock skew is the clock inaccuracy introduced by the clock distribution network.
Clock skew is constant from cycle to cycle.
CLK
Throughput Throughput –– LatencyLatency
Throughput
Metrics for the performance evaluation of circuits / systems.
Throughput
Throughput (παραγωγικότητα) is defined as the processing rate of the input data by the circuit / system.
Equivalently, it is the data transfer rate inside the circuit. Throughput is related to the clock frequency (clock cycle).
Latency
Clocking Schemes 4
Latency (λανθάνων χρόνος) is defined as the time required by the circuit / system to complete a computation.
In case that the required computation time is available inside a clock cycle, then latency and throughput are conversely proportional between each
other.
3
Pipeline StructuresPipeline Structures
Clocking Schemes 5
RE
G
RE
G
log
a
CLK Out
RE
G
RE
G
log
a
CLK RE
G
RE
G Out
Pipeline Structures Pipeline Structures ΙΙ
InitialDesign
PipelineDesign
+ +
RE
G
R
CLK
CLKb RE
G
R
CLK
CLK
R
CLK
R
CLKb
sulog_pabs_padd_pqcorgmin, tttttT
Clocking Schemes 6
sulog_pabs_padd_pqcpipemin, tt,t,tmaxtT
3T
T
ttt
orgmin,pipemin,
log_pabs_padd_p
in case that
then
4
LogicStage
LogicStage
LogicStage r
LogicStager
CLK
D0 D1 D2 D3 D4Q0 Q4
Pipeline Structures Pipeline Structures ΙΙΙΙ
r Q1 r Q2 r Q3Stage IF
StageID
Stage EX
RegisterStage
MEM
Register
Register
Register
Register
Clock cycles
s
IF ID EX MEM
IF ID EX MEM
Clocking Schemes 7
Operations –Instructions
IF ID EX MEM
IF ID EX
IF ID
MEM
EX
SingleSingle‐‐Phase MasterPhase Master‐‐Slave ClockingSlave Clocking II
Static LogicStatic LogicRegisterRegister
SingleSingle‐‐PhasePhaseMasterMaster‐‐Slave D FlipSlave D Flip‐‐FlopFlop
Inputs Outputs
CLK
static
Flip‐Flops
Flip‐Flops
Flip‐Flops
Flip‐Flops
staticstatic
Clocking Schemes 8
Positive edge triggered D Flip‐Flops
5
SingleSingle‐‐Phase MasterPhase Master‐‐Slave Clocking IISlave Clocking II
Inputs
static
static
static
static
static
static
static
Flip‐Flops
static Outputs
Flip‐Flops
Clock Cycle Boundary
CLK
CLK
tc‐q tsetup tskew
TCLK
Tlogic
Clocking Schemes 9
overheadCLKskewsetupqcCLKiclog TTtttTT
Available Time for Logic Evaluation:
Overhead Impact in PipelinesOverhead Impact in Pipelines
InputsOutputs
CLK'
static logic
Flip‐Flops
Flip‐Flops
CLK
CLK'Tl‐totall
TCLK'
InputsOutputs
...static‐1
Flip‐Flops
Flip‐Flops
Flip‐Flops
Flip‐Flops
static‐2 static‐N‐1 static‐N
Flip‐Flops
N stages
Clocking Schemes 10
N
TT totalll
iclog overheadtotalllCLKlatency TNTTNT overheadiclogCLK TTT
CLK
CLK ...TCLK Tlogic
6
SingleSingle‐‐Phase Double Edge ClockingPhase Double Edge Clocking
Positive Dynamic LogicPositive Dynamic Logicoror
RegisterRegisterPositive Edge TriggeredPositive Edge Triggered
Concurrent Register and Subsequent Logic Activation
Inputs Outputs
CLK
ooStatic LogicStatic Logic
g ggg ggMasterMaster‐‐Slave D FlipSlave D Flip‐‐FlopFlop
Flip‐Flops
Flip‐Flops
Flip‐Flops
Flip‐Flops
Clocking Schemes 11
Negative Dynamic LogicNegative Dynamic Logicoror
Static LogicStatic Logic
RegisterRegisterNegative EdgeNegative Edge‐‐TriggeredTriggeredMasterMaster‐‐Slave D FlipSlave D Flip‐‐FlopFlop
SingleSingle‐‐Phase TwoPhase Two‐‐Level ClockingLevel Clocking
Negative Dynamic LogicNegative Dynamic Logicoror
RegisterRegisterPositive LevelPositive Level
Concurrent Logic and Subsequent Register Activation
Inputs Outputs
CLK
ooStatic LogicStatic LogicLatchLatch
Latches
Latches
Latches
Latches
Clocking Schemes 12
Positive Dynamic LogicPositive Dynamic Logicoror
Static LogicStatic Logic
RegisterRegisterNegative LevelNegative Level
LatchLatch
Skew related clock signals’overlap in subsequentlatches, may result in flush‐through problems.
7
Positive Dynamic LogicPositive Dynamic Logicoror
RegisterRegisterPositive LevelPositive Level
SingleSingle‐‐Phase TwoPhase Two‐‐Level ClockingLevel Clocking
Concurrent Register and Subsequent Logic Activation
Inputs Outputs
CLK
ooStatic LogicStatic LogicLatchLatch
Latches
Latches
Latches
Latches
Clocking Schemes 13
Negative Dynamic LogicNegative Dynamic Logicoror
Static LogicStatic Logic
RegisterRegisterNegative LevelNegative Level
LatchLatch
!DynamicLogic
MultiMulti‐‐Phase ClockingPhase Clocking
Two‐Phase Clocking
In two‐phase clocking systems two discrete clock phases are utilized, which are generated by the main clock signal at the last level of the clock g y g
distribution network.
Overlapping clock signals can be used or not. In the first case higher speeds can be achieved at the risk of increased signal integrity problems due to skew
related issues in the clock distribution.
Clocking Schemes 14
Four‐Phase Clocking
Four‐phase clocking systems utilize four discrete clock phases. In general, design techniques with more than two phases are not very common in
system development.
8
Skew Tolerant Static CircuitsSkew Tolerant Static Circuits
static
static
static
static
static
static
Latches
Latches
Latch memory mode @ low!
CLK
CLKtd‐q
TCLK
CLK_B
CLK_B
td‐q
Clocking Schemes 15
qdCLKiclog t2TT
Available Time for Logic Evaluation:
Skew Tolerant Domino Circuits ISkew Tolerant Domino Circuits I
Dynam
ic
static
Dynam
ic
static
Dynam
ic
Latches
Dynam
ic
static
Dynam
ic
static
Dynam
ic
Laches
Standard Design
Precharge @ low!
Memory @ low!
CLK
CLK
td‐q
TCLK
CLK_B
CLK_B
td‐q
tskewtskew
Clocking Schemes 16
skewqdCLKiclog t2t2TT
Available Time for Logic Evaluation:
9
Skew Tolerant Domino Circuits IISkew Tolerant Domino Circuits II
Dynam
ic
static
Dynam
ic
static
Dynam
ic
static
Dynam
ic
static
Dynam
ic
static
Dynam
ic
static
Wave‐Pipeline Design
Precharge @ low!
CLK1
CLK1
TCLK
CLK2
CLK2
phase 1 phase 2
Clocking Schemes 17
!TT CLKiclog
Available Time for Logic Evaluation:
overlap time
In the slack borrowing technique, a logic partition utilizes time left over (slack) by the previous partition.
By definition this additional time is automatically (voluntarily) surrendered without circuitry and/or clock arrival time adjustments
Slack BorrowingSlack Borrowing
without circuitry and/or clock arrival time adjustments.
This technique is suitable for use in static logic with two phase, two‐level clocking (latch‐based) designs.
•Cycle slack borrowing: permits logic to use more than one cycle time and still fitwithin a single clock cycle boundary while maintaining the overall machine cycletime The time used for logic evaluation exceeds one cycle and the machine still
Clocking Schemes 18
time. The time used for logic evaluation exceeds one cycle and the machine stillworks at speed. The slack time is borrowed from preceding cycle(s).
•Phase slack borrowing: permits logic to use more than one phase time and stillmaintain the overall machine cycle time. The time used for logic evaluation in aclock phase exceeds the clock phase time and the machine still works at speed.The slack time is borrowed from preceding phase(s).
10
Typical OperationTypical Operation
L1 phase boundaryL2 phase boundary
Clock Cycle Latch BoundaryTwo‐level double‐phaseclocking
Evaluates in L2 Evaluates in L1 phase time
Latch memory @ low!
LogicLogic
CLK1
CLK2
a b b c e d eL1 L1L2 S1a S1bS2a S2b
Clock Cycle
S2
Logic
S1
Logic
phase time phase time
Clocking Schemes 19
CLK1
CLK2
L2 phase timeL1 phase time L1 phase time
tL1ttS1S1ttS2S2 tL2
c stable
tL1
a stable b stable d stable e stable
Slack BorrowingSlack Borrowing
Evaluates in L1
h i
Evaluates in L1
h iEvaluates in L2
L1 phase boundaryL2 phase boundary
Clock Cycle Latch BoundaryTwo‐level double‐phaseclocking
Latch memory @ low!
Logic Logic
CLK1
CLK2
a b c d e f g
phase time phase timephase time
L1 L1L2 S1a S1bS2a S2b
Logic Logic
Clock Cycle
S2
Logic
S1
Logic
Clocking Schemes 20
CLK1
CLK2
L2 phase timeL1 phase time L1 phase time
a stable b stablettS2aS2a
c stablettS2bS2b
e stablettS1aS1a
f stable g stabletL1ttS1bS1btL2
d stable
Slack TimeCycle Borrowing
Slack TimePhase Borrowing
tL1
tslackL1
11
Slack BorrowingSlack Borrowing:: Clocking Issues (I)Clocking Issues (I)
The logic propagation delay within a clock cycle latch boundary is:
Cycle Slack Borrowing
1Lb1Sa1S2Lb2Sa2Sdcycle ttttttt
The clock cycle time is:
1slackL1Lb1Sa1S2Lb2Scycle ttttttt
Clocking Schemes 21
The time difference between the clock cycle latch boundary and the clock cycle time, is:
1slackLa2Scycledcycle tttt
cycle(max)dcycle
cycle(max)a2S
t5.1t
t5.0t
Slack BorrowingSlack Borrowing:: Clocking Issues (II)Clocking Issues (II)
The logic propagation delay within an L2 phase latch boundary is:
Phase Slack Borrowing
2Lb2Sa2Sphase2dL tttt
The L2 phase cycle time is:
a1S2Lb2S2pL tttt
Clocking Schemes 22
The time difference between the L2 phase latch boundary and the L2 phase cycle time, is:
a1Sa2S2pLphase2dL tttt
cycle(max)phase2dL
cycle(max)a2S
cycle(max)a1S
t0.1t
t5.0t
t5.0t
12
Dead Time and Latch Dead Time and Latch RelaunchRelaunch PenaltyPenalty
Evaluates in L1 phase time
Evaluates in L2 h i
L1 phase boundaryL2 phase boundary
Clock Cycle Latch Boundary
Evaluates in L1 phase time
Latch memory @ low!
Logic
CLK1
CLK2
a b c de f
g
phase time phase time
L1 L1L2 S1a S1bS2a S2b
Logic Logic
Clock Cycle
S2’
phase time
Clocking Schemes 23
CLK1
CLK2
L2 phase timeL1 phase time L1 phase time
a stable b stable
ttS2aS2a
c stablettS2bS2b
e stable
ttS1aS1a
f stable
g stabletL1tL2
d stable
tL1
Dead Time
trelaunch_penalty tclock_jitter + tclock_skew
Phase PartitioningPhase Partitioning
Evaluates in L1 phase time
L1 phase boundaryL2 phase boundary
Clock Cycle Latch Boundary
Evaluates in L2 h i Evaluates in L1
Latch memory @ low!
Logic
CLK1
CLK2
a b c df
g
phase time
L1 L1L2 S1aS2a S2b
Clock Cycle
S2’ae S2’b
phase time
e
S2’
Evaluates in L1 phase time
Clocking Schemes 24
CLK1
CLK2
L2 phase timeL1 phase time L1 phase time
a stable b stable
ttS2aS2a
c stablettS2bS2b
e stable
ttS1aS1atL2
d stable
tL1
Slack Available forCycle Borrowing
g stable
Dead Time
tL1tL1f stable
ttS2’aS2’a ttS2’bS2’b
g stable
13
Time StealingTime Stealing
In the time stealing technique, a logic partition gains evaluation time by taking (stealing) it from the next clock cycle.
It is suitable for use in dynamic logic with two‐phase clocking or in static logic withIt is suitable for use in dynamic logic with two‐phase clocking or in static logic with single phase master‐slave clocking.
The additional time is involuntarily surrendered and it is obtained by adjusting the clock edges arrival times.
•Cycle time stealing: permits logic to use more than one cycle time and still fitwithin a single clock cycle boundary while maintaining the overall machine cycle
Clocking Schemes 25
time. The time used for logic evaluation exceeds one cycle and the machine stillworks at speed. The time is stolen from the subsequent cycle.
•Phase time stealing: permits logic to use more than one phase time and stillmaintain the overall machine cycle time. The time used for logic evaluation in aclock phase exceeds the clock phase time and the machine still works at speed.The time is stolen from the subsequent phase.
TwoTwo‐‐Phase Typical Dynamic LogicPhase Typical Dynamic Logic
a b c ie f gL2 L2L2
Dyn
Cycle Boundary 2Cycle Boundary 1
dL1
h jL1
Dyn Dyn Dyn Dyn kL1
Logic L1
Logic L2
Latch memory @ low!
CLK1
CLK2
bL2 L2L2y
Log
CLK1
CLK2
L1j
L1y
Logy
Logy
Logy
LogL1
Cycle Time 2Cycle Time 1
Logic L1 Precharges Logic L1 Evaluates
Logic L2 PrechargesLogic L2 EvaluatesL2 Latch ClosedL2 Latch Closed
L2 Latch OpenL2 Latch Open
L1 Latch OpenL1 Latch Open(Transparency)(Transparency)
L1 Latch ClosedL1 Latch Closed(Memory)(Memory)
Clocking Schemes 26
CLK2
0.50.5ttcyclecycle 0.0.55ttcyclecycle 0.50.5ttcyclecycle 0.0.55ttcyclecycle 0.50.5ttcyclecycle
Two‐phase clocking dynamic logic
Logic L2 PrechargesLogic L2 Evaluates
L1 Phase TimeL2 Phase Time
(Memory)(Memory)L2 Latch OpenL2 Latch Open(Transparency)(Transparency)
(non‐overlapping clocks)
14
Time Stealing Time Stealing –– Dynamic Logic IDynamic Logic I
a b c ie f gDyn d h jDyn Dyn Dyn Dyn kL2 L2L2L1 L1 L1
Cycle Boundary 2Cycle Boundary 1Latch memory @ low!
CLK1
CLK2
byLog
CLK1
CLK2
jyLog
yLog
yLog
yLog
L2 L2L2L1 L1 L1
Cycle Time 2Cycle Time 1
Evaluation Overlap
Modified Clocks
Clocking Schemes 27
CLK2
0.5*t0.5*tcyclecycle 0.70.7ttcyclecycle 0.50.5ttcyclecycle 0.30.3ttcyclecycle 0.50.5ttcyclecycle
Phase Time Stealing
Cycle Time Stealing
Two‐phase clocking dynamic logic
0.40.4ttcyclecycle
Dead Time
Time Stealing Time Stealing –– Dynamic Logic IIDynamic Logic II
a b c ie f gDyn d h jDyn Dyn Dyn Dyn kL2 L2L2L1 L1 L1
Cycle Boundary 2Cycle Boundary 1Overlap Fixing
CLK1
CLK2
byLog
CLK1
CLK2
jyLog
yLog
yLog
yLog
L2 L2L2L1 L1 L1
Cycle Time 2Cycle Time 1
Original Edges
Modified clocks
Clocking Schemes 28
CLK2
0.50.5ttcyclecycle 0.70.7ttcyclecycle 0.50.5ttcyclecycle 0.30.3ttcyclecycle 0.50.5ttcyclecycle
Phase Time Stealing
Cycle Time Stealing
Two‐phase clocking dynamic logic
15
Time Stealing Time Stealing –– MasterMaster‐‐Slave FlipSlave Flip‐‐FlopsFlops
a b ec d
Cycle 1
f g
Cycle 2 Cycle 3
tatic
p‐Flops
tatic
p‐Flops
tatic
p‐Flops
p‐Flops
CLK
CLK
Cycle
Cycle 1 Cycle 2 Cycle 3
Modified clockst
Flip st
Flip st
Flip
Flip
Clocking Schemes 29
ttcyclecycle 1.21.2ttcyclecycle 0.80.8ttcyclecyclettcyclecycle ttcyclecycle
Cycle Time Stealing
Static logic with single‐phase edge triggered (master‐slave flip‐flop) clocking
a c e gb d f
ReferencesReferences
• “High Speed CMOS Design Styles,” K. Bernstein et al, Kluwer, 1999.
• “Skew‐Tolerant Circuit Design,” D. Harris, Morgan Kaufmann Pub., 2001.
• “Digital Integrated Circuits: A Design Perspective,” J.M. Rabaey, A. Chandrakasan and B.g g g p , y,Nikolic, Prentice Hall, 2003.
• “CMOS VLSI Design: A Circuits and Systems Perspective,” N. Weste and D. Harris,Addison Wesley, 2011.
Clocking Schemes 30