Embed Size (px)
DESCRIPTION
In this paper a CMOS NAND gate layout has been designed and simulated using 90 nm technology. The layout has been designed using two approaches namely fully automatic and semicustom. In fully automatic technique NAND gate schematic is developed which is converted into its equivalent verilog file for automatic layout generation. In semicustom technique layout has been developed manually to optimize area and power. It can be observed from the simulated results that semicustom layout results in 74% saving in area consumption by consuming almost same power as compared to fully automatic design.
Citation preview
Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 120
Semi-custom Layout Design and Simulation ofCMOS NAND Gate
Aseemjot BrarStudent, Department of Electronics & Communication Engineering,
Jasdev Singh Sandhu Institute of Engineering and Technology Kauli, Patiala, Punjab, [email protected]
Abstract:-In this paper a CMOS NAND gate layout has beendesigned and simulated using 90 nm technology. The layouthas been designed using two approaches namely fullyautomatic and semicustom. In fully automatic techniqueNAND gate schematic is developed which is converted into itsequivalent verilog file for automatic layout generation. Insemicustom technique layout has been developed manually tooptimize area and power. It can be observed from thesimulated results that semicustom layout results in 74%saving in area consumption by consuming almost same poweras compared to fully automatic design.
Keywords: VLSI, CMOS Technology, layout, area.
1. INTRODUCTIONIn this paper, new methods for area reduction in 90 nmtechnology have been proposed. The reinforcement ofintegrated circuits is challenged by higher area and powerconsumption [1]. Emerging need for miniaturization isresponsible for attraction of attention to high performanceVLSI designing. Therefore trading off power and areaperformance in nanometer scale integrated circuits is alsobecoming popular [2]. Scaling increases speed,performance and reduces area and power consumption [1].Due to explosive growth of VLSI industry, the demand ofarea efficient devices has increased. As NAND gate isbasic circuit element so such demands can be fulfilled [3].MICROWIND provides both front end and back end VLSIcircuit designing. In front end it has DSCH in whichschematic is designed at gate level and transistor level anda verilog file is generated in DSCH and further verilog fileis compiled by MICROWIND back end designing tool toreduce area. In this paper two design flows are used forimplementing NAND gate. NAND gate is designed usingtwo techniques namely, fully automatic and semicustom.In fully automatic design DSCH 3.1 was used to designschematic of NAND gate and its behavior was simulated.Using verilog based netlist file the layout of simulatedNAND gate is generated which is later simulated usingMICROWIND 3.1 to analyze the performance. The DSCH3.1 provides user friendly environment for logic design andfast simulation with delay analysis [4]. DSCH 3.1 is usedas logic circuit designer. MICROWIND designs andsimulates the circuits at layout level. The MICROWINDtools feature enhanced editing commands, different viewsand an analog simulator. The MICROWIND providesDRC to check each and every step for proper designing insemicustom layout diagram [5]. A logic gate is an essentialphysical device that implements a Boolean function. Theyare significant building block for efficient performance ofcircuits [6].
2. NAND LOGICFig 1 show a two input CMOS NAND gate. It consist oftwo series n-MOS transistors between output Y and GNDand two parallel p-MOS transistors between output Y andVdd. If either A or B is ‘0’ at least one of the n-MOStransistors will be OFF, breaking the path from output Y toGND. But at least one of the p-MOS transistors will be ONcreating a path from output Y to Vdd. Hence, the output Ywill be 1. If both inputs are ‘1’ both the n-MOS transistorswill be ON and both of the p-MOS transistors will be OFF.Hence the output will be ‘0’ [7]. The truth table is givenbelow in table 1.
Fig 1 CMOS NAND gate
Table 1 Truth table of NAND gate
A B Pulldownnetwork
Pull upnetwork
OutputY
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0
3. NAND LOGIC SCHEMATICThe schematic design of the NAND gate is created usingtransistor in DSCH 3.1. When the circuit is constructed itis simulated and we get the schematic output. Schematic ofNAND gate is shown in Fig 2.
Fig 2 Fig 2 DSCH Schematic of NAND gate
Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
121 NITTTR, Chandigarh EDIT-2015
The output of the schematic can be verified using timingdiagram option available in DSCH as shown in Fig 3.
Fig 3 Timing diagram of NAND gate
The equivalent verilog file of the stimulated NAND gate iscreated in DSCH as shown in the Fig 4.
Fig 4 Verilog file of NAND gate
4. Layout Design SimulationsAfter creating verilog file it is compiled in theMICROWIND. After compiling verilog file fullyautomatic layout is generated on the screen as shown inFig 5.
Fig 5 Fully automatic layout of NAND gate
The output is driven using analog simulation as shown inFig 6. The analog simulated graph shows the powerconsumption. Different characteristic parameters of NANDgate can also be seen in the analog simulation.
Fig 6 Analog Simulation of automatic generated NAND gate
The parameters like area can be checked using propertiesoption. So to reduce area size semicustom design flow isused. In this design flow schematic part is eliminated. 90nm foundry is selected. The semicustom layout isgenerated using inbuilt n-MOS and p-MOS from layoutgenerator in palette. The semicustom layout of NAND gateis shown in Fig 7.
Fig 7 Semicustom Layout of NAND gate
Input connections are made using polysilicon and outputusing metal contact. This design flow leads to areareduction. The output is driven using analog simulation asdisplayed in Fig 8.
Fig 8 Analog simulation of Semicustom design of NAND gate..
5. Comparison of ParametersIn this analysis the comparison between the parameters ofthe two layout techniques is done that is fully automaticand semicustom. The comparison of parameters in tabularform is shown below in Table 2.
Table 2 Comparison of Parameters
Parameter Automaticdesign flow
Semicustomdesign flow
Width (µm) 5.7(µm) 2.7(µm)Height (µm) 5.0((µm) 2.8(µm)Area(µm²) 28.5(µm²) 7.4(µm²)Power ((µW)
1.666(µW)1.704(µW)
Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 122
Bar chart representation of the parameters
The bar chart depicts that the area is reduced by usingsemicustom technique by using almost same power.
5. CONCLUSIONThis paper presents fully automatic and semicustomtechniques to optimize area and power in VLSI design.The layout of NAND gate has been designed andsimulated using above mentioned techniques for area andpower comparison. Both the layouts have been simulatedusing 90 nm technology. The simulated results show thatsemicustom technique based NAND layout consumes 7.4µm² area as compared to 28.5 µm² in case of fullyautomatic NAND gate. It can be observed from thesimulated results that semicustom NAND gate consumes1.7 µW power as compared to 1.6 µW in case of fullyautomatic NAND gate.
REFERENCES[1] Pushpa Saini, Rajesh Mehra, “Leakage Power Reduction in CMOSVLSI circuits” International Journal of Computer Applications (0975-8887), Volume 55-No. 8, October 2012[2] Dinesh Sharma and Rajesh Mehra, “Low Power,Delay Optimized,Buffer Design using 70 nm CMOS Technology, International Journal ofComputer Applications (0975-8887), Volume 22-No. 3, May 2011.[3] Anjali Sharma, Richa Singh, Pankaj Kajla, “Area Efficient 1-BitComparator Design by using Hybridized Full Adder Module based onPTL and GDI Logic, Volume 82-No. 10, November 2013.[4] Meena Aggarwal, Aastha Aggarwal, Mr. Rajesh Mehra, “4-InputDecimal Adder Using 90 nm CMOS Technology”, IOSR Journal ofEngineering (IOSRJEN) e-ISSN:2250-3021,p-ISSN:2278-8719,VOL.3,Issue 5(May. 2013), || v4 || PP 48-51.[5] Prem Chandra Gupta, Rajesh Mehra, “Design of 8-Bit ALU usingMicrowind 3.1, International Journal of Advanced Engineering Researchand Technology (IJAERT), Volume 2, Issue 2, May 2014, ISSN No.:2348-8190.[6] Vibha Soni, Nitin Naiyar, “Evaluation of Logic Families using NORand NAND Logic gates”,International Journal of Engineering andInnovative Technology (IJEIT), Volume 3, Issue 7, January 2014.[7] Neil Weste and David Harris, CMOS VLSI Design, Circuit and
System perspective, edition 3, Pg no. 8.
AcknowledgmentThis research paper is made possible through the help and supportfrom everyone including parents, teachers and friends. EspeciallyI want to dedicate my acknowledgement of gratitude towards thefollowing significant advisors and contributors.Firstly and foremost I would like to thank Mr. Rajesh Mehra forhis support, encouragement and to read my research paper and toprovide valuable guidance. The product of this research paperwould not be possible without all of them.
05
1015202530
Automatic
Semicustom
