Semiconductor Technology: Trends, Challenges, & Opportunitiestheconfab.com/wp-content/uploads/2014/confab14_patton.pdf · assistance systems. Ultra Hi-ResTVs. Sony 4K ... Global mobile

1 © 2014 IBM Corporation

June 2014

Semiconductor Technology: Trends, Challenges, & Opportunities

Dr. Gary PattonVice President, IBM Semiconductor Research & Development CenterIEEE Fellow

2 Dr. Gary Patton © 2014 IBM Corporation

Key Trends at Biggest Consumer & Mobile Shows

MobilityAudi traffic assist:self-driving

Connected Cars

In your car this year

BMW ConnectedDrive:Smart apps, touch services & assistance systems

Ultra Hi-ResTVs

Sony 4K Ultra HD TVs

Sony Xperia 2 smartphone w/

4K video recordingPanasonic 4K screen

w/voice & face recognition

Avg. broadband access rate will need to

increase >2xto take full advantage

New / Bigger Smartphones,

Cheap Smartphones

Samsung, Sony, LG, Nokia, Blackberry and [insert name here]

all launch new models

Mozilla/Spreadtrum: $25 smartphone

Internet

OfThings

Pebble Steel Watches that interface to smartphones

LG Lifeband Fitness tracking with heart rate earphones

Memoto's Wearable cameras

+Wearable Devices

2.7 billionEstimated number of people on

the internet in 2013

6.8 billionEstimated number of mobile phone

subscribers worldwide

5.9 billionNumber of RFID tags that will be embedded into our

world and across entire ecosystems by 2013

1.5 exabytes (1018)/monthGlobal mobile data traffic in 2013… 2x that of 2012 and

12x size of whole internet in 2000. Expect 16 exabyte/month by 2018

130 per dayNumber of texts the average

18-24 year-old sends & receives

12.5 billionNumber of connected devices in the world,

constituting an “internet of things”. Expect 30 billion in 2020


Milestones in Our Industry1964 Solid Logic Tech. …………

IBM System 360The machine that defined the computer industry and the modern IBM

1964 - TransistorSLT module 6 transistors, 4 resistors

2014 – POWER8 Processor22nm SOI eDRAM technology, 650mm2

12 cores and 96MB of on-chip memory4.2 billion transistors

IBM POWER8 SystemsOpen Innovation for Big Data, Cloud, and Analytics

2014 22nm CMOS Tech.


Technology Inside a Smartphone

Applications processors

Digital baseband processors

Memory

Power control

Cellular transceivers /Analog baseband

Switch

TV tuner

PAPA

PAPA

Antenna tuner

Wi-Fi switch /

LNA

PA

Power

managem

ent Memory

Wireless SoC transceiver

(GPS, BT, Wi-Fi)

Cellular Front-End Module (FEM) Increasing bandwidth driven by new standards (4G/LTE) Increasing complexity driving component integration and

performanceKey technologies: RF CMOS, RF SOI, & SiGe

Wi-Fi FEM Becoming a standard on most phones to help offload data demand on base stations

Key technologies: RF CMOS, RF SOI, & SiGe

Processor Back-End Module & Power ManagementKey technologies: 32/28 nm HKMG SOCHV CMOS

Source:http://www.samsung.com/global/business/semiconductor/minisite/Exynos/products4quad.html

Source: http://www.ual.es/~vruiz/docencia/Apuntes/Networking/Technologies/Summary/Mobile_phone_evolution.jpg


Silicon Technology ScalingP

erfo

rman

ce, D

ensi

ty

1990 2000 20202010

Portable ComputingInternet Connectivity

Gate Oxide Limit

Planar CMOS

Planar Device Limit

Personal CommunicationsSmart Consumer Electronics

Planar CMOS w/ material & memory

innovations

Mobile ComputingInternet of Things

Atomic Dimension Limit

3D devices & 3D chip stacking,

Design-Tech Co-Optimization

Wearable ComputingEverything/Everywhere Connectivity

Cognitive Computing

Nanowire devices, 3D multi-chip stacking

& photonics


Smaller features Better performance & cost/function More applications Larger market

Driving Force: Economics

0.0001

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1

10

100

1000

1980

1985

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2015

Year

Rela

tive

Pric

e of

a T

rans

isto

r

1

10

100

1000

10000

100000

1000000

10000000

1980

1985

1990

1995

2000

2005

2010

2015

Year

Rela

tive

Cons

umpt

ion

of IC

Tra

nsis

tors

[per

198

2]


Transistor Cost Reduction Rate vs Scaling

-60

-50

-40

-30

-20

-10

0

0.55 0.

6

0.65 0.

7

0.75 0.

8

0.85 0.

9

Linear Scaling Factor x

% C

GR (c

ompo

unde

d gr

owth

rate

) in

per

-circ

uit c

ost

Semiconductor Business EconomicsWith a historical linear scaling factor of 0.7x, the circuit cost per

generation has dropped by 30 %

This image cannot currently be displayed.

Lithography Scaling

Lithography Scaling with Technology Enhancements

Reduced Scaling &Increased Complexity

Courtesy of R. Lange, IBM


Traditional scaling is reaching its limits…but the economics of Moore’s Law are still holding…

Atomsstill don’t

scaleBUT

Yes, scaling can still drive

down cost

It’s exponentially more costly to develop

Continued advances mean changing the way we think about innovation

Technical Innovation Business Model Innovation

• Innovations in Imaging, Materials, & Process to counter scaling challenges in cost-effective ways

• Close & Early Design-Technology Co-Optimization (DTCO) to squeeze every bit of scaling out of new groundrules while maintaining manufacturability

• Enable new capabilities & functionality that improve technology cost and value proposition

Innovation

• Collaborative R&D replaces independent R&D• Collaboration needs to include all functions

(semiconductor manufacturers, equipment vendors, & material suppliers)

• Shared investments / learning fostersbreakthroughs beyond what would be possible for a single company / function

Changing Innovation Requirements


Design ToolsManufacturing

IP Solutions

Manufacturing Platform

Design Services

Ecosystem

Process DevelopmentAlliance

Improving Technology Value Proposition – Collaboration

Materials

Exploratory Research

NRI

Government Partnerships

Packaging Joint Development

Tools & Equipment

Advanced Research

Computational Scaling

http://www.disco.co.jp/eg/index.html

http://www.disco.co.jp/eg/index.html


Improving Technology Value Proposition – Innovation, Collaboration, & New Approaches to “Scaling”

Vertical Devices for Improved

Scaling

Lower Cost Imaging solutions

Design Technology Co-Optimization (DTCO)

(early collaboration)

Enable New Functions & Capabilities

Traditional Pitch

Scaling


Lithography Discontinuity at 22nm: ‒ No New Tool

• Density scaling has been driven historically by 10%/year scaling of λ/NA• Discontinuity in lithography roadmap at 22nm and beyond

– EUVL is late - must extend current tool base (1.35NA, 193 nm Immersion)

100

1000

10000

1980 1985 1990 1995 2000 2005 2010

λ / N

A (n

m)

λ = 365 nmNA = 0.17

λ = 248 nm

λ = 193 nmImmersionNAmax=1.35

λ = 193 nm

NA

2 k1 λMin Pitch =

Options• Low k1 imaging

– computational scaling

• Double / Triple Pattering (DP/TP):

– increased cost

• Higher NA– materials ?

• EUV:– source ?

• eBeam– throughput ?


Lithography Scaling Challenge

Double Dipole 193ik1 = 0.28 (1.35NA)

Single Exposure EUV k1 = 0.74 (0.25NA)

ArF193nm

ImmersionArFi

193nm

DoublePatterning Immersion

ArFi193nm

EUV13.5nm

Min. Pitch =2*k1*λ / NA

0

50

100

150

200

250

90 65 45 32 22 20/14 10 7

Technology Node (nm)

Min

imu

m P

itch

(n

m)

0.0

0.1

0.2

0.3

0.4

0.5

k1 v

alu

e

Rayleigh factor k1


EUV Lithography: Comprehensive Technology Required

EUV Unique Elements vs 193i

New Wavelength (13.5nm)

High Vacuum

All Reflective Optics

Multilayer, Reflective Mask

No Pellicle

New Photoresists

22nm HP Line-Space and Contacts Patterns

EUV Scanner / Source Challenges Power and Availability

EUV Mask ChallengesDefectivity control for blanks, processed masks & in fab use

EUV Material Challenges: Resolution Line Edge Roughness Sensitivity

Required Source Power

Current ~40 W

Development ~125 W

Production ~250 W


IBM is Investing in EUVL

• Focus on understanding fundamental EUV challenges and providing manufacturing solutions

• Huge capital investment in the “EUV Center of Excellence”

• Albany’s NFX building has industry leading tooling:

– EUV mask and auxiliary wafer infrastructure operational

– EUV litho cluster readying for operation

• Strategic partnerships are in place for key EUV technologies

– Materials, inspections, process, mask, tooling, etc.


EUV Mitigation StrategyChallenges

Scalability ManufacturabiliyEase of design

Common Platform Leadership SolutionsDouble/Triple

Patterning (DP/TP) Coloring

DP/TP OptimizedDesign Flow

Sidewall Image Transfer (SIT)

DTCO Directed Self Assembly (DSA)


Guiding Patterns100nm

Poly-APoly-B

From scientific novelty to circuit-relevant patterning.

Provides higher order frequency multiplication

Block Copolymer Directed Self Assembly (DSA)


70%


N-1 Design Rule Manual

Targets for Process Team

Design Rule Manual

Targets for Design Team

1stProduct Design

Then…

Process Team‘capability’

Design Team‘need’

DTCO

Technology Architecture Optimization Design Rule Manual

- scaling targets (critical pitches)- technology features- constructs and design-rule-arcs

Now…



For Technology•Early clarity for process

definition•Better understanding of what

design will be

TechnologyNew Elements

DesignPrior node IP

Prototype designMetrics

Performance Scaling

Capability

NeedsNeeds

For Design• Optimized cost / benefit from

new technology elements

• Early view of design evolution

FinFETCapability

DTCO: highly collaborative technology definition

Focus on prototype design

Simultaneous engineering of design and technology elements

Multi-patterning


2 color solution, original architecture

3 color solution, original architecture

2 color solution, new architecture

MUX area = 1.8x MUX area = 1x1 added mask (~2% wafer cost)Complex processComplex enablement

MUX area = 1.7xRadical redesignPower/performance impact

DTCO Example 1: Collaboration of Design and Technology


DTCO Example 2: Identify Inflection Points in Cost/Complexity

0.80

0.90

1.00

1.10

1.20

1.30

1.40

404448525660646872768084

BEOL Metal Pitch

Lith

ogra

phy

Cost

per

Are

a

28 nm 16/14 nm 10 nm

Limit of Double Exposure

0.8x 0.7x 0.64x 0.5x

Limit of Single Exposure

Estimated Relative Lithography Cost-per-Die vs BEOL PitchAssuming Optical Litho with 'Pitch-Limited' Scaling


22/20 nm 14/10 nm 7 nm & Beyond

Conventional Planar Device FinFET

FDSOI

Si NanowireC Electronics

Fully Depleted Devices

Scaling beyond 20nm requires alternative device structures and new material innovations.

MaterialInnovations

SiGe FinFET

III-V FinFET

Device Research Pipeline


Gates control this. No leakage path.Have more Si and thus can carry more current.

Source

DrainGate

Gate controls this. Gate can not control below that. So current can leak through there.

PDSOI

Gate1V

Gate controls this. No leakage path.

FDSOI

Gate 1V

Leak

DrainSource

FinFET

Si

Gate 1V

Gate

DrainSource

Device Innovation – Fully Depleted Devices

Better Electrostatics Stronger Gate Control– Lower Vt for the same leakage– Shorter channel for the same Vt

Reduced Channel Doping Better SRAMs– Less doping-driven threshold fluctuation– Lower supply voltage (Vmin) – by about 150mV– Lower voltages means lower power – up to 40%


Low cost option• Planar Technology - leverages conventional

CMOS processing and design methodologies– 90% Planar Low Power (LP) Technology + 10 %

Specific elements• Reduced mask count and simpler process • Extended battery life, or smaller battery for

same duration

Key FDSOI features• Excellent short channel control• Superior performance for low-power • Undoped body → lower Vmin

Fully Depleted SOI (FDSOI) Advantages

Cheng, IEDM 2012

Gate1V


Why FinFETs?

Gate

Source

Drain

FinFET

FinFET product advantages• Fin Effect: WEFF > Physical W-footprint

– Enables high-density designs– Scaling to advanced nodes

• Low Power from low VDD operation– Low Vt due to superior gate control– Low channel doping gives low δVT

FinFET manufacturing• More complex process, but…• Self-aligned gate structure• Dense contacts to devices


Carbon nanotubes offer significant improvement on energy efficient computation compared to conventional devices and alternatives.

CNT-FETs (high speed with low power)By David Frank, IBM

CNT Power & Performance Benefits


Separating the Metallic CNTs

To meet 5nm node requirements:purity must to be << 10-4 metallic CNTs

Remove metallic-CNTsUse size-exclusion chromatography

Semi-conducting CNT move more slowlythan metallic ones

Purified sample

Before

After


Carbon Nanotube Breakthrough

CNTs controllably placed at a density of 1 billion per square centimeter More than 10,000 working carbon nanotube transistors on a single chip

for more information: New York Times, 28 Oct 2012google “IBM Press Release 39250”


The real challenge in scaling is interconnect scaling

28 25 June 2014

• Materials : Liner/barriers dominate• Physics: Edge scattering• Patterning: Restrictive geometries

Net: Interconnect resistances growing much faster than the traditional 1/k

At lower levels of the hierarchy:

Interconnects/Back End Of Line (BEOL)


Beyond Moore’s “Law” Scaling

Thinking “Outside the Box”…..

– Improving the technology value proposition without relying solely on traditional “scaling”

New features and new capabilities


Cell Size ( µ m2)

Perf

orm

an

ce (

AU

)

Leakag

e (

nA

)

0

20

40

60

80

100

00.10.20.30.40.50.001

0.01

0.1

1

10

100

SRAMs

Low leakage

eDRAM

Cell Size ( µ m2)Cell Size ( µ m2)

Perf

orm

an

ce (

AU

)

Leakag

e (

nA

)

0

20

40

60

80

100

00.10.20.30.40.50.001

0.01

0.1

1

10

100

SRAMs

Low leakage

eDRAM

Integrated Embedded Memory Solutions

Memory is 50-70% of die – key to optimizing performance & cost High Performance eDRAM delivers 3X more

memory at same die size & power 3X density benefit vs SRAM > 5X standby power benefit

Compact decoupling cap for noise reduction and I/O is a great bonus!

IBM POWER8 Processor Chip

– 650mm2 22nm SOI eDRAM technology– Twelve processor cores – 96MB on chip eDRAM shared L3– Equivalent function of 8B transistors

(vs 4B actual) due to eDRAM efficiency


Beyond Silicon: Packaging & Board Innovations

Board & package size key to additional reductions in cost, power, & performance

Interposers do this quite effectively Stacking die reduces board footprint

21 23 213 215 219 22325 29 217 221

Typical access latency in processor cycles (@ 4 GHz)


Scaling a Digital Chip with Analog Content

A monolithic mixed signal chip can get much more expensive at 45 nm

Perfect scaling

Chip SizeScaling

Actual% AnalogArea

Example of Hybrid Integration Semtech “Orioles” - IBM Cu45 ASICS + SiGe8HP (130nm) on 90nm Interposer

Inter-chip data rate: ~2Tb/secSemtech-IBM, 2010


3D Module Cross-Section

MODULE COVERTOP CHIP

LAMINATE

TOP CHIP

THINNED BOTTOM CHIP

LAMINATE

J. Golz, VLSI, © IEEE 2011 [14]

THINNED BOTTOM CHIP

Pb-FreeC4

TOP CHIP

Pb-FreeC4

Pb-FreeC4

Pb-FreeC4

32nm High-K CMOS 11 level metal Deep trench capacitor Cu Through Silicon Via (TSV)

TSV


Stacked Main Memory usingHybrid Memory Cube (HMC) Technology

Source: Micron-IBM HMC development

• 85% less active signals compared to DD3

• 90% less board space than DD4

• 72% less power than DDR4

1.28 TB/secperformance

All higher power logic functions including I/Os are localized to a single logic chip on bottom

3D TSV


BOX

Si

SOI

Optical waveguide

FET

M1

Embedding photonics with silicon FET devices

90nm Silicon Nanophotonics Technology– Performance: 25Gbps per channel– Scalability: 1 Terabit/s from 5x5 mm2 die

• integration density (10-100X) andwavelength multiplexing (4-8Ch)

– Cost efficiency: 10X cost reduction

CMOS Front End (FEOL) Photonic Integration

Advantages: Most dense integration with CMOS Very high-performance (lowest

power) photonic devices Same mask set, standard processing Same design environment (e.g.

Cadence)


Vision: Highly Integrated Logic-Memory-Photonics

Logic Plane

Logic plane: ~300 of coresMemory plane: ~30GB eDRAMPhotonic plane: On-Chip Optical Network

>1Tbps optical on-chip>1Tbps optical off-chip

Optical Switch Network

Photonic PlaneMemory Plane

Photonic layer not only connects various cores,

but also routes the traffic

3D Integration allows restructuring of the compute node to leverage dense memory and dramatically increase memory bandwidth.

37 Dr. Gary Patton © 2014 IBM CorporationMuch thinner than a sheet of paper!

Silicon substrate

Fracture front 10 mm

Everywhere Computing

Wearable electronics

Biomedical

CMOS: Improvedthermal mgmt.

Mighty electronic chips in your clothes to monitor your vitals? A tablet that folds up and fits in your back pocket?

Fastest flexible ROs to date!

18mm

Roll it thinner than a dime!

0.0 0.3 0.6 0.910-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

R=∞ R=6.3mm R=15.8mm

Dra

in C

urre

nt (

A)

Gate Voltage (V)


Summary

• Silicon scaling will continue to provide the foundation for new products

– Innovations in Imaging, Materials, & Process to counter scaling challenges in cost-effective ways

– Close & Early Design-Technology Co-Optimization (DTCO) to squeeze every bit of scaling out of new groundrules while maintaining manufacturability

• New features & capabilities will be key to maintaining a strong value proposition for future technology “nodes”

– On Silicon and Beyond Silicon


Thank You!

Documents

Semiconductor Technology: Trends, Challenges, & Opportunitiestheconfab.com/wp-content/uploads/2014/confab14_patton.pdf · assistance systems. Ultra Hi-ResTVs. Sony 4K ... Global mobile