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Seminar for Seminar for the Class of the Class of Digital Systems Digital Systems Electronics Electronics The The VHDL simulation VHDL simulation environment environment Polytechnic of Bari Polytechnic of Bari May 5 – 7, 2004 May 5 – 7, 2004 R. Antonicelli R. Antonicelli ST Belgium, Network Division ST Belgium, Network Division

Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

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Page 1: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

Seminar forSeminar for the Class of Digital the Class of Digital Systems Systems ElectronicsElectronics

The The VHDL simulation VHDL simulation environmentenvironment

Polytechnic of BariPolytechnic of BariMay 5 – 7, 2004May 5 – 7, 2004

R. Antonicelli R. Antonicelli ST Belgium, Network DivisionST Belgium, Network Division

Page 2: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

2R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

When we write down a VHDL code, When we write down a VHDL code, we must ensure a good matching we must ensure a good matching between the digital circuit and our between the digital circuit and our modelmodel

Thus, we need to check every Thus, we need to check every signal and monitor the source signal and monitor the source code step by stepcode step by step

With a simulator tool we can easily With a simulator tool we can easily reach these goalsreach these goals

What is simulation good to?

Page 3: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

3R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

ModelsimModelsim by Mentor Graphics by Mentor Graphics * * * * ** * * * * LeapfrogLeapfrog by Cadence by Cadence * * ** * * SaberSaber by Cadence by Cadence ** VSSVSS by Synopsys by Synopsys **

What simulators are often used?

Page 4: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

4R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

We discuss now about Modelsim simulator toolWe discuss now about Modelsim simulator tool

Modelsim EE/SE

Page 5: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

5R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Modelsim EE: Graphic interface

Main windowMain window

Page 6: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

6R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Wave Wave windowwindow

Modelsim EE: Graphic interface

Page 7: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

7R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Wave windowWave window

Modelsim EE: Graphic interface

Page 8: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

8R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Structure windowStructure window

Modelsim EE: Graphic interface

Page 9: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

9R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Signals windowSignals window

Modelsim EE: Graphic interface

Page 10: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

10R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Signals windowSignals window

Modelsim EE: Graphic interface

Page 11: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

11R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Variables windowVariables window

Modelsim EE: Graphic interface

Page 12: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

12R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

List windowList window

Modelsim EE: Graphic interface

Page 13: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

13R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Source windowSource window

Modelsim EE: Graphic interface

Page 14: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

14R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Create a new libraryCreate a new library

Modelsim EE: Lessons

Page 15: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

15R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Compile a modelCompile a model

Modelsim EE: Lessons

Page 16: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

16R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Load a designLoad a design

Modelsim EE: Lessons

Page 17: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

17R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Running a designRunning a design

Modelsim EE: Lessons

Page 18: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

18R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Running a designRunning a design

Modelsim EE: Lessons

Page 19: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

19R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Running a designRunning a design

Modelsim EE: Lessons

Page 20: Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of

20R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division

Managing a designManaging a design

Modelsim EE: Lessons