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Seminar forSeminar for the Class of Digital the Class of Digital Systems Systems ElectronicsElectronics
The The VHDL simulation VHDL simulation environmentenvironment
Polytechnic of BariPolytechnic of BariMay 5 – 7, 2004May 5 – 7, 2004
R. Antonicelli R. Antonicelli ST Belgium, Network DivisionST Belgium, Network Division
2R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
When we write down a VHDL code, When we write down a VHDL code, we must ensure a good matching we must ensure a good matching between the digital circuit and our between the digital circuit and our modelmodel
Thus, we need to check every Thus, we need to check every signal and monitor the source signal and monitor the source code step by stepcode step by step
With a simulator tool we can easily With a simulator tool we can easily reach these goalsreach these goals
What is simulation good to?
3R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
ModelsimModelsim by Mentor Graphics by Mentor Graphics * * * * ** * * * * LeapfrogLeapfrog by Cadence by Cadence * * ** * * SaberSaber by Cadence by Cadence ** VSSVSS by Synopsys by Synopsys **
What simulators are often used?
4R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
We discuss now about Modelsim simulator toolWe discuss now about Modelsim simulator tool
Modelsim EE/SE
5R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Modelsim EE: Graphic interface
Main windowMain window
6R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Wave Wave windowwindow
Modelsim EE: Graphic interface
7R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Wave windowWave window
Modelsim EE: Graphic interface
8R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Structure windowStructure window
Modelsim EE: Graphic interface
9R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Signals windowSignals window
Modelsim EE: Graphic interface
10R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Signals windowSignals window
Modelsim EE: Graphic interface
11R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Variables windowVariables window
Modelsim EE: Graphic interface
12R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
List windowList window
Modelsim EE: Graphic interface
13R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Source windowSource window
Modelsim EE: Graphic interface
14R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Create a new libraryCreate a new library
Modelsim EE: Lessons
15R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Compile a modelCompile a model
Modelsim EE: Lessons
16R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Load a designLoad a design
Modelsim EE: Lessons
17R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Running a designRunning a design
Modelsim EE: Lessons
18R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Running a designRunning a design
Modelsim EE: Lessons
19R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Running a designRunning a design
Modelsim EE: Lessons
20R. Antonicelli May 5-7, 2004 STMicroelectronics Belgium, Network Division
Managing a designManaging a design
Modelsim EE: Lessons