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Last updated 12 September 2002 2:29
PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SH-4 CPU CoreArchitecture
iiPRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Issued by the MCDT Documentation Group on behalf of STMicroelectronics
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility forthe consequences of use of such information nor for any infringement of patents or other rights of third parties which mayresult from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces
all information previously supplied. STMicroelectronics products are not authorized for use as critical components inlife support devices or systems without the express written approval of STMicroelectronics.
Notice:When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without Hitachi’s permission.3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons
during operation of the user’s unit according to this document.4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of
Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or otherproblems that may result from applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd.6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the
written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in lifesupport systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planningto use the products in MEDICAL APPLICATIONS.
The ST logo is a registered trademark of STMicroelectronics.
SuperH is a registered trademark for products originally developed by Hitachi, Ltd. and is owned by HitachiLtd.
© 2000, 2001, 2002 STMicroelectronics and Hitachi, Ltd. All Rights Reserved.
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PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Contents
Preface xi
1 Overview 15
1.1 SH-4 CPU core features 151.2 Block diagram 19
2 Programming model 21
2.1 General registers 222.2 System registers 252.3 Control registers 312.4 Floating-point registers 342.5 Memory-mapped registers 362.6 Data format in registers 372.7 Data formats in memory 372.8 Processor states 38
2.8.1 Reset state 382.8.2 Exception-handling state 382.8.3 Program execution state 382.8.4 Power-down state 39
2.9 Processor modes 40
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STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
3 Memory management unit (MMU) 41
3.1 Overview 413.2 Role of the MMU 413.3 Register descriptions 42
3.3.1 Page table entry high register (PTEH) 433.3.2 Page table entry low register (PTEL) 443.3.3 Translation table base register (TTB) 473.3.4 TLB exception address register (TEA) 473.3.5 MMU control register (MMUCR) 47
3.4 Address space 513.4.1 Physical address space 513.4.2 External memory space 523.4.3 Virtual address space 553.4.4 On-chip RAM space 563.4.5 Address translation 573.4.6 Single virtual memory mode and multiple virtual memory
mode 573.4.7 Address space identifier (ASID) 58
3.5 TLB functions 583.5.1 Unified TLB (UTLB) configuration 583.5.2 Instruction TLB (ITLB) configuration 593.5.3 Address translation method 59
3.6 MMU functions 623.6.1 MMU hardware management 623.6.2 MMU software management 623.6.3 MMU instruction (LDTLB) 633.6.4 Hardware ITLB miss handling 643.6.5 Avoiding synonym problems 64
3.7 Handling MMU exceptions 653.7.1 ITLBMULTIHIT 653.7.2 ITLBMISS 653.7.3 EXECPROT 66
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3.7.4 OTLBMULTIHIT 673.7.5 TLBMISS 673.7.6 READPROT 683.7.7 FIRSTWRITE 68
3.8 Memory-mapped TLB configuration 693.8.1 ITLB address array 703.8.2 ITLB data array 1 713.8.3 UTLB address array 723.8.4 UTLB data array 1 74
4 Caches 75
4.1 Overview 754.1.1 Features 75
4.2 Register descriptions 774.2.1 Cache control register (CCR) 774.2.2 Queue address control register 0 (QACR0) 804.2.3 Queue address control register 1 (QACR1) 81
4.3 Operand cache (OC) 824.3.1 Configuration 824.3.2 Read operation 844.3.3 Write operation 864.3.4 Write-back buffer 884.3.5 Write-through buffer 884.3.6 RAM mode 884.3.7 OC index mode 914.3.8 Coherency between cache and external memory 914.3.9 Prefetch operation 91
4.4 Instruction cache (IC) 924.4.1 Configuration 924.4.2 Read operation 944.4.3 IC index mode 94
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4.5 Memory-mapped cache configuration 954.5.1 IC address array 954.5.4 IC data array 974.5.5 OC address array 984.5.6 OC data array 99
4.6 Store queues 1014.6.1 SQ configuration 1014.6.2 SQ writes 1024.6.3 SQ reads (implementation dependant) 1024.6.4 Transfer to external memory 102
5 Exceptions 105
5.1 Overview 1055.2 Register descriptions 105
5.2.1 Exception event register (EXPEVT) 1065.2.2 Interrupt event register (INTEVT) 1065.2.3 TRAPA exception register (TRA) 107
5.3 Exception handling functions 1085.3.1 Exception handling flow 1085.3.2 Exception handling vector addresses 108
5.4 Exception types and priorities 1095.5 Exception flow 110
5.5.1 Exception flow 1105.5.2 Exception source acceptance 1125.5.3 Exception requests and BL bit 1145.5.4 Return from exception handling 114
5.6 Description of exceptions 1155.6.1 Resets 1155.6.2 General exceptions 1205.6.3 Interrupts 1385.6.4 Priority order with multiple exceptions 141
5.7 Usage notes 142
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6 Floating-point unit 145
6.1 Overview 1456.2 Floating-point format 146
6.2.1 Non-numbers (NaN) 1486.2.2 Denormalized numbers 149
6.3 Rounding 1496.4 Floating-point exceptions 1506.5 Graphics support functions 152
6.5.1 Geometric operation instructions 1526.5.2 Pair single-precision data transfer 154
7 Instruction set 155
7.1 Execution environment 1557.2 Addressing modes 1587.3 Instruction set summary 163
8 Instruction specification 179
8.1 Overview 1798.2 Variables and types 180
8.2.1 Integer 1808.2.2 Boolean 1818.2.3 Bit-fields 1818.2.4 Arrays 1818.2.5 Floating point values 182
8.3 Expressions 1828.3.1 Integer arithmetic operators 1828.3.2 Integer shift operators 1848.3.3 Integer bitwise operators 1848.3.4 Relational operators 1868.3.5 Boolean operators 1868.3.6 Single-value functions 187
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8.4 Statements 1908.4.1 Undefined behavior 1908.4.2 Assignment 1908.4.3 Conditional 1928.4.4 Repetition 1928.4.5 Exceptions 1938.4.6 Procedures 193
8.5 Architectural state 1948.6 Memory model 196
8.6.1 Support functions 1978.6.2 Reading memory 1988.6.3 Prefetching memory 2008.6.4 Writing memory 200
8.7 Cache model 2028.8 Floating-point model 202
8.8.1 Functions to access SR and FPSCR 2028.8.2 Functions to model floating-point behavior 2048.8.3 Floating-point special cases and exceptions 206
8.9 Abstract sequential model 2068.9.1 Initial conditions 2078.9.2 Instruction execution loop 2078.9.3 State changes 208
8.10 Example instructions 2098.10.1 ADD #imm, Rn 2098.10.2 FADD FRm, FRn 211
9 Instruction descriptions 213
9.1 Alphabetical list of instructions 213
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10 Pipelining 483
10.1 Pipelines 48310.2 Parallel executables 49010.3 Execution cycles and pipeline stalling 494
A Address list 513
B Instruction prefetch side effects 515
Index 517
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STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
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STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Preface
This document is part of the SuperH Documentation Suite detailed below.Comments on this or other manuals in the SuperH Documentation Suite should bemade by contacting your local STMicroelectronics Limited Sales Office ordistributor.
Document identification and controlEach book carries a unique identifier in the form:
ADCS nnnnnnnx
Where, nnnnnnn is the document number and x is the revision.
Whenever making comments on a document the complete identification ADCSnnnnnnnx should be quoted.
ST40 Micro Toolset Getting Started
ADCS 7379953. This manual provides an introduction to the ST40 Micro Toolsetand instructions for getting a simple OS21 application run on anSTMicroelectronics’ MediaRef platform. It also describes how to boot OS21applications from ROM and how to port applications which use STMicroelectronics’STLite/OS20 operating systems to OS21.
OS21 User’s Manual
ADCS 7358306. This manual describes the generic use of OS21 across supportedplatforms. It describes all the core features of OS21and their use and details theOS21 function definitions.It also explains how OS21 differs to STLite/OS20, the APItargeted at ST20.
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STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
OS21 for ST40 User Manual
ADCS 7358673. This manual describes the use of OS21 on ST40 platforms. Itdescribes how specific ST40 facilities are exploited by the OS21 API. It alsodescribes the OS21 board support packages for ST40 platforms.
32-Bit RISC Series, SH-4 CPU Core Architecture
ADCS 7182230. This manual describes the architecture and instruction set of theSH4-1xx (previously known a ST40-C200) core as used by STMicroelectronics.
32-Bit RISC Series, SH-4, ST40 System Architecture
This manual describes the ST40 family system architecture. It is split into fourvolumes:
ST40 System Architecture - Volume 1 System - ADCS 7153464.
ST40 System Architecture - Volume 2 Bus Interfaces - ADCS 7171720.
ST40 System Architecture - Volume 3 Video Devices - ADCS 7225754.
ST40 System Architecture - Volume 4 I/O Devices - ADCS 7225754.
Conventions used in this guide
General notation
The notation in this document uses the following conventions:
• Sample code, keyboard input and file names,
• Variables and code variables,
• Equations and math,
• Screens, windows and dialog boxes,
• Instructions.
Hardware notation
The following conventions are used for hardware notation:
• REGISTER NAMES and FIELD NAMES,
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STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
• PIN NAMES and SIGNAL NAMES.
Software notation
Syntax definitions are presented in a modified Backus-Naur Form (BNF). Briefly:
1 Terminal strings of the language, that is those not built up by rules of thelanguage, are printed in teletype font. For example, void.
2 Nonterminal strings of the language, that is those built up by rules of thelanguage, are printed in italic teletype font. For example, name.
3 If a nonterminal string of the language starts with a nonitalicized part, it isequivalent to the same nonterminal string without that nonitalicized part. Forexample, vspace-name.
4 Each phrase definition is built up using a double colon and an equals sign toseparate the two sides.
5 Alternatives are separated by vertical bars (‘|’).
6 Optional sequences are enclosed in square brackets (‘[’ and ‘]’).
7 Items which may be repeated appear in braces (‘{’ and ‘}’).
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STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
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STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
1Overview
1.1 SH-4 CPU core features1
This manual describes the architecture of the SH-4 CPU core. The core is a highlyencapsulated design component that can be integrated into any product, you willtherefore find no references to clock speeds, system facilities, pin-outs or similardata in this manual. For this information you are referred to the Datasheet and/orSystem Architecture Manual of the appropriate product.
The SH-4 is a 32-bit RISC (reduced instruction set computer) microprocessor,featuring object code upward-compatibility with Hitachi SuperH SH-1, SH-2, SH-3,and SH-3E microcomputers. It includes an instruction cache, a operand cache thatcan be switched between copy-back and write-through modes, a 4-entryfull-associative instruction TLB (translation look aside buffer), and MMU (memorymanagement unit) with 64-entry full-associative shared TLB.
The SH-4’s 16-bit fixed-length instruction set enables program code size to bereduced by almost 50% compared with 32-bit instructions.
The SH-4 200 series includes an enhanced mode which enables 2-way set associativeinstruction and operand cache (rather than direct mapped as for the SH-4 100 seriesand SH-4 200 series when running in default compatibility mode). In particular, theSH4-202 has a 32 Kbyte 2-way operand cache and a 16 Kbyte 2-way instructioncache. On power up this behaves as a 16Kbyte direct mapped operand cache and an8Kbyte direct mapped instruction cache.
1. Naming conventions:SH-4: for non-variant specific informationSH-4 100/200 series: for series specific featuresSH4-103/202: for variant specific features
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STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
The features of the SH-4 CPU core are summarized as follows:
CPU
• Original Hitachi SH architecture
• 32-bit internal data bus
• General register file:
- Sixteen 32-bit general registers (and eight 32-bit shadow registers)
- Seven 32-bit control registers
- Four 32-bit system registers
• RISC-type instruction set (upward-compatible with SH Series)
- Fixed 16-bit instruction length for improved code efficiency
- Load-store architecture
- Delayed branch instructions
- Conditional execution
• Superscalar architecture: Parallel execution of two instructions
• Instruction execution time: Maximum 2 instructions/cycle
• Virtual address space: 4 Gbytes (448-Mbyte external memory space)
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• On-chip multiplier
• Five-stage pipeline
FPU
• On-chip floating-point coprocessor
• Supports single-precision (32 bits) and double-precision (64 bits)
• Supports IEEE754-compliant data types and exceptions
• Two rounding modes: Round to Nearest and Round to Zero
• Handling of denormalized numbers: Truncation to zero or interrupt generationfor compliance with IEEE754
• Floating-point registers:
- 2 banks of sixteen 32-bit single precision registers or,
- 2 banks of eight 64-bit double precision registers or,
- 2 banks of four 128-bit vector registers (each vector is 4 single precisionelements)
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STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
• 32-bit CPU-FPU floating-point communication register (FPUL)
• Supports FMAC (multiply-and-accumulate) instruction
• Supports FDIV (divide) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution times
- Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles(double-precision)
- Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles(double-precision)
- Note: FMAC is supported for single-precision only.
• 3-D graphics instructions (single-precision only):
- 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles(pitch), 7 cycles (latency)
- 4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 4 cycles (latency)
• Five-stage pipeline
Power-down
• Power-down modes
- Sleep mode
- Standby mode
- Module standby function
MMU
• 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
• Single virtual mode and multiple virtual memory mode
• Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
• 4-entry fully-associative TLB for instructions
• 64-entry fully-associative TLB for instructions and operands
• Supports software-controlled replacement and random-counter replacementalgorithm
• TLB contents can be accessed directly by address mapping
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Cache memory
SH4-103 • Instruction cache (IC)- 8 kbytes, direct mapping- 256 entries, 32-byte block length- Normal mode (8-Kbyte cache)- Index mode
• Operand cache (OC)- 16 kbytes, direct mapping- 512 entries, 32-byte block length- Normal mode (16-kbyte cache)- Index mode- RAM mode (8-kbyte cache + 8-kbyte RAM)- Choice of write method (copy-back or write-through)
• Single-stage copy-back buffer, single-stage write-through buffer• Cache memory contents can be accessed directly by address
mapping (usable as on-chip memory)• Store queue (32 bytes x 2 entries)
SH4-202 • Instruction cache (IC):- 16 Kbyte, 2-way set associative- 512 entries, 32-bytes block length- Compatibility mode (8 Kbyte direct mapped)
- Index modea
• - Operand cache (OC)- 32 Kbyte, 2-way set associative- 1024 entries, 32 bytes block length- Compatibility mode (16 Kbyte direct mapped)- Index mode- RAM mode (16 Kbyte cache + 16 Kbyte RAM)
• Single-stage copy-back buffer, single-stage write-through buffer• Cache memory contents can be accessed directly by address
mapping (usable as on-chip memory)• Store queue (32 bytes x 2 entries)
a. Index mode (IC and OC) is only supported when in SH4-1xx compatibilitymode.
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STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
1.2 Block diagramFigure 1 shows an internal block diagram of the SH-4 32-Bit CPU Core .
Figure 1 SH-4 32-Bit CPU core
CCN: Cache and TLB controllerFPU: Floating point unitITLB: Instruction Translation
lookaside bufferUTLB: Unified Translation
lookaside buffer
CPU FPU
O CacheUTLBCCNITLBI cache
Add
ress
(in
stru
ctio
n)
Dat
a (in
stru
ctio
n)
Add
ress
(da
ta)
Dat
a (lo
ad)
Dat
a (s
tore
)
Dat
a (s
tore
)
Dat
a (s
tore
)Lower data
Lower data
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STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
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STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
2Programmingmodel
The SH-4 CPU core has two processor modes, user mode and privileged mode. TheSH-4 normally operates in user mode, and switches to privileged mode when anexception occurs, or an interrupt is accepted.
There are four kinds of registers:
• general registers
There are 16 general registers, R0 to R15. General registers R0 to R7 are bankedregisters which are switched by a processor mode change.
• system registers
Access to these registers does not depend on the processor mode.
• control registers
• floating-point registers
There are thirty-two floating-point registers, FR0–FR15 and XF0–XF15.FR0–FR15 and XF0–XF15 can be assigned to either of two banks(FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1).
The registers that can be accessed differ in the two processor modes.
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Register values after a reset are shown in Table 1.
2.1 General registersFigure 2 shows the relationship between the processor modes and the generalregisters. The SH-4 CPU core has twenty-four 32-bit general registers(R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16of these can be accessed as general registers, R0–R15, in either processor mode. Theassignment of R0–R7, in both modes, is shown below.
• R0_BANK0–R7_BANK0
In user mode (SR.MD = 0), R0–R7 are always assigned toR0_BANK0–R7_BANK0.
In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0only when SR.RB = 0.
Type Registers Initial valuea
General registers R0_BANK0–R7_BANK0,R0_BANK1–R7_BAN K1,R8–R15
Undefined
Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, I3–I0= 1111 (0xF), reserved bits = 0, others undefined
GBR, SSR, SPC, SGR,DBR
Undefined
VBR 0x00000000
System registers MACH, MACL, PR, FPUL Undefined
PC 0xA0000000
FPSCR 0x00040001
Floating-point reg-isters
FR0–FR15, XF0–XF15 Undefined
Table 1: Initial register values
a. Initialized by a power-on reset and manual reset
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• R0_BANK1–R7_BANK1
In user mode, R0_BANK1–R7_BANK1 cannot be accessed.
In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only whenSR.RB = 1.
Figure 2: General registers
SR.MD = 0 or (SR.MD = 1, SR.RB = 0)
R0_BANK0R1_BANK0R2_BANK0R3_BANK0R4_BANK0R5_BANK0R6_BANK0R7_BANK0
R0_BANK0R1_BANK0R2_BANK0R3_BANK0R4_BANK0R5_BANK0R6_BANK0R7_BANK0
R0_BANK1R1_BANK1R2_BANK1R3_BANK1R4_BANK1R5_BANK1R6_BANK1R7_BANK1
R0_BANK1R1_BANK1R2_BANK1R3_BANK1R4_BANK1R5_BANK1R6_BANK1R7_BANK1
R0R1R2R3R4R5R6R7
R0R1R2R3R4R5R6R7
R8R9R10R11R12R13R14R15
R8R9
R10R11R12R13R14R15
R8R9
R10R11R12R13R14R15
(SR.MD = 1, SR.RB = 1)
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Programming Note:
As the user’s R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an exceptionor interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary forthe interrupt handler to save and restore the user’s R0–R7(R0_BANK0–R7_BANK0).
After a reset, the values of R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, andR8–R15 are undefined.
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2.2 System registers
Name Size Initial value Synopsis
MACH 32 Undefined Multiply-and-accumulate register high
Operation MACH is used for the added value in a MAC instruction, and tostore a MAC instruction or MUL instruction operation result.
MACL 32 Undefined Multiply-and-accumulate register low
Operation MACL is used for the added value in a MAC instruction, and tostore a MAC instruction or MUL instruction operation result.
PR 32 Undefined Procedure register
Operation The return address is stored when a subroutine call using aBSR, BSRF or JSR instruction. PR is referenced by the subrou-tine return instruction (RTS).
PC 32 0xA000 0000 Program counter
Operation PC indicates the executing instruction address.
FPSCR 32 0x0004 0001 Floating-point status/control register
Operation Refer to Table 3: FPSCR register description
FPUL 32 undefined Floating-point communication register
Operation Data transfer between FPU registers and CPU registers is car-ried out via the FPUL register. The FPUL register is a systemregister, and is accessed from the CPU side by means of LDSand STS instructions. For example, to convert the integer storedin general register R1 to a single-precision floating-point num-ber, the processing flow is as follows:
R1 → (LDS instruction) → FPUL → (single-precision FLOATinstruction) → FR1
Table 2: System registers
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FPSCR
Field Bits Size Synopsis Type
RM [0,1] 2 Rounding mode. RW
Operation RM = 00: Round to Nearest.
RM = 01: Round to Zero.
RM = 10: Reserved.
RM = 11: Reserved.
For details see Section 6.3: Rounding
Power-on reset 1
Flag inexact 2 1 FPU inexact exception flag. RW
Operation Set to 1 if Inexact exception occurs.
Power-on reset 0
Flag underflow 3 1 FPU underflow exception flag. RW
Operation Set to 1 if Underflow exception occurs
Power-on reset 0
Flag overflow 4 1 FPU overflow exception flag. RW
Operation Set to 1 if overflow exception occurs
Power-on reset 0
Flag division byzero
5 1 FPU division by zero exception flag. RW
Operation Set to 1 if division by zero exception occurs
Power-on reset 0
Flag invalid opera-tion
6 1 FPU invalid operation exception flag. RW
Operation Set to 1 if Invalid operation exception occurs
Power-on reset 0
Table 3: FPSCR register description
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Enable inexact 7 1 FPU invalid exception enable field. RW
Operation Set to 1 to cause a trap when an inexact exception occurs.
Power-on reset 0
Enable underflow 8 1 FPU underflow exception enable field. RW
Operation Set to 1 to cause a trap when an underflow exceptionoccurs.
Power-on reset 0
Enable overflow 9 1 FPU overflow exception enable field. RW
Operation Set to 1 to cause a trap when an overflow exceptionoccurs.
Power-on reset 0
Enable divisionby zero
10 1 FPU division by zero exception enable field. RW
Operation Set to 1 to cause a trap when a division by zero exceptionoccurs.
Power-on reset 0
Enable invalid 11 1 FPU invalid exception enable field. RW
Operation Set to 1 to cause a trap when an Invalid exception occurs.
Power-on reset 0
Cause inexact 12 1 FPU inexact exception cause field. RW
Operation Set to 0 before an FPU instruction is executed. Set to 1 ifan Inexact exception occurs.
Power-on reset 0
FPSCR
Field Bits Size Synopsis Type
Table 3: FPSCR register description
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Cause underflow 13 1 FPU underflow exception cause field. RW
Operation Set to 0 before an FPU instruction is executed. Set to 1 ifan underflow exception occurs.
Power-on reset 0
Cause overflow 14 1 FPU overflow exception cause field. RW
Operation Set to 0 before an FPU instruction is executed. Set to 1 ifan overflow exception occurs.
Power-on reset 0
Cause division byzero
15 1 FPU division by zero exception cause field. RW
Operation Set to 0 before an FPU instruction is executed. Set to 1 if adivision by zero exception occurs.
Power-on reset 0
Cause invalid 16 1 FPU invalid exception cause field. RW
Operation Set to 0 before an FPU instruction is executed. Set to 1 ifan invalid exception occurs.
Power-on reset 0
Cause FPU error 17 1 FPU error exception cause field. RW
Operation Set to 0 before an FPU instruction is executed. Set to 1 ifan FPU error exception occurs.
Power-on reset 0
DN 18 1 Denormalization mode. RW
Operation DN = 0: A denormalizing number is treated as such.
DN = 1: A denormalized number is treated as zero.
Power-on reset 0
FPSCR
Field Bits Size Synopsis Type
Table 3: FPSCR register description
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STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
PR 19 1 Precision mode. RW
Operation PR = 0: Floating point instructions are executed as singleprecision operations.
PR = 1: Floating point instructions are executed as dou-ble-precision operations (the result of instructions forwhich double-precision is not supported is undefined).
Mode setting [SZ = 1, PR = 1] is reserved. FPU operationresults are undefined in this mode.
Power-on reset 1
SZ 20 1 Transfer size mode. RW
Operation SZ = 0: The data size of the FMOV instruction is 32 bits.
SZ = 1: The data size of the FMOV instruction is a 32-bitregister pair (64 bits).
Programming note:
When SZ = 1 and big endian mode is selected, FMOV canbe used for double-precision floating-point data load orstore operations. In little endian mode, two 32-bit data sizemoves must be executed, with SZ = 0, to load or store adouble-precision floating-point number.
Power-on reset 0
FR 21 1 Floating-point register bank. RW
Operation FR = 0: FPR0_BANK0-FPR15_BANK0 are assigned toFR0-FR15; FPR0_BANK1-FPR15_BANK1 are assignedto XF0-XF15.
FR = 1: FPR0_BANK0-FPR15_BANK1 are assigned toFR0-FR15.
Power-on reset 0
FPSCR
Field Bits Size Synopsis Type
Table 3: FPSCR register description
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RES [22,31] 10 Bits reserved RW
Power-on reset Undefined
FPSCR
Field Bits Size Synopsis Type
Table 3: FPSCR register description
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2.3 Control registers
Name Size Initial valuePrivilegeprotection
Synopsis
SR 32 See Table 5 forindividual bits.
Yes Status register
Operation Refer to Table 5: SR register description
SSR 32 Undefined Yes Saved status register
Operation The current contents of SR are saved to SSR in the event of anexception or interrupt.
SPC 32 Undefined Yes Saved program counter
Operation The address of an instruction at which an interrupt or exceptionoccurs is saved to SPC.
GBR 32 Undefined No Global base register
Operation GBR is referenced as the base address in a GBR-referencingMOV instruction.
VBR 32 0x0000 0000 Yes Vector base register
Operation VBR is referenced as the branch destination base address in theevent of an exception or interrupt.
For details, see Chapter 5: Exceptions.
SGR 32 Undefined Yes Saved general register
Operation The contents of R15 are saved to SGR in the event of an excep-tion or interrupt.
DBR 32 undefined Yes Debug base register
Operation When the user break debug function is enabled (BRCR.UBDE =1), DBR is referenced as the user break handler branch destina-tion address instead of VBR.
Table 4: Control registers
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SR
Field Bits Size Synopsis Type
T 0 1 True/False condition or carry/borrow bit. RW
Operation Refer to individual instruction descriptions, which affect the Tbit.
Power-on reset Undefined
S 1 1 Specifies a saturation operation for a MAC instruction. RW
Operation Refer to individual instruction descriptions, which affect the Sbit.
Power-on reset Undefined
IMASK [4,7] 4 Interrupt mask level. RW
Operation External interrupts of a lower level than IMASK are masked.
Power-on reset 1
Q 8 1 State for divide step. RW
Operation Used by the DIV0S, DIV0U and DIV1 instructions.
Power-on reset Undefined
M 9 1 State for divide step. RW
Operation Used by the DIV0S, DIV0U and DIV1 instructions.
Power-on reset Undefined
FD 15 1 FPU disable bit (cleared to 0 by a reset). RW
Operation FD = 1: An FPU instruction causes a general FPU disableexception, and if the FPU instruction is in a delay slot, a slotFPU disable exception is generated.
For further details see FPUDIS description in section Section6.4: Floating-point exceptions
Power-on reset 0
Table 5: SR register description
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BL 28 1 Exception/interrupt block bit (set to 1 by a reset,exception, or interrupt).
RW
Operation BL = 1: Interrupt requests are masked. If a general exception,other than a user break occurs while BL = 1, the processorswitches to the reset state.
Power-on reset 1
RB 29 1 General register bank specifier in privileged mode (setto 1 by a reset, exception or interrupt).
RW
Operation RB = 0: R0_BANK0-R7_BANK0 are accessed as general regis-ters R0-R7. (R0_BANK1-R7_BANK1 can be accessed usingLDC/STC R0_BANK-R7_BANK instructions.)
RB = 1: R0_BANK1-R7_BANK1 are accessed as general regis-ters R0-R7. (R0_BANK0-R7_BANK0 can be accessed usingLDC/STC R0_BANK-R7_BANK instructions.)
Power-on reset 1
MD 30 1 Processor mode. RW
Operation MD = 0: User mode (Some instructions cannot be executed,and some resources cannot be accessed).
MD = 1: Privileged mode.
Power-on reset 1
RES [2,3],[10,14][16,27]31
20 Bits reserved RW
Power-on reset Undefined
SR
Field Bits Size Synopsis Type
Table 5: SR register description
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2.4 Floating-point registersFigure 3 shows the floating-point registers. There are thirty-two 32-bitfloating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 andFPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15,DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. Thecorrespondence between FPRn_BANKi and the reference name is determined by theFR bit in FPSCR.
• Floating-point registers, FPRn_BANKi (32 registers)
• Single-precision floating-point registers, FRi (16 registers)
FPSCR.FR = 0 : FR0–FR15 are assigned to FPR0_BANK0–FPR15_BANK0.FPSCR.FR = 1 : FR0–FR15 are assigned to FPR0_BANK1–FPR15_BANK1.
• Double-precision floating-point registers or single-precision floating-pointregister pairs, DRi (8 registers): A DR register comprises two FR registers.
DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7},
DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13},
DR14 = {FR14, FR15}
• Single-precision floating-point vector registers, FVi (4 registers): An FV registercomprises four FR registers
FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7},
FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}
• Single-precision floating-point extended registers, XFi (16 registers)
FPSCR.FR = 0 : XF0-XF15 are assigned to FPR0_BANK1-FPR15_BANK1.
FPSCR.FR = 1 : XF0-XF15 are assigned to FPR0_BANK0-FPR15_BANK0.
• Single-precision floating-point extended register pairs, XDi (8 registers): An XDregister comprises two XF registers
XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7},
XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13},
XD14 = {XF14, XF15}
• Single-precision floating-point extended register matrix, XMTRX: XMTRXcomprises all 16 XF registers
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XMTRX = XF0 XF4 XF8 XF12
XF1 XF5 XF9 XF13
XF2 XF6 XF10 XF14
XF3 XF7 XF11 XF15
Figure 3: Floating-point registers
FPR0_BANK0FPR1_BANK0FPR2_BANK0FPR3_BANK0FPR4_BANK0FPR5_BANK0FPR6_BANK0FPR7_BANK0FPR8_BANK0FPR9_BANK0
FPR10_BANK0FPR11_BANK0FPR12_BANK0FPR13_BANK0FPR14_BANK0FPR15_BANK0
XF0XF1XF2 XF3XF4XF5XF6XF7 XF8 XF9 XF10 XF11XF12XF13XF14XF15
FR0FR1FR2 FR3FR4FR5FR6FR7 FR8 FR9 FR10 FR11FR12FR13FR14FR15
DR0
DR2
DR4
DR6
DR8
DR10
DR12
DR14
FV0
FV4
FV8
FV12
XD0 XMTRX
XD2
XD4
XD6
XD8
XD10
XD12
XD14
FPR0_BANK1FPR1_BANK1FPR2_BANK1FPR3_BANK1FPR4_BANK1FPR5_BANK1FPR6_BANK1FPR7_BANK1FPR8_BANK1FPR9_BANK1
FPR10_BANK1FPR11_BANK1FPR12_BANK1FPR13_BANK1FPR14_BANK1FPR15_BANK1
XF0XF1XF2 XF3XF4XF5XF6XF7 XF8 XF9 XF10 XF11XF12XF13XF14XF15
FR0FR1FR2 FR3FR4FR5FR6FR7 FR8 FR9 FR10 FR11FR12FR13FR14FR15
DR0
DR2
DR4
DR6
DR8
DR10
DR12
DR14
FV0
FV4
FV8
FV12
XD0XMTRX
XD2
XD4
XD6
XD8
XD10
XD12
XD14
FPSCR.FR = 0 FPSCR.FR = 1
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Programming Note:
After a reset, the values of FPR0_BANK0–FPR15_BANK0 andFPR0_BANK1–FPR15_BANK1 are undefined.
2.5 Memory-mapped registersAppendix A summarizes how the control registers are mapped in to the addressspace. The control registers are double-mapped to the following two memory areas.All registers have two addresses.
0x1F00 0000-0x1FFF FFFF
0xFF00 0000-0xFFFF FFFF
These two areas are used as follows.
• 0x1F00 0000–0x1FFF FFFF
This area must be accessed in address translation mode using the TLB. Sinceexternal memory area is defined as a 29-bit address space in the SH-4 CPU corearchitecture, the TLB’s physical page numbers do not cover a 32-bit address space.In address translation, the page numbers of this area can be set in thecorresponding field of the TLB by accessing a memory-mapped register. The pagenumbers of this area should be used as the actual page numbers set in the TLB.When address translation is not performed, the operation of accesses to this area isundefined.
• 0xFF00 0000–0xFFFF FFFF
Access to area 0xFF00 0000-0xFFFF FFFF in user mode will cause an address error.Memory-mapped registers can be referenced in user mode by means of access thatinvolves address translation.
Note: Do not access undefined locations in either area. The operation of an access to anundefined location is undefined. Memory-mapped registers must be accessed using aload/store instruction of an equal size to that of the register. The operation of anaccess using an invalid data size is undefined.
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2.6 Data format in registersRegister operands are always longwords (32 bits). When a memory operand is only abyte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded intoa register.
2.7 Data formats in memoryMemory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. Amemory operand less than 32 bits in length is sign-extended before being loadedinto a register.
A word operand must be accessed starting from a word boundary (even address of a2-byte unit: address 2n), and a longword operand starting from a longwordboundary (even address of a 4-byte unit: address 4n). An address error will result ifthis rule is not observed. A byte operand can be accessed from any address.
Big endian or little endian byte order can be selected for the data format. Thisendian selection cannot be changed dynamically and is selected by the systemduring power-on reset. Refer to the system architecture manual of the relevantproduct for details of how to perform endian selection. Bit positions are numberedleft to right from most-significant to least-significant. Thus, in a 32-bit longword,the left-most bit, bit 31, is the most significant bit and the right-most bit, bit 0, is theleast significant bit.
The data format in memory is shown in Figure 4.
Note: The SH-4 CPU core does not support endian conversion for the 64-bit data format.Therefore, if double-precision floating-point format (64-bit) access is performed inlittle endian mode, the upper and lower 32 bits will be reversed.
Figure 4: Data formats in memory
Address A
A
7 0 7 0 7 0 7 0
31
15 0 15 0
31 0
15 0
31 0
23 15 7 0
A + 1 A + 2 A + 3
Byte 0
Word 0
Longword
Word 1
Byte 1 Byte 2 Byte 3
A + 11
7 0 7 0 7 0 7 0
31
15 0
23 15 7 0
A + 10 A + 9 A + 8
Byte 3
Word 1
Longword
Word 0
Byte 2 Byte 1 Byte 0
Address A + 4
Address A + 8
Address A + 8
Address A + 4
Address A
Big endian Little endian
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2.8 Processor statesThe SH-4 CPU core has four processor states. Transitions between the states areshown in Figure 5
2.8.1 Reset state
In this state the CPU is reset. The CPU can be placed in one of two reset states,either power on reset or manual reset. Which of these is selected is determined bythe system architecture. Refer to the relevant system architecture manual fordetails. For more information on resets, see section 5, Exceptions.
The purpose of having two reset modes is to allow some flexibility over which systemcomponents are reset. Typically:
• power-on reset will cause all system components to be reset,
• manual reset may, for example, avoid resetting DRAM controllers so thatmemory contents are preserved.
2.8.2 Exception-handling state
This is a transient state during which the CPU’s processor state flow is altered by areset, general exception, or interrupt exception source.
In the case of a reset, the CPU branches to address 0xA000 0000 and startsexecuting the user-coded exception handling program.
In the case of a general exception or interrupt, the program counter (PC) contentsare saved in the saved program counter (SPC), the status register (SR) contents aresaved in the saved status register (SSR), and the R15 contents are saved in savedgeneral register (SGR). The CPU branches to the start address of the user-codedexception service routine, found from the sum of the contents of the vector baseaddress and the vector offset.
See Chapter 5: Exceptions, for more information on resets, general exceptions, andinterrupts.
2.8.3 Program execution state
In this state the CPU executes program instructions in sequence.
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2.8.4 Power-down state
The power-down state is entered by executing a SLEEP instruction. In this state theCPU stops executing instructions and signals to the system that the CPU has beenput to sleep. The system response to receiving this signal is described in the SystemArchitecture Manual of the appropriate product.
The CPU is restarted by raising an interrupt.
Note: For conditions determining state transitions, see the System Architecture Manual.
Figure 5: Processor state transitions
Power-on reset state Manual reset state
Exception-handling state
Program execution state
Sleep mode Standby mode
Power-on reset state Manual reset state
Reset state
Power-down state
InterruptInterrupt
End of exceptiontransitionprocessing
Exceptioninterrupt
SLEEP instruction with STBY bit set
SLEEP instructionwith STBY bitcleared
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2.9 Processor modesThere are two processor modes: user mode and privileged mode. The processor modeis determined by the processor mode bit (MD) in the status register (SR). User modeis selected when the MD bit is cleared to 0, and privileged mode when the MD bit isset to 1. When the reset state or exception-handling state is entered, the MD bit isset to 1. When exception handling ends, the MD bit returns to the value held beforethe exception occurred.
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3Memorymanagementunit (MMU)3.1 Overview
The SH-4 CPU core manages a 29-bit external memory space by providing 8-bitaddress space identifiers, and a 32-bit logical (virtual) address space. Addresstranslation from virtual address to physical address is performed using the memorymanagement unit (MMU), built into the SH-4 CPU core. The MMU performshigh-speed address translation by caching user-created address translation tableinformation, in an address translation buffer (translation lookaside buffer: TLB).The SH-4 has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB)entries. UTLB copies are stored in the ITLB by hardware. It is possible to set thevirtual address space access right, and implement storage protection independently,for privileged mode and user mode.
3.2 Role of the MMUThe main purpose of an MMU is to ensure that efficient use is made of physicalmemory, which in most systems is a limiting resource. The MMU is normallymanaged by the OS, which allocates physical pages of memory to virtual pages ofmemory, as required by a task. Pages which are switched out by the OS are placed ina secondary storage device, such as a hard disk.
A page refers to a contiguous range of addresses, which can all be translated by asingle translation table entry. On SH-4 there is support for 4 page sizes: 1-kbyte,4-kbyte, 64-kbyte and 1-Mbyte.
Memory protection functions are provided to prevent physical memory frominadvertently being accessed and reset by a process.
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Although the functions of the MMU could be implemented by software alone, havingaddress translation performed by software each time a process accessed physicalmemory would be very inefficient. For this reason, a buffer for address translation(TLB) is provided in hardware, and frequently used address translation informationis placed here. The TLB can be described as a cache for address translationinformation. However, unlike a cache, if address translation fails—that is, if anexception occurs—switching of the address translation information is normallyperformed by software. Thus memory management can be performed in a flexiblemanner by software.
3.3 Register descriptions There are six MMU-related registers.
Note: Behavior is undefined if an area designated as a reserved area in this manual isaccessed.
Name Abbreviation R/WInitial
valuea P4 addressbArea 7
addressBAccess
size
Page table entry highregister
PTEH R/W Undefined 0xFF00 0000 0x1F00 0000 32
Page table entry lowregister
PTEL R/W Undefined 0xFF00 0004 0x1F00 0004 32
Translation table baseregister
TTB R/W Undefined 0xFF00 0008 0x1F00 0008 32
Translation table addressregister
TEA R/W Undefined 0xFF00 000C 0x1F00 000C 32
MMU control register MMUCR R/W 0x00000000
0xFF00 0010 0x1F00 0010 32
Table 6: MMU registers
a. The initial value is the value after a power-on reset or manual reset.
b. This is the address when using the virtual/physical address space P4 region. When making anaccess from physical address space Area 7 using the TLB, the upper 3 bits of the address areignored.
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3.3.1 Page table entry high register (PTEH)
Longword access to PTEH can be performed from 0xFF00 0000 in the P4 region,and 0x1F00 0000 in Area 7. When an MMU exception or address error exceptionoccurs, the VPN of the virtual address at which the exception occurred, is set in theVPN field by hardware. VPN varies according to the page size, but the VPN set byhardware when an exception occurs, always consists of the upper 22 bits of thevirtual address which caused the exception. VPN setting can also be carried out bysoftware. The number of the currently executing process is set in the ASID field bysoftware. ASID is not updated by hardware. VPN and ASID are recorded in theUTLB by means of the LDLTB instruction.
PTEH
Field Bits Size Synopsis Type
ASID [0,7] 8 Address space identifier. RW
Operation Indicates the process that can access a virtual page. In singlevirtual memory mode and user mode, or in multiple virtualmemory mode, if the SH bit is 0, this identifier is compared withthe ASID in PTEH when address comparison is performed.
See section 3.3.7 Address space identifier.
Power-on reset Undefined
VPN [10,31] 22 Virtual page number. RW
Operation For 1-kbyte: upper 22 bits of virtual address.
For 4-kbyte: upper 20 bits of virtual address.
For 64-kbyte: upper 16 bits of virtual address.
For 1-Mbyte: upper 12 bits of virtual address.
Power-on reset Undefined
Table 7: PTEH register description
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3.3.2 Page table entry low register (PTEL)
Longword access to PTEL can be performed from 0xFF00 0004 in the P4 region, and0x1F00 0004 in Area 7. PTEL is used to hold the physical page number and pagemanagement information to be recorded in the UTLB, by means of the LDTLBinstruction. The contents of this register are not changed unless a software directiveis issued.
PTEL
Field Bits Size Synopsis Type
WT 0 1 Write-through bit. RW
Operation Specifies the cache write mode.
0: Copy-back mode.
1: Write-through mode.
Power-on reset Undefined
SH 1 1 Share status bit. RW
Operation 0: pages are not shared by processes.
1: pages are shared by processes.
Power-on reset Undefined
D 2 1 Dirty bit RW
Operation Indicates whether a write has been performed to a page.
0: Write has not been performed.
1: Write has been performed.
Power-on reset Undefined
C 3 1 Cacheability bit. RW
Operation Indicates whether a page is cacheable.
0: Not cacheable.
1: Cacheable.
When control register is mapped, this bit must be cleared to 0.
Power-on reset Undefined
Table 8: PTEL register description
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SZ0 4 1 Page size bit. RW
Operation Specify page size.
Power-on reset Undefined
PR [5,6] 2 Protection key data. RW
Operation 2-bit data expressing the page access right as a code.
00: Can be read only in privileged mode.
01: Can be read and written in privileged mode.
10: Can be read only, in privileged or user mode.
11: Can be read and written in privileged or user mode.
Power-on reset Undefined
SZ1 7 1 Page size bit RW
Operation Refer to SZ0 for operation details.
Power-on reset 0
PTEL
Field Bits Size Synopsis Type
Table 8: PTEL register description
Bit SZ1 Bit SZ0 Page Size
0 0 1-kbyte
0 1 4-kbyte
1 0 64-kbyte
1 1 1-Mbyte
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V 8 1 Validity bit. RW
Operation Indicates whether the entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset.
Not affected by a manual reset.
Power-on reset Undefined
PPN [10,28] 19 Physical page number RW
Operation Upper 19 bits of the physical address.
With a 1-kbyte page, PPN bits [28:10] are valid.
With a 4-kbyte page, PPN bits [28:12] are valid.
With a 64-kbyte page, PPN bits [28:16] are valid.
With a 1-Mbyte page, PPN bits [28:20] are valid.
The synonym problem must be taken into account when settingthe PPN (Section 3.6.5: Avoiding synonym problems onpage 64).
Power-on reset Undefined
RES 9,[29,31]
4 Bits reserved RW
Power-on reset Undefined
PTEL
Field Bits Size Synopsis Type
Table 8: PTEL register description
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3.3.3 Translation table base register (TTB)
Long word access to the TTB can be performed from 0xFF00 0008 in the P4 region,and 0x1F00 0008 in Area 7. The contents of the TTB are not changed unless asoftware directive is issued. This register can be freely used by software.
3.3.4 TLB exception address register (TEA)
Longword access to TEA can be performed from 0xFF00 000C in the P4 region and0x1F00 000C in Area 7. The contents of this register can be changed by software.
3.3.5 MMU control register (MMUCR)
Longword access to MMUCR can be performed from 0xFF00 0010 in the P4 region,and 0x1F00 0010 in Area 7. The individual bits perform MMU settings as shownbelow. Therefore, MMUCR rewriting should be performed by a program in the P1 orP2 region. After MMUCR is updated, an instruction that performs data access to the
TTB
Field Bits Size Synopsis Type
TTB [0,31] 32 Translation table base register. RW
Operation TTB is used, for example, to hold the base address of thecurrently used page table.
Power-on reset Undefined
Table 9: TTB register description
TEA
Field Bits Size Synopsis Type
TEA [0,31] 32 TLB exception address register. RW
Operation After an MMU exception or address error exception occurs, thevirtual address at which the exception occurred is set in TEA byhardware.
Power-on reset Undefined
Table 10: TEA register description
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P0, P3, U0, or store queue region should be located at least four instructions afterthe MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0region should be located at least eight instructions after the MMUCR updateinstruction. MMUCR contents can be changed by software. The LRUI bits and URCbits may also be updated by hardware.
MMUCR
Field Bits Size Synopsis Type
AT 0 1 Address translation bit. RW
Operation Specifies MMU enabling or disabling.
0: MMU disabled.
1: MMU enabled.
MMU exceptions are not generated when the AT bit is 0.Therefore, in the case of software that does not use the MMU,the AT bit should be cleared to 0.
Power-on reset 0
TI 2 1 TLB invalidate. RW
Operation Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLBbits. This bit always returns 0 when read.
Power-on reset 0
SV 8 1 Single virtual mode bit. RW
Operation Bit that switches between single virtual memory mode andmultiple virtual memory mode.
0: Multiple virtual memory mode.
1: Single virtual memory mode.
When this bit is changed, ensure that 1 is also written to the TIbit.
Power-on reset 0
Table 11: MMUCR register description
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SQMD 9 1 Store queue mode bit. RW
Operation Specifies the right of access to the store queues.
0: User/privileged access possible.
1: Privileged access possible (address error exception in case ofuser access).
Power-on reset 0
URC [10,15] 6 UTLB replace counter. RW
Operation Random counter for indicating the UTLB entry for whichreplacement is to be performed with an LDTLB instruction. URCis incremented each time the UTLB is accessed. When URB > 0,URC is reset to 0 when the condition URC = URB occurs. Alsonote that, if a value is written to URC by software which results inthe condition URC > URB, incrementing is first performed inexcess of URB until URC = 0x3F. URC is not incremented by anLDTLB instruction.
Power-on reset 0
URB [18,23] 6 UTLB replace boundary. RW
Operation Bits that indicate the UTLB entry boundary at which replacementis to be performed. Valid only when URB > 0.
Power-on reset 0
MMUCR
Field Bits Size Synopsis Type
Table 11: MMUCR register description
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LRUI [26, 31] 6 Least recently used ITLB. RW
Operation The LRU (least recently used) method is used to decide the ITLBentry to be replaced in the event of an ITLB miss. The entry to bepurged from the ITLB can be confirmed using the LRUI bits. LRUIis updated by means of the algorithm shown below. A dash in thistable means that updating is not performed .
When the LRUI bit settings are as shown below, thecorresponding ITLB entry is updated by an ITLB miss. Anasterisk in this table means “don’t care”..
Ensure that values for which “Setting prohibited” is indicated inthe above table are not set at the discretion of software. After apower-on manual reset the bits are initialized to 0,and therefore aprohibited setting is never made by a hardware update.
Power-on reset 0
MMUCR
Field Bits Size Synopsis Type
Table 11: MMUCR register description
[5] [4] [3] [2] [1] [0]
When ITLB entry 0 is used 0 0 0 - - -
When ITLB entry 1 is used 1 - - 0 0 -
When ITLB entry 2 is used - 1 - 1 - 0
When ITLB entry 3 is used - - 1 - 1 1
Other than the above - - - - - -
[5] [4] [3] [2] [1] [0]
ITLB entry 0 is updated 1 1 1 * * *
ITLB entry 1 is updated 0 * * 1 1 *
ITLB entry 2 is updated * 0 * 0 * 1
ITLB entry 3 is updated * * 0 * 0 0
Other than the above Setting prohibited
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3.4 Address space
3.4.1 Physical address space
The SH-4 CPU core supports a 32-bit (4-Gbyte) physical address space. When theMMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space accessedby the program is this physical address space. The physical address space is dividedinto a number of regions, as shown in Figure 7. The region is selected using the top3 bits of the physical address.
RES 1, [3,7],[16,17],[24,25]
10 Bits reserved RW
Power-on reset Undefined
MMUCR
Field Bits Size Synopsis Type
Table 11: MMUCR register description
Bit Region accessed
31 30 29 Privileged mode User mode
0 0 0 P0 U0
0 0 1
0 1 0
0 1 1
1 0 0 P1 Address error
1 0 1 P2 Address error
1 1 0 P3 Address error
1 1 1 P4 Address errora
a. Except for address from 0xe000 0000 - 0xe3FF FFFF which the user can useto access the store queues.
Table 12: Region selection
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The region selected determines how the remaining 29 bits are interpreted. Forexample P0, P1 and P3 all access the 29 bits of external memory via the cache. P4 isused exclusively to access the cores internal devices. See the system architecturemanual for more details of the internal devices available on a particular product.
3.4.2 External memory space
The SH-4 CPU core supports a 29-bit external memory space.The external memoryspace is divided into eight Areas as shown in Figure 7. Areas 0 to 6 relate tomemory, Area 7 is a reserved area, and is only accessed via the P4 region.
Figure 6: External memory Space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7 (reserved area)
0x0800 0000
0x0000 0000
0x0400 0000
0x0C00 0000
0x1000 0000
0x1400 0000
0x1800 0000
0x1C00 0000
0x1FFF FFFF
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P0, P1, P3, U0 Regions: The P0, P1, P3, and U0 regions can be accessed using thecache. Whether or not the cache is used is determined by the cache control register(CCR). When the cache is used, with the exception of the P1 region, switchingbetween the copy-back method and the write-through method for write accesses isspecified by the CCR.WT bit. For the P1 region, switching is specified by theCCR.CB bit. Zeroing the upper 3 bits of an address in these regions gives thecorresponding external memory space address. However, since Area 7 in theexternal memory space is a reserved Area, a reserved area also appears in theseregions.
P2 Region: The P2 region cannot be accessed using the cache. In the P2 region,zeroing the upper 3 bits of an address gives the corresponding external memoryspace address. However, since Area 7 in the external memory space is a reservedArea, a reserved area also appears in this region.
P4 Region: The P4 region is mapped onto SH-4 CPU core on-chip I/O channels.This region cannot be accessed using the cache. The P4 region is shown in detail inTable 13.
Figure 7: Physical address space (MMUCR.AT = 0)
0xFFFF FFFF
0xC000 0000
0xE000 0000
0xA000 0000
0x8000 0000
P4 regionNon-cacheable
P3 regionCacheable
P2 regionNon-cacheable
P1 region Cacheable
0xFFFF FFFF Address error
Address error
0xE000 00000xE400 0000
0x8000 0000
U0 regionCacheable
0x0000 00000x0000 0000
P0 regionCacheable
Privileged mode User mode
Area 0Area 1Area 2Area 3Area 4Area 5Area 6Area 7 *
External memory space
Store queue region
* Area 7 is reserved
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Start address End address Function
0xE000 0000 0xE3FF FFFF Comprises addresses for accessing the store queues (SQs). Whenthe MMU is disabled (MMUCR.AT=0), the SQ access right isspecified by the MMUCR.SQMD bit.
For details, see Section 4.6: Store queues on page 101.
0xF000 0000 0xF0FF FFFF Used for direct access to the instruction cache address array.
For details, see Section 4.5.1: IC address array on page 95.
0xF100 0000 0xF1FF FFFF Used for direct access to the instruction cache data array.
For details, see Section 4.5.4: IC data array on page 97.
0xF200 0000 0xF2FF FFFF Used for direct access to the instruction TLB address array.
For details, see Section 3.8.1: ITLB address array on page 70
0xF300 0000 0xF3FF FFFF Used for direct access to instruction TLB data arrays 1 and 2.
For details, see Section 3.8.2: ITLB data array 1 on page 71.
0xF400 0000 0xF4FF FFFF Used for direct access to the operand cache address array.
For details, see Section 4.5.5: OC address array on page 98.
0xF500 0000 0xF5FF FFFF Used for direct access to the operand cache data array.
For details, see Section 4.5.6: OC data array on page 99.
0xF600 0000 0xF6FF FFFF Used for direct access to the unified TLB address array.
For details, see Section 3.8.3: UTLB address array on page 72.
0xF700 0000 0xF7FF FFFF Used for direct access to unified TLB data arrays 1 and 2.
For details, see Section 3.8.4: UTLB data array 1 on page 74.
0xFC00 0000 0xFFFF FFFF Control register area.
Table 13: P4 area
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3.4.3 Virtual address space
Setting the MMUCR.AT bit to 1, enables the P0, P3, and U0 regions of the addressspace in the SH-4 CPU core to be mapped onto any external memory space in 1-, 4-,or 64-kbyte, or 1-Mbyte, page units. Mapping from virtual address space to 29-bitexternal memory space is carried out using the TLB. When accessed using virtualaddressing, Area 7 is equivalent to the P4 region in physical address space. Virtualaddress space is illustrated in Figure 8.
Figure 8: Virtual memory space (MMUCR.AT = 1)
Area 0Area 1Area 2Area 3Area 4Area 5Area 6Area 7
P0 regionCacheableAddress TranslationPossible
P1 regionCacheableAddress Translation
Not PossibleP2 regionNon-cacheableAddress Translation
Not PossibleP3 regionCacheableAddress Translation
PossibleP4 regionNon-cacheableAddress Translation
Not Possible
U0 regionCacheableAddress Translation
Possible
Address error
Store queue region
Address error
External memory space
Privileged mode User mode
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P0, P3, U0 Regions: The P0 region (excluding addresses 0x7C00 0000 to 0x7FFFFFFF), P3 region, and U0 region, allow access using the cache, and addresstranslation using the TLB. These regions can be mapped onto any external memoryspace in 1, 4, or 64-kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabledstate, and the TLB enable bit (C bit) is 1, accesses can be performed using the cache.In write accesses to the cache, switching between the copy-back method and thewrite-through method is indicated by the TLB write-through bit (WT bit), and isspecified in page units.
Only when the P0, P3, and U0 regions are mapped onto external memory space bymeans of the TLB, are addresses 0x1C00 0000 to 0x1FFF FFFF of Area 7 in externalmemory space allocated to the control register area. This enables control registers tobe accessed from the U0 region in user mode. In this case, the C bit for thecorresponding page must be cleared to 0.
P1, P2, P4 Regions: Address translation using the TLB cannot be performed forthe P1, P2, or P4 region (except for the store queue region). Accesses to these regionsare the same as for physical address space. The store queue region can be mappedonto any external memory space by the MMU. However, operation in the case of anexception differs from that for normal P0, U0, and P3 spaces. For details, see section4.6, Store Queues.
3.4.4 On-chip RAM space
In the SH-4 CPU core, half of the (16 kbyte) operand cache can be used as on-chipRAM. This can be done by changing the CCR settings.
When the operand cache is used as on-chip RAM (CCR.ORA = 1), the P0/ U0 regionaddresses 0x7C00 0000 to 0x7FFF FFFF are an on-chip RAM area. Data accesses(byte/word/longword/quadword) can be used in this area. This area can only be usedin RAM mode.
Note: It is not possible to execute instructions out of this on-chip RAM.
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3.4.5 Address translation
In the SH-4 CPU core, the ITLB is used for instruction accesses and the UTLB fordata accesses. In the event of an access to an region other than the P4 region, theaccessed virtual address is translated to a physical address. If the virtual addressbelongs to the P1 or P2 region, the physical address is uniquely determined withoutaccessing the TLB. If the virtual address belongs to the P0, U0, or P3 region, theTLB is searched using the virtual address, and if the virtual address is recorded inthe TLB, a TLB hit is made and the corresponding physical address is read from theTLB. If the accessed virtual address is not recorded in the TLB, a TLB missexception is generated and processing switches to the TLB miss exception handlingroutine. In the TLB miss exception handling routine, the address translation tablein external memory is searched, and the corresponding physical address and pagemanagement information are recorded in the TLB. After the return from theexception handling routine, the instruction which caused the TLB miss exception isre-executed.
3.4.6 Single virtual memory mode and multiple virtual memorymode
There are two virtual memory systems, either of which can be selected with theMMUCR.SV bit:
• single virtual memoryA number of processes run simultaneously, using non-overlapping virtualaddress spaces, so that the physical address corresponding to a particular virtualaddress is uniquely determined.
• multiple virtual memoryA number of processes run with overlapping virtual address spaces,consequently, virtual addresses may need to be translated into different physicaladdresses depending on the process i.d.
The only difference between the single virtual memory and multiple virtual memorysystems in terms of operation is in the TLB address comparison method (see Section3.5.3: Address translation method on page 59).
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3.4.7 Address space identifier (ASID)
In multiple virtual memory mode, the 8-bit address space identifier (ASID) is usedto distinguish between processes running simultaneously, while sharing the virtualaddress space. Software can set the ASID of the currently executing process inPTEH in the MMU. The TLB does not have to be purged when processes areswitched by means of ASID.
In single virtual memory mode, ASID is used to provide memory protection forprocesses running simultaneously while using the virtual memory space on anexclusive basis.
3.5 TLB functions
3.5.1 Unified TLB (UTLB) configuration
The unified TLB (UTLB) is so called because of its use for the following twopurposes:
1 To translate a virtual address to a physical address in a data access
2 As a table of address translation information, to be recorded in the instructionTLB in the event of an ITLB miss
Information in the address translation table located in external memory is cachedinto the UTLB. The address translation table contains virtual page numbers andaddress space identifiers, and corresponding physical page numbers and pagemanagement information. Figure 9 shows the overall configuration of the UTLB.The UTLB consists of 64 fully-associative type entries.
Figure 9: UTLB configuration
Entry 0Entry 1Entry 2
Entry 63
ASID [7:0]ASID [7:0]ASID [7:0]
VPN [31:10]VPN [31:10]VPN [31:10]
VVV
PPN [28:10]PPN [28:10]PPN [28:10]
SZ [1:0]SZ [1:0]SZ [1:0]
SHSHSH
CCC
PR [1:0]PR [1:0]PR [1:0]
DDD
WTWTWT
PPN [28:10] SZ [1:0] SH C PR [1:0] D WTASID [7:0] VPN [31:10] V
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3.5.2 Instruction TLB (ITLB) configuration
The ITLB is used to translate a virtual address to a physical address in aninstruction access. Information in the address translation table located in theUTLB, is cached into the ITLB. Figure 10 shows the overall configuration of theITLB. The ITLB consists of 4 fully-associative type entries. The address translationinformation is almost the same as that in the UTLB, but with the followingdifferences:
1 D and WT bits are not supported.
2 There is only one PR bit, corresponding to the upper of the PR bits in the UTLB.
3.5.3 Address translation method
Figure 11 and Figure 12 show flowcharts of memory accesses using the UTLB andITLB
Figure 10: ITLB configuration
Entry 0Entry 1Entry 2
ASID [7:0]ASID [7:0]ASID [7:0]
VPN [31:10]VPN [31:10]VPN [31:10]
VVV
PPN [28:10]PPN [28:10]PPN [28:10]
SZ [1:0]SZ [1:0]SZ [1:0]
SHSHSH
CCC
PRPRPR
Entry 3 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR
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.
Figure 11: Flowchart of memory access using UTLB figure
MMUCR.AT = 1
SH = 0 and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs matchand ASIDs match and
V = 1
Only oneentry matches
SR.MD?
CCR.OCE?
CCR.CB? CCR.WT?
VPNs matchand V = 1
Cache accessin write-through mode
Memory access
Memory access
Data TLB multiplehit exception
Data TLB protectionviolation exception
Data TLB missexception
Initial page writeexception
Data TLB protectionviolation exception
Cache accessin copy-back mode
Data access to virtual address (VA)
On-chip I/O access
R/W?R/W?
VA is in P4 area
VA is in P2 area
VA is in P1 area
VA is in P0, U0, or P3 area
Yes
No
1
0
Yes
Yes
NoNo
Yes
Yes
Yes
No
No
1 (Privileged)
1
0
0
PR?
0 (User)
D?
R/W? WWW
RRR R
WR/W?
(Non-cacheable)
WT?
C = 1 and CCR.OCE = 1
No
1
1
0
0
00 or 01
10 11 01 or 11 00 or 10
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Figure 12: Flowchart of memory access using ITLB
MMUCR.AT = 1
SH = 0and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs matchand ASIDs match and
V = 1
Only oneentry matches
SR.MD?
CCR.ICE?
VPNs matchand V = 1
Memory access
Instruction TLBmultiple hit exception
Instruction TLBmiss exception
Instruction access to virtual address (VA)
VA is in P4 area
VA is in P2 area
VA is in P1 area
VA is in P0, U0, or P3 area
Yes
No
1
0
Yes
Yes
NoNo
Yes
Yes
No
(Non-cacheable)
C = 1and CCR.ICE = 1
No
PR?
Instruction TLB protectionviolation exception
Match? Record in ITLB
Access prohibited
0
1
No
Yes
Yes
No
Hardware ITLB miss handling
0 (User)1 (Privileged)
Search UTLB
Cache access
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3.6 MMU functions
3.6.1 MMU hardware management
The SH-4 CPU core supports the following MMU functions.
1 The MMU decodes the virtual address to be accessed by software, and performsaddress translation by controlling the UTLB/ITLB, in accordance with theMMUCR settings.
2 The MMU determines the cache access status, on the basis of the pagemanagement information read during address translation (C, WT bits).
3 If address translation cannot be performed normally in a data access orinstruction access, the MMU notifies software by means of an MMU exception.
4 If address translation information is not recorded in the ITLB in an instructionaccess, the MMU searches the UTLB, and if the necessary address translationinformation is recorded in the UTLB, the MMU copies this information into theITLB in accordance with MMUCR.LRUI.
3.6.2 MMU software management
Software processing for the MMU consists of the following:
1 Setting of MMU-related registers.Some registers are also partially updated by hardware automatically.
2 Recording, deletion, and reading of TLB entries.There are two methods of recording UTLB entries: by using the LDTLBinstruction, or by writing directly to the memory-mapped UTLB.
ITLB entries can only be recorded by writing directly to the memory-mappedITLB. For deleting or reading UTLB/ITLB entries, it is possible to access thememory-mapped UTLB/ITLB.
3 MMU exception handling.When an MMU exception occurs, processing is performed based on informationset by hardware.
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3.6.3 MMU instruction (LDTLB)
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When anLDTLB instruction is issued, the SH-4 CPU core copies the contents of PTEH andPTEL, to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updatedby the LDTLB instruction, and therefore address translation information purgedfrom the UTLB entry may still remain in the ITLB entry. As the LDTLB instructionchanges address translation information, ensure that it is issued by a program inthe P1 or P2 region. The operation of the LDTLB instruction is shown in Figure 13.
Figure 13: Operation of LDTLB instruction
PPN [28:10]
PPN [28:10]
PPN [28:10]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SH
SH
SH
C
C
C
PR [1:0]
PR [1:0]
PR [1:0]
ASID [7:0]
ASID [7:0]
ASID [7:0]
VPN [31:10]
VPN [31:10]
VPN [31:10]
V
V
V
Entry 0
Entry 1
Entry 2
D
D
D
WT
WT
WT
PPN [28:10] SZ [1:0] SH C PR [1:0]
SA [2:0]
SA [2:0]
SA [2:0]
TC
TC
TC
SA [2:0] TCASID [7:0] VPN [31:10] VEntry 63 D WT
31 29 28 9 8 7 6 5 4 3 2 1 0
— — V SZ PR SZ C D SHWT
PTEL
Write
UTLB
31 10 9 8 7 0
— ASID
PTEH
31 26 25 24 23 18 17 16 15 10 9 8 7 3 2 1 0
LRUI — URB — URC SV
SQMD
— TI — AT
MMUCR
VPN
10
PPN
31 4 3 2 0
— SATC
PTEA
Entry specification
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3.6.4 Hardware ITLB miss handling
In an instruction access, the SH-4 CPU core searches the ITLB. If it cannot find thenecessary address translation information (i.e. in the event of an ITLB miss), theUTLB is searched by hardware, and if the necessary address translationinformation is present, it is recorded in the ITLB. This procedure is known ashardware ITLB miss handling. If the necessary address translation information isnot found in the UTLB search, an instruction TLB miss exception is generated andprocessing passes to software.
3.6.5 Avoiding synonym problems
When 1 or 4-kbyte pages are recorded in TLB entries, a synonym problem may arise.The problem is that, when a number of virtual addresses are mapped onto a singlephysical address, the same physical address data may be recorded in a number ofcache entries, and it becomes impossible to guarantee data integrity. This problemdoes not occur with the instruction TLB or instruction cache. In the SH-4 CPU core,line selection is performed using bits [13:5] of the virtual address, as this avoids thecache having to go via the TLB and thus achieves faster operand cache operation.However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits[13:12] of the virtual address in the case of a 4-kbyte page, are subject to addresstranslation. As a result, bits [13:10] of the physical address after translation maydiffer from bits [13:10] of the virtual address.
Great care must therefore be taken whenever translations are set up which couldcause synonyms, in particular, if two operand translations are to the same physicalpage but their virtual addresses differ in their synonym bits:
• Do not allow both the translations to be active at the same time.
• Always separate activations of the two translations by an appropriate cachepurge.
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3.7 Handling MMU exceptionsThere are seven MMU exceptions.
3.7.1 ITLBMULTIHIT
An instruction TLB multiple hit exception occurs when, more than one ITLB entrymatches the virtual address to which an instruction access has been made. Ifmultiple hits occur when the UTLB is searched by hardware, in hardware ITLBmiss handling, a data TLB multiple hit exception will result.
When an instruction TLB multiple hit exception occurs a reset is executed, andcache coherency is not guaranteed.
Hardware processing
See Chapter 5: Exceptions on page 105, ITLBMULTIHIT - Instruction TLBMultiple-Hit Exception on page 118.
Software processing (reset routine)
The ITLB entries which caused the multiple hit exception are checked in the resethandling routine. This exception is intended for use in program debugging, andshould not normally be generated.
3.7.2 ITLBMISS
An instruction TLB miss exception occurs when, address translation information forthe virtual address to which an instruction access is made, is not found in the UTLBentries by the hardware ITLB miss handling procedure. The instruction TLB missexception processing, carried out by software, is shown below. This is the same asthe processing for a data TLB miss exception.
Hardware processing
See, Chapter 5: Exceptions on page 105, ITLBMISS - Instruction TLB MissException on page 122.
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Software processing (instruction TLB miss exception handling routine)
Software is responsible for searching the external memory page table and assigningthe necessary page table entry. Software should carry out the following processing inorder to find and assign the necessary page table entry.
1 Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in thepage table entry recorded in the external memory address translation table.
2 When the entry to be replaced in entry replacement is specified by software,write that value to URC in the MMUCR register. If URC is greater than URB atthis time, the value should be changed to an appropriate value after issuing anLDTLB instruction.
3 Execute the LDTLB instruction and write the contents of PTEH, PTEL, and tothe TLB.
4 Finally, execute the exception handling return instruction (RTE), terminate theexception handling routine, and return control to the normal flow. The RTEinstruction should be issued at least one instruction after the LDTLBinstruction.
3.7.3 EXECPROT
An instruction TLB protection violation exception occurs when, even though anITLB entry contains address translation information matching the virtual addressto which an instruction access is made, the actual access type is not permitted by theaccess right specified by the PR bit. The instruction TLB protection violationexception processing, carried out by software, is shown below.
Hardware processing
See Chapter 5: Exceptions on page 105, EXECPROT - Instruction TLB ProtectionViolation Exception on page 126.
Software processing (instruction TLB protection violation exception handlingroutine)
Resolve the instruction TLB protection violation, execute the exception handlingreturn instruction (RTE), terminate the exception handling routine, and returncontrol to the normal flow. The RTE instruction should be issued at least oneinstruction after the LDTLB instruction.
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3.7.4 OTLBMULTIHIT
An operand TLB multiple hit exception occurs when, more than one UTLB entrymatches the virtual address to which a data access has been made. A data TLBmultiple hit exception is also generated if multiple hits occur, when the UTLB issearched in hardware ITLB miss handling.
When an operand TLB multiple hit exception occurs, a reset is executed, and cachecoherency is not guaranteed. The contents of PPN in the UTLB prior to theexception may also be corrupted.
Hardware processing
See Chapter 5: Exceptions on page 105, OTLBMULTIHIT - Operand TLBMultiple-Hit Exception on page 119.
Software processing (reset routine)
The UTLB entries which caused the multiple hit exception are checked in the resethandling routine. This exception is intended for use in program debugging, andshould not normally be generated.
3.7.5 TLBMISS
A data TLB miss exception occurs when, address translation information for thevirtual address to which a data access is made is not found in the UTLB entries. Thedata TLB miss exception processing, carried out by software, is shown below.
Hardware processing
See Chapter 5: Exceptions on page 105, RTLBMISS - Read Data TLB MissException on page 120.
Software processing (data TLB miss exception handling routine)
Software is responsible for searching the external memory page table and assigningthe necessary page table entry. Software should carry out the following processing inorder to find and assign the necessary page table entry.
1 Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in thepage table entry recorded in the external memory address translation table.
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2 When the entry to be replaced in entry replacement is specified by software,write that value to URC in the MMUCR register. If URC is greater than URB atthis time, the value should be changed to an appropriate value after issuing anLDTLB instruction.
3 Execute the LDTLB instruction and write the contents of PTEH, PTEL, and tothe UTLB.
4 Finally, execute the exception handling return instruction (RTE), terminate theexception handling routine, and return control to the normal flow. The RTEinstruction should be issued at least one instruction after the LDTLBinstruction.
3.7.6 READPROT
A data TLB protection violation exception occurs when, even though a UTLB entrycontains address translation information matching the virtual address to which adata access is made, the actual access type is not permitted by the access rightspecified by the PR bit. The data TLB protection violation exception processing,carried out by software, is shown below.
Hardware processing
See Chapter 5: Exceptions on page 105, READPROT - Data TLB ProtectionViolation Exception on page 124
Software processing (data TLB protection violation exception handling routine)
Resolve the data TLB protection violation, execute the exception handling returninstruction (RTE), terminate the exception handling routine, and return control tothe normal flow. The RTE instruction should be issued at least one instruction afterthe LDTLB instruction.
3.7.7 FIRSTWRITE
An initial page write exception occurs when, the D bit is 0 even though a UTLBentry contains address translation information matching the virtual address towhich a data access (write) is made, and the access is permitted. The initial pagewrite exception processing, carried out by software, is shown below.
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Hardware processing
See Chapter 5: Exceptions on page 105, FIRSTWRITE - Initial Page Write Exceptionon page 123
Software processing (initial page write exception handling routine)
The following processing should be carried out as the responsibility of software:
1 Retrieve the necessary page table entry from external memory.
2 Write 1 to the D bit in the external memory page table entry.
3 Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in thepage table entry recorded in external memory.
4 When the entry to be replaced in entry replacement is specified by software,write that value to URC in the MMUCR register. If URC is greater than URB atthis time, the value should be changed to an appropriate value after issuing anLDTLB instruction.
5 Execute the LDTLB instruction and write the contents of PTEH, PTEL, and tothe UTLB.
6 Finally, execute the exception handling return instruction (RTE), terminate theexception handling routine, and return control to the normal flow. The RTEinstruction should be issued at least one instruction after the LDTLBinstruction.
3.8 Memory-mapped TLB configurationTo enable the ITLB and UTLB to be managed by software, their contents can beread and written by a P2 region program, with a MOV instruction in privilegedmode. Operation is not guaranteed if access is made from a program in anotherregion. A branch to a region other than the P2 region should be made at least 8instructions after this MOV instruction. The ITLB and UTLB are allocated to the P4region in physical address space. VPN, V and ASID in the ITLB can be accessed asan address array, PPN, V, SZ, PR, C, and SH as data array 1. VPN, D, V, and ASIDin the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SHas data array 1. V and D can be accessed from both the address array side and thedata array side. Only longword access is possible. Instruction fetches cannot beperformed in these regions. For reserved bits, a write value of 0 should be specified;their read value is undefined.
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3.8.1 ITLB address array
The ITLB address array is allocated to addresses 0xF200 0000 to 0xF2FF FFFF inthe P4 region. An address array access requires a 32-bit address field specification(when reading or writing), and a 32-bit data field specification (when writing).Information for selecting the entry to be accessed is specified in the address field,and VPN, V, and ASID to be written to the address array are specified in the datafield.
In the address field, bits [31:24] have the value 0xF2 indicating the ITLB addressarray, and the entry is selected by bits [9:8]. As longword access is used, 0 should bespecified for address field bits [1:0].
In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits[7:0].
The following two kinds of operation can be used on the ITLB address array:
1 ITLB address array read
VPN, V, and ASID are read into the data field from the ITLB entrycorresponding to the entry set in the address field.
2 ITLB address array write
VPN, V, and ASID specified in the data field are written to the ITLB entrycorresponding to the entry set in the address field.
Figure 14: Memory-mapped ITLB address array
Address field31 23 0
1 1 1 1 0 0 1 0 E
Data field31 10 9 0
VVPN
VPN:V:
E:
24
Virtual page numberValidity bitEntry
10 9 8 7
9 8 7
ASID
ASID::
Address space identifierReserved bits (0 write value, undefinedread value)
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3.8.2 ITLB data array 1
ITLB data array 1 is allocated to addresses 0xF300 0000 to 0xF37F FFFF in the P4region. A data array access requires a 32-bit address field specification (whenreading or writing), and a 32-bit data field specification (when writing). Informationfor selecting the entry to be accessed is specified in the address field, and PPN, V,SZ, PR, C, and SH to be written to the data array are specified in the data field.
In the address field, bits [31:23] have the value 0xF30 indicating ITLB data array 1,and the entry is selected by bits [9:8].
In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4],PR by bit [6], C by bit [3], and SH by bit [1].
The following two kinds of operation can be used on ITLB data array 1:
1 ITLB data array 1 read
PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entrycorresponding to the entry set in the address field.
2 ITLB data array 1 write
PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLBentry corresponding to the entry set in the address field.
Figure 15: Memory-mapped ITLB data array 1
Address field31 23 0
1 1 1 1 0 0 01 1 E
Data field
PPN:V:E:
SZ:
24
Physical page numberValidity bitEntryPage size bits
10 9 8 7
PR:C:
SH::
Protection key dataCacheability bitShare status bitReserved bits (0 write value, undefinedread value)
31 2 1 0
V
10 9 8 730 29 28 4 36 5
SZ SHPR
CPPN
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3.8.3 UTLB address array
The UTLB address array is allocated to addresses 0xF600 0000 to 0xF6FF FFFF inthe P4 region. An address array access requires a 32-bit address field specification(when reading or writing), and a 32-bit data field specification (when writing).Information for selecting the entry to be accessed is specified in the address field,and VPN, D, V, and ASID to be written to the address array are specified in the datafield.
In the address field, bits [31:24] have the value 0xF6 indicating the UTLB addressarray, and the entry is selected by bits [13:8]. The address array bit [7] associationbit (A bit), specifies whether or not address comparison is performed when writingto the UTLB address array.
In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASIDby bits [7:0].
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The following three kinds of operation can be used on the UTLB address array:
1 UTLB address array read
VPN, D, V, and ASID are read into the data field from the UTLB entrycorresponding to the entry set in the address field. In a read, associativeoperation is not performed, regardless of whether the association bit specified inthe address field is 1 or 0.
2 UTLB address array write (non-associative)
VPN, D, V, and ASID specified in the data field are written to the UTLB entrycorresponding to the entry set in the address field. The A bit in the address fieldshould be cleared to 0.
3 UTLB address array write (associative)
When a write is performed with the A bit in the address field set to 1,comparison of all the UTLB entries is carried out using the VPN specified in thedata field and PTEH.ASID. The usual address comparison rules are followed,but if a UTLB miss occurs, the result is no operation, and an exception is notgenerated. If the comparison identifies a UTLB entry, corresponding to the VPNspecified in the data field, D and V specified in the data field are written to thatentry. If there is more than one matching entry, a data TLB multiple hitexception results. This associative operation is simultaneously carried out on theITLB, and if a matching entry is found in the ITLB, V is written to that entry.Even if the UTLB comparison results in no operation, a write to the ITLB sideonly is performed as long as there is an ITLB match. If there is a match in boththe UTLB and ITLB, the UTLB information is also written to the ITLB.
Figure 16: Memory-mapped UTLB address array
Address field
Data field
VPN:V:E:D:
Virtual page numberValidity bitEntryDirty bit
ASID:A:
:
Address space identifierAssociation bitReserved bits (0 write value, undefinedread value)
31 0
VD
10 9 8 730 2928
A
8 7
ASIDVPN
31 23 2 1 0
1 1 1 1 0 1 1 0 E
24 14 13
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3.8.4 UTLB data array 1
UTLB data array 1 is allocated to addresses 0xF700 0000 to 0xF77F FFFF in the P4region. A data array access requires a 32-bit address field specification (whenreading or writing), and a 32-bit data field specification (when writing). Informationfor selecting the entry to be accessed is specified in the address field, and PPN, V,SZ, PR, C, D, SH, and WT to be written to the data array, are specified in the datafield.
In the address field, bits [31:23] have the value 0xF70 indicating UTLB data array1, and the entry is selected by bits [13:8].
In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4],PR by bits [6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0].
The following two kinds of operation can be used on UTLB data array 1:
1 UTLB data array 1 read
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field, from the UTLBentry corresponding to the entry set in the address field.
2 UTLB data array 1 write
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field, are written to theUTLB entry corresponding to the entry set in the address field.
Figure 17: Memory-mapped UTLB data array 1
Address field
Data field
PPN:V:E:
SZ:D:
Physical page numberValidity bitEntryPage size bitsDirty bit
PR:C:
SH:WT:
:
Protection key dataCacheability bitShare status bitWrite-through bitReserved bits (0 write value, undefined read value)
31 2 1 0
V
10 9 8 730 29 28 4 36 5
PR CPPN
31 23 0
1 1 1 1 0 1 1 1 0 E
24 8 714 13
D
SZ SH WT
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4Caches
4.1 Overview
4.1.1 Features
Note: This chapter details both the SH4-103 and SH4-202 variants. Please refer to yourdatasheet for specific core details.
The SH-4 CPU core has an on-chip 8-kbyte instruction cache (IC) for instructionsand 16-kbyte operand cache (OC) for data. Half of the memory of the operand cache(8 kbytes) can also be used as on-chip RAM. The features of these caches aresummarized in Table 14.
The SH4-202 has an on-chip 16-kbyte instruction cache (IC) for instructions and32-kbyte operand cache (OC) for data. Half of the operand cache (16 kbytes) can alsobe used as on-chip RAM. The features of these caches are summarized in Table 14and Table 15.
The SH-4 CPU supports two 32-byte store queues (SQ) to perform high-speed writesto external memory. The features of the SQ are summarized in Table 16.
Item Instruction cache Operand cache
Capacity 8-kbyte cache 16-kbyte cache or 8-kbytecache + 8-kbyte RAM
Type Direct mapping Direct mapping
Line size 32 bytes 32 bytes
Table 14: Cache features (SH4-103, SH4-202 in compatibility mode)
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Entries 256 512
Write method Copy-back/write-throughselectable
Item Instruction cache Operand cache
Table 14: Cache features (SH4-103, SH4-202 in compatibility mode)
Item Instruction cache Operand cache
Capacity 16-kbyte cache 32-kbyte cache or 16-kbyte
cache + 16-kbyte RAM
Type 2way set associative 2way set associative
Line size 32 bytes 32 bytes
Entries 256 entry /way 512 entry / way
Write method Copy-back/write-through
selectable
Replace algorithm LRU LRU
Table 15: Cache features (SH4-202 in the enhanced mode)
Item Store queues
Capacity 2 × 32 bytes
Addresses 0xE000 0000 to 0xE3FF FFFF
Write Store instruction
Write-back Prefetch instruction
Access right MMU off: according to MMUCR.SQMD
MMU on: according to individual page PR
Table 16: Store queue features
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4.2 Register descriptionsThere are three cache and store queue related control registers.
4.2.1 Cache control register (CCR)
CCR can be accessed by longword-size access from 0xFF00001C in the P4 region and0x1F00001C in Area 7. The CCR bits are used to modify the cache settings describedbelow. CCR modifications must only be made by a program in the non-cached P2region. After CCR is updated, an instruction that performs data access to the P0, P1,P3, or U0 regions, should be located at least four instructions after the CCR updateinstruction. Also, a branch instruction to the P0, P1, P3, or U0 regions should belocated at least eight instructions after the CCR update instruction.
Name Abbreviation R/WInitial
valueaP4
addressbArea 7
addressbAccesssize
Cache controlregister
CCR R/W 0x0000 0000 0xFF00 001C 0x1F00 001C 32
Queue addresscontrol register 0
QACR0 R/W Undefined 0xFF00 0038 0x1F00 0038 32
Queue addresscontrol register 1
QACR1 R/W Undefined 0xFF00 003C 0x1F00 003C 32
Table 17: Cache control registers
a. The initial value is the value after a power-on or manual reset.
b. This is the address when using the virtual/physical address space P4 area. The area 7address is the address used when making an access from physical address space area7 using the TLB.
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CCR
Field Bits Size Synopsis Type
OCE 0 1 OC enable. RW
Operation Indicates whether or not the OC is to be used. When address trans-lation is performed, the OC cannot be used unless the C bit in thepage management information is also 1.
0: OC not used.
1: OC used.
Power-on reset 0
WT 1 1 Write-through enable. RW
Operation Indicates the P0, U0 and P3 region cache write mode. Whenaddress translation is performed, the value of the WT bit in the pagemanagement information has priority.
0: Copy-back mode.
1: Write-through mode.
Power-on reset 0
CB 2 1 Copy-back bit. RW
Operation Indicates the P1 region cache write mode.
0: Write-through mode.
1: Copy-back mode.
Power-on reset 0
OCI 3 1 OC invalidation bit. RW
Operation When 1 is written to this bit, the V and U bits of all OC entries arecleared to 0. This bit always returns 0 when read.
Power-on reset 0
Table 18: CCR register description
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ORA 5 1 OC RAM enable bit. RW
Operation 0: Normal mode (all of OC is used as cache).
1: RAM mode (half of OC is used as cache, the other half is used asRAM. Please refer to Section 4.3.6).
Power-on reset 0
OIX 7 1 OC index enable bit. RW
Operation 0: Address bits [13:5] used for OC entry selection.
1: Address bits [25] and [12:5] used for OC entry selection.
Note: In SH4-202, when CCR.ORA is set to 1, CCR.OIX must be setto 0. Please refer to Section 4.3.7.
Power-on reset 0
ICE 8 1 IC enable bit. RW
Operation Indicates whether or not the IC is to be used. When address transla-tion is to be performed, the IC cannot be used unless the C bit in thepage management information is also 1.
0: IC not used.
1: IC used.
Power-on reset 0
ICI 11 1 IC invalidation bit. RW
Operation When 1 is written to this bit, the V bits of all IC entries are cleared to0. This bit always returns 0 when read.
Power-on reset 0
IIX 15 1 IC index enable bit. RW
Operation 0: Address bits [12:5] used for IC entry selection.
1: Address bits [25] and [11:5] used for IC entry selection.
Power-on reset 0
CCR
Field Bits Size Synopsis Type
Table 18: CCR register description
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4.2.2 Queue address control register 0 (QACR0)
QACR0 can be accessed by longword-size access from 0xFF000038 in the P4 region,and 0x1F000038 in Area 7.
EMODE 31 1 Enhanced mode SH4-202 only. RW
Operation Indicates whether or not the OC is to be used in enhanced mode.
0: Compatible mode*.
1: Enhanced mode.
*: SH4-202 is not compatible with SH4-103 in the followingconditions:1. OC index mode and RAM mode.2. Address map in RAM mode.
Power-on reset 0
Reservedbits
4, 6,[10:9][14:12][30:16]
23 For maximum forward compatibility preserve values onwrite, otherwise write 0. Read is undefined.
Power-on reset
CCR
Field Bits Size Synopsis Type
Table 18: CCR register description
QACR0
Field Bits Size Synopsis Type
Area [2,4] 3 Queue address control register 0. RW
Operation QACR0 specifies the area onto which store queue 0 (SQ0) ismapped when the MMU is off.
Power-on reset Undefined
Table 19: QACR0
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4.2.3 Queue address control register 1 (QACR1)
QACR1 can be accessed by longword-size access from 0xFF00003C in the P4 region,and 0x1F00003C in Area 7.
Reserved bits [0,1],[5,31]
29
Power-on reset
QACR0
Field Bits Size Synopsis Type
Table 19: QACR0
QACR1
Field Bits Size Synopsis Type
Area [2,4] 3 Queue address control register 1. RW
Operation QACR1 specifies the area onto which store queue 1 (SQ1) ismapped when the MMU is off.
Power-on reset Undefined
Reserved bits [0,1],[5,31]
29
Power-on reset
Table 20: QACR1
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4.3 Operand cache (OC)
4.3.1 Configuration
Figure 18 shows the configuration of the operand cache for the SH4-103 whileFigure 19 shows the same for the SH4-202.
Figure 18: Configuration of operand cache on SH4-103 and SH-202 in compatibility mode
31 26 25 5 4 3 2 1
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits
MMU
RAM areadetermination
ORAOIX[13] [12]
[11:5]
511 19 bits 1 bit 1 bit
Tag address U V
Address array Data array
Ent
ry s
elec
tion
Longword (LW) selection
Effective address
39
22
19
0
Write dataRead data
Hit signal
Compare
13 12 11 10 9 0
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The operand cache for the SH4-103 consists of 512 cache lines, each composed of a19-bit tag, V bit, U bit, and 32-byte data.
The SH4-202 operand cache is 2 way associative cache and consists of 512 cachelines/way, each composed of a 19-bit tag, V bit and 32-byte data.
• Tag
Stores the upper 19 bits of the 29-bit external address of the data line to becached. The tag is not initialized by a power-on or manual reset.
Figure 19: Configuration of instruction cache on the SH4-202
Effective address
31 25 14 13 12 10 5 4 2 026 24 9
OIX
[13]
[12:5] Longword (LW)selection
22 9
3
Address array (Way0, Way1) Data array (Way0, Way1)
0
LRU
MMU
Hit signal
Compare
Way0
CompareWay1
19 bit 1 bit 32 bit 1 bit32 bit32 bit 32 bit32 bit 32 bit32 bit 32 bit
Tag address V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
Read data
19
1
RAM area
ORA
Entryselection
U
1 bit
Write data
511
determination
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• V bit (validity bit)
Setting this bit to 1, indicates that valid data is stored in the cache line. The Vbit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
• U bit (dirty bit)
The U bit is set to 1 if data is written to the cache line, while the cache is beingused in copy-back mode, that is the U bit indicates a mismatch between the datain the cache line and the data in external memory. The U bit is never set to 1while the cache is being used in write-through mode, unless it is modified byaccessing the memory-mapped cache (see Section 4.5: Memory-mapped cacheconfiguration on page 95). The U bit is initialized to 0 by a power-on reset, butretains its value in a manual reset.
• Data field
The data field holds 32 bytes (256 bits) of data per cache line. The data array isnot initialized by a power-on or manual reset.
• LRU (SH-4 200 series only)
When a 200 series SH-4 is operating in enhanced mode, an additional state bit isdeployed to keep track of which of the two ways in each cache set was leastrecently used (LRU). These additional LRU bits can not be read or written bysoftware.
4.3.2 Read operation
When the OC is enabled (CCR.OCE = 1) and data is read by means of an effectiveaddress from a cacheable area, the cache operates as follows:
1 The tag, V bit, and U bit are read from the cache line, indexed by effectiveaddress bits [13:5].
2 The tag is compared with bits [28:10] of the address resulting from effectiveaddress translation by the MMU. Operation is as described in Table 2.
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Tagmatch
V bit U bit Operation Description
Yes 1 - Cache hit The data indexed by bits [4:0] of the effective address, isread from the cache line indexed by bits [13:5], inaccordance with the access size (quadword/longword/word/byte).
Yes 0 - Cache miss(nowrite-back)
Data from the external memory space, corresponding tothe effective address, is written into the cache line. Datareading is performed, using the critical word first method,and when the date arrives in the cache, the read data isreturned to the CPU. The CPU continues to execute thenext process, while the cache line of data is being read.When reading of one line of data is completed, the tagcorresponding to the effective address is recorded in thecache, and the V bit is set to 1.
No 0 -
No 1 0
No 1 1 Cache miss(withwrite-back)
The tag and data field of the cache line, indexed byeffective address bits [13:5], are saved in the write-backbuffer. Then, data from the external memory space,corresponding to the effective address, is written into thecache line.Data reading is performed, using the criticalword first method, and when the date arrives in thecache, the read data is returned to the CPU. The CPUcontinues to execute the next process, while the cacheline of data is being read. When reading of one line ofdata is completed, the tag corresponding to the effectiveaddress is recorded in the cache, the V bit is set to 1,and the U bit is set to 0. The data in the write-back bufferis then written back to the external memory.
Table 21: OC read operation
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4.3.3 Write operation
When the OC is enabled (CCR.OCE = 1) and data is written by means of an effectiveaddress to a cacheable area, the cache operates as follows:
1 The tag, V bit, and U bit are read from the cache line indexed by effectiveaddress bits [13:5].
2 The tag is compared with bits [28:10] of the address resulting from effectiveaddress translation by the MMU. In copy back, operation is per Table 22. Inwrite through mode it is per Table 23.
Tag match V bit U bit Operation Description
Yes 1 - Cache hit(copy-back)
A data write for the data indexed by bits [4:0] is per-formed, in accordance with the access size (quadword/longword/word/byte).
Yes 0 - Cache miss(nocopy-back/write-back)
A data write for the data indexed by bits [4:0] is per-formed, in accordance with the access size (quadword/longword/word/byte). Then, data from the external mem-ory corresponding to the effective address, is read intothe cache line. Data reading is performed, using the crit-ical word first method, and one cache line of data isread, excluding the written data.The CPU continues toexecute the next process, while the cache line of data isbeing read. When reading of one line of data is com-pleted, the tag corresponding to the effective address isrecorded in the cache, the V bit and U bit are both set to1.
No 0 -
No 1 0
Table 22: OC write operation, with copy-back
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No 1 1 Cache miss(withcopy-back/write-back)
The tag and data field of the cache line, indexed byeffective address bits [13:5] are first saved in thewrite-back buffer. Then, a data write for the data indexedby bits [4:0], is performed in accordance with the accesssize (quadword/longword/word/byte). Data from theexternal memory space, corresponding to the effectiveaddress, is read into the cache line. Data reading is per-formed, using the critical word first method, and onecache line of data is read, excluding the written data.TheCPU continues to execute the next process, while thecache line of data is being read. When reading of oneline of data is completed, the tag corresponding to theeffective address is recorded in the cache, the V bit andU bit are both set to 1. The data in the write back bufferis then written back to external memory.
Tag match V bit U bit Operation Description
Yes 1 - Cache-hit(write-through)
A data write for the data indexed by bits [4:0], is per-formed in accordance with the access size (quadword/longword/word/byte). The U bit is set to 1.
Yes 0 - Cache miss(write-through)
A write is performed to the external memory, corre-sponding to the effective address. A write to cache isnot performed.No 0 -
No 1 0
No 1 1
Table 23: OC write operation, with write-through
Tag match V bit U bit Operation Description
Table 22: OC write operation, with copy-back
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4.3.4 Write-back buffer
The write-back buffer enables priority to be given to data reads, and improvesperformance. When a cache miss makes the purge of a dirty cache entry intoexternal memory necessary, the cache entry is held in the write-back buffer. Thewrite-back buffer contains one cache line of data and the physical address of thepurge destination.
4.3.5 Write-through buffer
When writing data in write-through mode or writing to a non-cacheable area, datais held in a 64-bit buffer. This allows the CPU to proceed to the next operation assoon as the write to the write-through buffer is completed, without waiting forcompletion of the write to external memory.
4.3.6 RAM mode
SH-4 100 series
Setting CCR.ORA to 1 enables 8 kbytes of the operand cache to be used as RAM. Theoperand cache entries used as RAM are, entries 128 to 255 and 384 to 511. Otherentries can still be used as cache. RAM can be accessed using addresses 0x7C000000 to 0x7FFF FFFF. Byte-, word-, longword-, and quadword-size data reads andwrites can be performed in the operand cache RAM area. Instruction fetches cannotbe performed in this area.
Note: On the SH4-202, RAM mode cannot be used in conjunction with OC index mode evenwhen in compatibility mode.
Figure 20: Configuration of write-back buffer
LW7Physical address bits [28:5] LW6LW5LW4LW3LW2LW1LW0
Figure 21: Configuration of write-through buffer
Physical address bits [28:0] LW1LW0
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An example of RAM use is shown below. Here, the 4 kbytes comprising OC entries128 to 256 are designated as RAM area 1, and the 4 kbytes comprising OC entries384 to 511 as RAM area 2.
• When OC index mode is off (CCR.OIX = 0):
Thus, to secure a continuous 8-kbyte RAM area, the area from 0x7C00 1000 to0x7C00 2FFF can be used, for example.
• When OC index mode is on (CCR.OIX = 1):
As the distinction between RAM areas 1 and 2 is indicated by address bit [25],the area from 0x7DFF F000 to 0x7E00 0FFF should be used to secure acontinuous 8-kbyte RAM area.
Address start Address end Size RAM area
0x7C00 0000 0x7C00 0FFF 4-kbytes 1
0x7C00 1000 0x7C00 1FFF 1
0x7C00 2000 0x7C00 2FFF 2
0x7C00 3000 0x7C00 3FFF 2
0x7C00 4000 0x7C00 4FFF 1a
a. RAM areas 1 and 2 then repeat evert 8Kbytes upto 0x7FFF FFFF.
Table 24: RAM use when OC index mode is off
Address start Address end Size RAM area
0x7C00 0000 0x7C00 0FFF 4-kbytes 1
0x7C00 1000 0x7C00 1FFF 1
0x7C00 2000 0x7C00 2FFF 1
... ... 1
0x7DFF F000 0x7DFF FFFF 1
0x7E00 0000 0x7E00 0FFF 2
0x7E001000 0x7E00 1FFF 2
... ... 2
0x7FFF F000 0x7FFF FFFF 2
Table 25: RAM use when OC index mode is on
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RAM Mode of SH4-202
Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. Theoperand cache entries used as RAM are entries 256 to 511 in the compatible mode.The operand cache entries used as RAM are entries 256 to 511 of each way in theenhanced mode. Other entries can still be used as cache. RAM can be accessed usingaddresses 0x7C00 0000 to 0x7FFF FFFF. Byte-, word-, longword-, andquadword-size data reads and writes can be performed in the operand cache RAMarea. Instruction fetches cannot be performed in this area.
Even when in compatibility mode, the OC index mode cannot be used in conjunctionwith RAM mode on a 200 series part.
RAM mode address map of SH4-202
An example of RAM use is shown below. Here, the 8 kbytes comprising OC entries256 to 511 of way 0 are designated as RAM area 1, and the 8 kbytes comprising OCentries 256 to 511 of way 1 as RAM area 2.
In the compatible mode (CCR.EMODE=0)
In the enhanced mode (CCR.EMODE=1)
Address start Address end Size RAM area
0x7C00 0000 0x7C00 1FFF 8-Kbytes 256-511
0x7C00 2000 0x7C00 3FFF 8-Kbytes 256-511
Repeated until...
0x7FFF E000 0x7FFF FFFF 8-Kbytes 256-511
Table 26: Compatible mode
Address start Address end Size RAM area
0x7C00 0000 0x7C00 1FFF 8-Kbytes 1
0x7C00 2000 0x7C00 3FFF 8-Kbytes 2
0x7C00 4000 0x7C00 5FFF 8-Kbytes 1
0x7C00 6000 0x7C00 7FFF 8-Kbytes 2
RAM areas 1 and 2 then repeat every 16Kbytes until...
0x7FFF C000 0x7FFF FFFF 16-Kbytes
Table 27: Compatible mode
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4.3.7 OC index mode
OC index mode is only available on the SH-4 100 series or when a 200 series part isused in compatibility mode and RAM mode is not being used.
In normal mode, with CCR.OIX cleared to 0, OC indexing is performed using bits[13:5] of the effective address. Using index mode, with CCR.OIX set to 1, allows theOC to be handled as two 8-kbyte areas, by means of effective address bit [25]. Thispartitioning makes it possible for the software to make more efficient use of thecache.
4.3.8 Coherency between cache and external memory
Coherency between cache and external memory should be assured by software. Inthe SH-4 CPU core, the following four new instructions are supported for cacheoperations. Details of these instructions are given in the Instruction Descriptionschapter.
4.3.9 Prefetch operation
The SH-4 CPU core supports a prefetch instruction, to reduce the cache fill penaltyincurred as the result of a cache miss. If it is known that a cache miss will resultfrom a read or write operation, it can be prevented by using the prefetch instructionto fill the cache with data before the operation, and so improve softwareperformance. If a prefetch instruction is executed for data already held in the cache,or if the prefetch address results in a UTLB miss or a protection violation, the resultis no operation, and an exception is not generated. Details of the prefetchinstruction are given in the Instruction Descriptions chapter.
Prefetch instruction: PREF @Rn
Invalidate instruction: OCBI @Rn Cache invalidation (no write-back)
Purge instruction: OCBP @Rn Cache invalidation (with write-back)
Write-back instruction: OCBWB @Rn Cache write-back
Allocate instruction: MOVCA.L R0,@Rn Cache allocation
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4.4 Instruction cache (IC)
4.4.1 Configuration
Figure 22 shows the configuration of the instruction cache for SH4-103, whileFigure 23 shows the IC for the SH4-202.
Figure 22: Configuration of instruction cache on the SH4-103 (and SH4-202 in compatibility mode)
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits255 19 bits 1 bit
Tag address V
Address array
Longword (LW) selection
Data array
0
Read data
Hit signal
Compare
31 26 25 5 4 3 2 1
MMU
IIX[12]
[11:5]
Ent
ry s
elec
tion
Effective address
8 3
22
19
13 12 11 10 9 0
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The instruction cache for the SH4-103 consists of 256 cache lines, each composed ofa 19-bit tag, V bit, and 32-byte data (16 instructions).
The instruction cache for the SH4-202 consists of 256 cache lines/way, eachcomposed of a 19-bit tag, V bit, and 32-byte data (16 instructions).
• Tag
Stores the upper 19 bits of the 29-bit external memory address of the data line tobe cached. The tag is not initialized by a power-on or manual reset.
• V bit (validity bit)
Setting this bit to 1Indicates that valid data is stored in the cache line. The V bitis initialized to 0 by a power-on reset, but retains its value in a manual reset.
Figure 23: Configuration of instruction cache on the SH4-202 in enhanced mode (CCR.EMODE=1)
Effective address
31 26 13 12 11 10 5 4 2 027 25 9
IIX
[12]
[11:5]
Entry selection
Longword (LW)selection
22 83
Address array (Way0, Way1) Data array (Way0, Way1)
0
LRU
MMU
Hit signal
Compare
Way0
CompareWay1
19 bit 1 bit 32 bit 1 bit32 bit32 bit 32 bit32 bit 32 bit32 bit 32 bit
Tag address V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
Read data
19
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• Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array isnot initialized by a power-on or manual reset.
• LRU (SH-4 200 series only)
When a 200 series SH-4 is operating in enhanced mode, an additional state bit isdeployed to keep track of which of the two ways in each cache set was leastrecently used (LRU). These additional LRU bits can not be read or written bysoftware.
4.4.2 Read operation
When the IC is enabled (CCR.ICE = 1), and instruction fetches are performed bymeans of an effective address from a cacheable area, the instruction cache operatesas follows:
1 The tag and V bit are read from the cache line indexed by effective address bits[12:5].
2 The tag is compared with bits [28:10] of the address resulting from effectiveaddress translation by the MMU:
4.4.3 IC index mode
IC index mode is only available on the SH-4 100 series or when a 200 series part isused in compatibility mode.
Tag V bit Operation Description
Matches 1 Cache hit Data indexed by effective address bits [4:2], is read asan instruction.
Matches 0 Cache miss Data is read into the cache line, from the external mem-ory space corresponding to the effective address. Datareading is performed, using the critical word first method,and when the data arrives in the cache, the read data isreturned to the CPU as an instruction. When reading ofone line of data is completed, the tag corresponding tothe effective address is recorded in the cache, and 1 iswritten to the V bit.
Does notmatch
0
Does notmatch
1
Table 28: IC read operation
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In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits[12:5] of the effective address. Using index mode, with CCR.IIX set to 1, allows theIC to be handled as two 4-kbyte areas by means of effective address bit [25]. Thisprovides efficient use of the cache.
4.5 Memory-mapped cache configurationTo enable the IC and OC to be managed by software, IC content can be read andwritten by a P2 region program, with a MOV instruction in privileged mode.Behavior is undefined if access is made from a program in another region. In thiscase, a branch to the P0, U0, P1, or P3 regions should be made at least 8 instructionsafter this MOV instruction.
The OC content can be read and written by a P1 and P2 regions program, with aMOV instruction in privileged mode. Behavior is undefined if access is made from aprogram in another region. In this case, a branch to the P0, U0, or P3 regions shouldbe made at least 8 instructions after this MOV instruction.
The IC and OC are allocated to the P4 region in physical memory space. Only(longword) data accesses can be used on both the IC address array and data array,and the OC address array and data array. Instruction fetches cannot be performedin these regions. For reserved bits, a write value of 0 should be specified; their readvalue is undefined.
4.5.1 IC address array
The IC address array is allocated to addresses 0xF000 0000 to 0xF0FF FFFF in theP4 region. An address array access requires a 32-bit address field specification(when reading or writing), and a 32-bit data field specification. The entry to beaccessed is specified in the address field, and the write tag and V bit are specified inthe data field.
In the address field, bits [31:24] have the value 0xF0 indicating the IC addressarray, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entryspecification. The address array bit [3], the association bit (A bit), specifies whetheror not association is performed when writing to the IC address array. As onlylongword access is used, 0 should be specified for address field bits [1:0].
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In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As theIC address array tag is 19 bits in length, data field bits [31:29] are not used in thecase of a write in which association is not performed. Data field bits [31:29] are usedfor the virtual address specification, only in the case of a write in which associationis performed.
The following three kinds of operation can be used on the IC address array:
1 IC address array readThe tag and V bit are read into the data field from the IC entry corresponding tothe entry set in the address field. In a read, associative operation is notperformed, regardless of whether the association bit specified in the addressfield is 1 or 0.
2 IC address array write (non-associative)The tag and V bit specified in the data field are written to the IC entrycorresponding to the entry set in the address field. The A bit in the address fieldshould be cleared to 0.
3 IC address array write (associative)When a write is performed with the A bit in the address field set to 1, the tagstored in the entry specified in the address field, is compared with the tagspecified in the data field. If the MMU is enabled at this time, comparison isperformed after the virtual address, specified by data field bits [31:10], has beentranslated to a physical address using the ITLB. If the addresses match and theV bit is 1, the V bit specified in the data field is written into the IC entry. In othercases, no operation is performed. This operation is used to invalidate a specificIC entry. If an ITLB miss occurs during address translation, or the comparisonshows a mismatch, an interrupt is not generated, no operation is performed, andthe write is not executed. If an instruction TLB multiple hit exception occursduring address translation, processing switches to the instruction TLB multiplehit exception handling routine.
Figure 24: Memory-mapped IC address array
Address field31 23 12 5 4 3 2 1 0
1 1 1 1 0 0 0 0 Entry A
Data field31 10 9 1 0
VTag address
VA
24 13
: Validity bit: Association bit: Reserved bits (0 write value, undefined read value)
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4.5.4 IC data array
The IC data array is allocated to addresses 0xF100 0000 to 0xF1FF FFFF in the P4region. A data array access requires a 32-bit address field specification (whenreading or writing), and a 32-bit data field specification. The entry to be accessed isspecified in the address field, and the longword data to be written is specified in thedata field.
In the address field, bits [31:24] have the value 0xF1 indicating the IC data array,and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entryspecification. Address field bits [4:2] are used for the longword data specification inthe entry. As only longword access is used, 0 should be specified for address field bits[1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the IC data array:
1 IC data array readLongword data is read into the data field, from the data specified by thelongword specification bits in the address field in the IC entry, corresponding tothe entry set in the address field.
2 IC data array writeThe longword data specified in the data field is written, for the data specified bythe longword specification bits in the address field in the IC entry, correspondingto the entry set in the address field.
Figure 25: Memory-mapped IC data array
Address field31 23 12 5 4 2 1 0
1 1 1 1 0 0 0 1 Entry L
Data field31 0
Longword data
L
24 13
: Longword specification bits: Reserved bits (0 write value, undefined read value)
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4.5.5 OC address array
The OC address array is allocated to addresses 0xF400 0000 to 0xF4FF FFFF in theP4 region. An address array access requires a 32-bit address field specification(when reading or writing), and a 32-bit data field specification. The entry to beaccessed is specified in the address field, and the write tag, U bit, and V bit arespecified in the data field.
In the address field, bits [31:24] have the value 0xF4 indicating the OC addressarray, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have noeffect on this entry specification. The address array bit [3], association bit (A bit),specifies whether or not association is performed when writing to the OC addressarray. As only longword access is used, 0 should be specified for address field bits[1:0].
In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the Vbit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29]are not used in the case of a write in which association is not performed. Data fieldbits [31:29] are used for the virtual address specification only in the case of a writein which association is performed.
The following three kinds of operation can be used on the OC address array:
1 OC address array read
The tag, U bit, and V bit are read into the data field from the OC entrycorresponding to the entry set in the address field. In a read, associativeoperation is not performed, regardless of whether the association bit specified inthe address field is 1 or 0.
2 OC address array write (non-associative)
The tag, U bit, and V bit specified in the data field are written to the OC entrycorresponding to the entry set in the address field. The A bit in the address fieldshould be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both1, after write-back of that cache line, the tag, U bit, and V bit specified in thedata field are written.
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3 OC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tagstored in the entry specified in the address field is compared with the tagspecified in the data field. If the MMU is enabled at this time, comparison isperformed after the virtual address specified by data field bits [31:10] has beentranslated to a physical address using the UTLB. If the addresses match and theV bit is 1, the U bit and V bit specified in the data field are written into the OCentry. This operation is used to invalidate a specific OC entry. In other cases, nooperation is performed. If the OC entry U bit is 1, and 0 is written to the V bit orto the U bit, write-back is performed. If a UTLB miss occurs during addresstranslation, or the comparison shows a mismatch, an exception is not generated,no operation is performed, and the write is not executed. If a data TLB multiplehit exception occurs during address translation, processing switches to the dataTLB multiple hit exception handling routine.
4.5.6 OC data array
The OC data array is allocated to addresses 0xF500 0000 to 0xF5FF FFFF in the P4region. A data array access requires a 32-bit address field specification (whenreading or writing), and a 32-bit data field specification. The entry to be accessed isspecified in the address field, and the longword data to be written is specified in thedata field.
In the address field, bits [31:24] have the value 0xF5 indicating the OC data array,and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect onthis entry specification. Address field bits [4:2] are used for the longword dataspecification in the entry. As only longword access is used, 0 should be specified foraddress field bits [1:0].
Figure 26: Memory-mapped OC address array
Address field31 23 5 4 3 2 1 0
1 1 1 1 0 1 0 0 Entry A
Data field31 10 9 1 0
VTag address
24 1314
2
U
VUA
: Validity bit: Dirty bit: Association bit: Reserved bits (0 write value, undefined read value)
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The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
1 OC data array read
Longword data is read into the data field, from the data specified by thelongword specification bits in the address field, in the OC entry corresponding tothe entry set in the address field.
2 OC data array write
The longword data specified in the data field is written for the data specified bythe longword specification bits in the address field in the OC entrycorresponding the entry set in the address field. This write does not set the U bitto 1 on the address array side.
Memory-mapped OC configuration in the enhanced mode (SH4-202)
• Normal mode (0xF500 3FFF (16 Kbyte): Corresponds to Way0 (entry 0 - 511)0xF500 4000 to 0xF500 7FFF (16 Kbyte): Corresponds to Way1 (entry 0 - 511) : : :Cache area then repeat every 32 kbytes up to 0xF5FF FFFF.
• RAM mode (CCR.ORA=1)
0xF500 0000 to 0xF500 1FFF (8 Kbyte): Corresponds to Way0 (entry 0 - 255)0xF500 2000 to 0xF500 3FFF (8 Kbyte): Corresponds to Way1 (entry 0 - 255) : : :Cache area then repeat every 16 kbytes up to 0xF5FF FFFF.
Figure 27: Memory-mapped OC data array
Address field31 23 5 4 2 1 0
1 1 1 1 0 1 0 1 Entry L
Data field31 0
Longword data
24 1314
L : Longword specification bits: Reserved bits (0 write value, undefined read value)
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4.6 Store queuesTwo 32-byte store queues (SQs) are supported to perform high-speed writes toexternal memory. When not using the SQs, the low power dissipation power-downmodes, in which SQ functions are stopped, can be used. The queue address controlregisters (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.Refer to the product level documentation of clock and power management for thedetails on stopping SQ functions.
4.6.1 SQ configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in Figure 28. These twostore queues can be set independently.
Item Store queues
Capacity 2 * 32
Addresses 0xE000 0000 to 0xE3FF FFFF
Write Store instruction (1-cycle write)
Write-back Prefetch instruction
Access right MMU off: according to MMUCR.SQMD
MMU on: according to individual page PR
Table 29: Store queue features
Figure 28: Store queue configuration
SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7]
SQ1 SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7]
4B 4B 4B 4B 4B 4B 4B 4B
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4.6.2 SQ writes
A write to the SQs can be performed using a store instruction on P4 area 0xE0000000 to 0xE3FF FFFC. A longword or quadword access size can be used. Themeaning of the address bits is as follows:
4.6.3 SQ reads (implementation dependant)
A read from the SQs can be performed using a load instruction on P4 area 0xFF001000 to 0xFF00 103C. A longword access size must be used. The meaning of theaddress bits is as follows:
4.6.4 Transfer to external memory
Transfer from the SQs to external memory can be performed with the prefetchinstruction (PREF). Issuing a PREF instruction for 0xE000 0000 to 0xE3FF FFFCin the P4 region, starts a burst transfer from the SQs to external memory. The bursttransfer has a fixed length of 32 bytes, and the start address must be at a 32-byteboundary. While the contents of one SQ are being transferred to external memory,the other SQ can be written to, without incurring a penalty cycle. A write to the SQbeing transferred to external memory is suspended until the transfer to externalmemory is completed.
The SQ transfer destination external address bit [28:0] specification is as shownbelow, according to whether the MMU is on or off.
[31:26]: 111000 Store queue specification
[25:6]: Don’t care Used for external memory transfer/access right
[5]: 0/1 0: SQ0 specification 1: SQ1 specification
[4:2]: LW specification Specifies longword position in SQ0/SQ1
[1:0] 00 Fixed at 0
[31:6]: 0xFF00100 Store queue specification
[5]: 0/1 0: SQ0 specification 1: SQ1 specification
[4:2]: LW specification Specifies longword position in SQ0/SQ1
[1:0]: 00 Fixed at 0
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• When MMU is on
The SQ area (0xE000 0000 to 0xE3FF FFFF) is set in VPN of the UTLB, and thetransfer destination external address is set in PPN. The ASID, V, SZ, SH, PR,and D bits have the same meaning as for normal address translation, but the Cand WT bits have no meaning with regard to this page.
When a prefetch instruction is issued for the SQ area, address translation isperformed and external memory address bits [28:10] are generated inaccordance with the SZ bit specification. For external address bits [9:5], theaddress prior to address translation is generated in the same way as when theMMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs toexternal is performed to this address.
If SQ access is enabled by MMUCR.SQMD, in privileged mode only, an addresserror will be flagged in user mode, even if address translation is successful.
• When MMU is off
• The SQ area (0xE000 0000 to 0xE3FF FFFF) is specified as the address at whicha prefetch is performed. The meaning of address bits [31:0] is as follows:
External address bits [28:26], which cannot be generated from the above address,are generated from the QACR0/1 registers.
QACR0 [4:2]: External address bits [28:26] corresponding to SQ0
QACR1 [4:2]: External address bits [28:26] corresponding to SQ1
External address bits [4:0] are always fixed at 0 since burst transfer starts at a32-byte boundary.
[31:26]: 111000 Store queue specification
[25:6]: Address External memory address bits [25:6]
[5]: 0/1 0: SQ0 specification
1: SQ1 specification and external memory address bit [5]
[4:2]: Don’t care No meaning in a prefetch
[1:0] 00 Fixed at 0
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Determination of SQ access exception
Determination of an exception in a write to an SQ or transfer to external memory(PREF instruction) is performed as follows according to whether the MMU is on oroff. In the SH7751, if an exception occurs in as SQ Write, the SQ contents may becorrupted. In the SH7751R, if an exception occurs in as SQ Write, SQ write access iscancelled and the data before the SQ write access is kept. If an exception occurs intransfer from an SQ to external memory, the transfer to external memory will beaborted.
• When MMU is on
Operation is in accordance with the address translation information recorded inthe UTLB, and MMUCR.SQMD. Write type exception judgment is performed forwrites to the SQs, and read type for transfer from the SQs to external memory(PREF instruction), and a TLB miss exception, protection violation exception, orinitial page write exception is generated. However, if SQ access is enabled, inprivileged mode only, by MMUCR.SQMD, an address error will be flagged inuser mode even if address translation is successful.
• When MMU is off
Operation is in accordance with MMUCR.SQMD.
0: Privileged/user access possible
1: Privileged access possible
If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, anaddress error will be flagged.
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5Exceptions
5.1 OverviewThe process of responding to an extraordinary event such as a reset, a generalexception (trap) or an interrupt, is called exception handling.
Exception handling is performed by user supplied special routines, that areexecuted by the CPU when one of these extraordinary events is encountered.
5.2 Register descriptionsThere are three registers related to exception handling. These are allocated tomemory, and can be accessed by specifying the P4 address or Area 7 address.
Name Abbreviation R/W Initial valueaP4
addressbArea 7
addressBAccesssize
TRAPA exception register TRA R/W Undefined 0xFF00 0020 0x1F00 0020 32
Exception event register EXPEVT R/W 0x0000 0000/
0x0000 0020A0xFF00 0024 0x1F00 0024 32
Interrupt event register INTEVT R/W Undefined 0xFF00 0028 0x1F00 0028 32
Table 30: Exception-related registers
a. 0x0000 0000 is set in a power-on reset, and 0x0000 0020 in a manual reset.
b. This is the address when using the virtual/physical address space P4 area. Whenmaking an access from physical address space area 7 using the TLB, the upper 3 bitsof the address are ignored.
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5.2.1 Exception event register (EXPEVT)
The exception event register (EXPEVT) resides at P4 address 0xFF00 0024, andcontains a 12-bit exception code. The exception code set in EXPEVT is that for areset or general exception event. The exception code is set automatically byhardware when an exception occurs. EXPEVT can also be modified by software.
5.2.2 Interrupt event register (INTEVT)
The interrupt event register (INTEVT) resides at P4 address 0xFF00 0028, andcontains a 12-bit exception code. The exception code set in INTEVT is that for aninterrupt request. The exception code is set automatically by hardware when anexception occurs. INTEVT can also be modified by software.
EXPEVT
Field Bits Size Synopsis Type
Exceptioncode
[0,11] 12 Exception code RW
Operation Exception code set automatically by hardware when exceptionoccurs.
Power-on reset Undefined
RES [12,31] 20 Bits reserved RW
Power-on reset Undefined
Table 31: EXPEVT Register Description
INTEVT
Field Bits Size Synopsis Type
Exceptioncode
[0,11] 12 Exception code RW
Operation Exception code set automatically by hardware when exceptionoccurs.
Power-on reset Undefined
Table 32: INTEVT Register Description
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5.2.3 TRAPA exception register (TRA)
The TRAPA exception register (TRA) resides at P4 address 0xFF00 0020. TRA is setautomatically by hardware when a TRAPA instruction is executed. TRA can also bemodified by software.
RES [12,31] 20 Bits reserved RW
Power-on reset Undefined
INTEVT
Field Bits Size Synopsis Type
Table 32: INTEVT Register Description
TRA
Field Bits Size Synopsis Type
Imm [2,9] 8 8-bit immediate data for the TRAPA instruction. RW
Operation
Power-on reset Undefined
RES [0,1],[10,31]
24 Bits reserved RW
Power-on reset Undefined
Table 33: TRA
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5.3 Exception handling functions
5.3.1 Exception handling flow
In exception handling, the contents of the program counter (PC), status register(SR) and R15 are saved in the saved program counter (SPC), saved status register(SSR) and saved general register (SGR). The CPU starts execution of theappropriate exception handling routine according to the vector address. Anexception handling routine is a program the user writes to handle a specificexception. The exception handling routine is terminated and control returned to theoriginal program, by executing a return-from-exception instruction (RTE). Thisinstruction restores the PC and SR contents, and returns control to the normalprocessing routine at the point at which the exception occurred. The SGR contentsare not written back to R15 by an RTE instruction.
The basic processing flow is as follows. See section 2, Data Formats and Registers,for the meaning of the individual SR bits.
1 The PC, SR and R15 contents are saved in SPC, SSR and SGR.
2 The block bit (BL) in SR is set to 1.
3 The mode bit (MD) in SR is set to 1.
4 The register bank bit (RB) in SR is set to 1.
5 In a reset, the FPU disable bit (FD) in SR is cleared to 0.
6 The exception code is written to bits 11 to 0 of the exception event register(EXPEVT), or to bits 13 to 0 of the interrupt event register (INTEVT).
7 The CPU branches to the determined exception handling vector address, and theexception handling routine begins.
5.3.2 Exception handling vector addresses
The reset vector address is fixed at 0xA000 0000. Exception and interrupt vectoraddresses are determined by adding the offset for the specific event, to the vectorbase address, which is set by software in the vector base register (VBR). In the caseof the TLB miss exception, for example, the offset is 0x0000 0400, so if 0x9C08 0000is set in VBR, the exception handling vector address will be 0x9C08 0400. If afurther exception occurs at the exception handling vector address, a duplicateexception will result, and recovery will be difficult; therefore, fixed physicaladdresses (P1, P2) should be specified for vector addresses.
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5.4 Exception types and prioritiesTable 34 shows the types of exceptions, with their relative priorities, vectoraddresses, and exception/interrupt codes.
Exceptioncategory
Executionmode
ExceptionPriority
levelPriorityorder
Vectoraddress
OffsetException
code
Reset Abort type POWERON 1 1 0xA000 0000 - 0x000
MANRESET 1 2 0xA000 0000 - 0x020
HUDIRESET 1 1 0xA000 0000 - 0x000
ITLBMULTIHIT 1 3 0xA000 0000 - 0x140
OTLBMULTIHIT 1 4 0xA000 0000 - 0x140
Generalexception
Re-executiontype
UBRKBEFORE*1 2 0 (VBR/DBR) 0x100/- 0x1E0
IADDERR 2 1 (VBR) 0x100 0x0E0
ITLBMISS 2 2 (VBR) 0x400 0x040
EXECPROT 2 3 (VBR) 0x100 0x0A0
RESINST 2 4 (VBR) 0x100 0x180
ILLSLOT 2 4 (VBR) 0x100 0x1A0
FPUDIS 2 4 (VBR) 0x100 0x800
SLOTFPUDIS 2 4 (VBR) 0x100 0x820
RADDERR 2 5 (VBR) 0x100 0x0E0
WADDERR 2 5 (VBR) 0x100 0x100
RTLBMISS 2 6 (VBR) 0x400 0x040
WTLBMISS 2 6 (VBR) 0x400 0x060
READPROT 2 7 (VBR) 0x100 0x0A0
WRITEPROT 2 7 (VBR) 0x100 0x0C0
FPUEXC 2 8 (VBR) 0x100 0x120
FIRSTWRITE 2 9 (VBR) 0x100 0x080
Table 34: Exceptions
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Priority: Priority is first assigned by priority level, then by priority order withineach level (the lowest number represents the highest priority).
Exception transition destination: Control passes to 0xA000 0000 in a reset, andto [VBR + offset] in other cases.
Exception code: Stored in EXPEVT for a reset or general exception, and inINTEVT for an interrupt.
IRL: Interrupt request level (pins IRL3ñIRL0).
Module/source: See the sections on the relevant peripheral modules.
Note: When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + 0x100.
5.5 Exception flow
5.5.1 Exception flow
Figure 29 shows an outline flowchart of the basic operations in instruction executionand exception handling. For the sake of clarity, the following description assumesthat instructions are executed sequentially, one by one. Register settings in the
Completiontype
TRAP 2 4 (VBR) 0x100 0x160
UBRKAFTER*A 2 10 (VBR/DBR) 0x100/- 0x1E0
Interrupt Completiontype
NMIb 3 - (VBR) 0x600 0x1C0
IRLINTb 4 a (VBR) 0x600 See thesystem
manualbPERIPHINTb 4 A (VBR) 0x600
a. The priority order of external interrupts and peripheral module interrupts can be set bysoftware.
b. The set of peripheral interrupts is system-dependent. See the Interrupt chapter in theSystem Architecture Manual for the list of peripheral interrupts and their correspondingINTEVT codes.
Exceptioncategory
Executionmode
ExceptionPriority
levelPriorityorder
Vectoraddress
OffsetException
code
Table 34: Exceptions
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event of an exception are shown only for SSR, SPC, EXPEVT/INTEVT, SR, and PC,but other registers may be set automatically by hardware, depending on theexception. For details, see section 5.6, Description of Exceptions. Also, seeSection 5.6.4, for exception handling during execution of a delayed branchinstruction and a delay slot instruction, and in the case of instructions in which twodata accesses are performed.
Figure 29: Instruction execution and exception handling
Execute next instruction
Is highest- priority exception
re-exceptiontype?
Cancel instruction executionresult
Yes
Yes
Yes
No
No
No
No
Yes
SSR ← SRSPC ← PCSGR ← R15EXPEVT/INTEVT ← exception codeSR.{MD,RB,BL} ← 111PC ← (BRCR.UBDE=1 && User_Break?
DBR: (VBR + Offset))
EXPEVT ← exception codeSR. {MD, RB, BL, FD, IMASK} ← 11101111PC ← H'A000 0000
Interruptrequested?
Generalexception requested?
Resetrequested?
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5.5.2 Exception source acceptance
A priority ranking is provided for all exceptions, for use in determining which of twoor more simultaneously generated exceptions should be accepted. Five of thegeneral exceptions:
• general illegal instruction exception
• slot illegal instruction exception
• general FPU disable exception
• slot FPU disable exception
• unconditional trap exception
are detected in the process of instruction decoding, and do not occur simultaneouslyin the instruction pipeline. Therefore, these exceptions all have the same priority.General exceptions are detected in the order of instruction execution. However,exception handling is performed in the order of instruction flow (program order).Thus, an exception for an earlier instruction is accepted before that for a laterinstruction. An example of the order of acceptance for general exceptions is shown inFigure 30.
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Figure 30: Example of general exception acceptance order
IF
IF
ID
ID
EX
EX
MA
MA
WB
WB
TLB miss (data access)Pipeline flow:
Order of detection:
Instruction nInstruction n+1
General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously
Order of exception handling:
TLB miss (instruction n)
Program order
1
Instruction n+2
General illegal instruction exception
IF ID EX MA WB
IF ID EX MA WB
TLB miss (instruction access)
2
3
4
IF: Instruction fetchID: Instruction decodeEX: Instruction executionMA: Memory accessWB: Write-back
Instruction n+3
TLB miss (instruction n)
Re-execution of instruction n
General illegal instruction exception (instruction n+1)
Re-execution of instruction n+1
TLB miss (instruction n+2)
Re-execution of instruction n+2
Execution of instruction n+3
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5.5.3 Exception requests and BL bit
When the BL bit in SR is 0, exceptions and interrupts are accepted.
When the BL bit in SR is 1 and an exception other than a user break is generated,the CPUs internal registers are set to their post-reset state, the registers of theother modules retain their contents prior to the exception, and the CPU branches tothe same address as in a reset (0xA000 0000). For the operation in the event of auser break, see section 20: User Break Controller. If an ordinary interrupt occurs,the interrupt request is held pending, and is accepted after the BL bit has beencleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be heldpending or accepted, according to the setting made by software.
Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, toenable multiple exception state acceptance.
5.5.4 Return from exception handling
The RTE instruction is used to return from exception handling. When the RTEinstruction is executed, the SPC contents are restored to PC, and the SSR contentsto SR. The CPU returns from the exception handling routine by branching to theSPC address. If SPC and SSR were saved to external memory, set the BL bit in SRto 1 before restoring the SPC and SSR contents and issuing the RTE instruction.
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5.6 Description of exceptionsThe various exception handling operations are described here, covering exceptionsources, transition addresses, and processor operation, when a transition is made.
5.6.1 Resets
1 POWERON - Power-On Reset
- Sources:For details of how the core is driven to the power on reset state, refer to theSystem Architecture Manual of the appropriate product.
- Transition address: 0xA000 0000
- Transition operations:Exception code 0x000 is set in EXPEVT, initialization of VBR and SR isperformed, and a branch is made to PC = 0xA000 0000. In the initializationprocessing, the VBR register is set to 0x0000 0000, and in SR, the MD, RB,and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits(I3-I0) are set to 0xF.
CPU initialization is performed. For details of the impact on the rest of thesystem refer to the System Architecture Manual.
Refer to Appendix A for power-on reset values for the various CPU coremodules set by the Initialize_Module function.
POWERON(){
Initialize_Module(PowerOn);EXPEVT = 0x00000000;VBR = 0x00000000;SR.MD = 1;SR.RB = 1;SR.BL = 1;SR.(I0-I3) = 0xF;SR.FD=0;PC = 0xA0000000;
}
MANRESET - Manual Reset
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- Sources:When a general exception other than a user break occurs while the BL bit isset to 1 in SR. It is also possible for the system in which the core is integratedto drive the processor in to this reset state. For details refer to the SystemArchitecture Manual of the appropriate product.
- Transition address: 0xA000 0000
- Transition operations:
Exception code 0x020 is set in EXPEVT, initialization of VBR and SR isperformed, and a branch is made to PC = 0xA000 0000. In the initializationprocessing, the VBR register is set to 0x0000 0000, and in SR, the MD, RB,and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits(I3-I0) are set to 0xF. CPU and system initialization are performed. Fordetails refer to the System Architecture Manual.
Refer to Appendix A for the manual reset values for the various CPU coremodules set by the Initialize_Module function.
MANRESET(){
Initialize_Module(Manual);EXPEVT = 0x00000020;VBR = 0x00000000;SR.MD = 1;SR.RB = 1;SR.BL = 1;SR.(I0-I3) = 0xF;SR.FD = 0;PC = 0xA0000000;
}
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2 HUDIRESET - H-UDI Reset
- Source:Refer to the System Architecture Manual for a description of how the core isplaced in the H-UDI reset state.
- Transition address: 0xA000 0000
Transition operations:
Exception code 0x000 is set in EXPEVT, initialization of VBR and SR isperformed, and a branch is made to PC = 0xA000 0000. In the initializationprocessing, the VBR register is set to 0x0000 0000, and in SR, the MD, RB,and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits(I3-I0) are set to 0xF. CPU and system initialization are performed, for detailsrefer to the System Architecture Manual.
Refer to Appendix A for the manual reset values for the various CPU coremodules set by the Initialize_Module function.
HUIDRESET(){
Initialize_Module(PowerOn);EXPEVT = 0x00000000;VBR = 0x00000000;SR.MD = 1;SR.RB = 1;SR.BL = 1;SR.(I0-I3) = 0xF;SR.FD = 0;PC = 0xA0000000;
}
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3 ITLBMULTIHIT - Instruction TLB Multiple-Hit Exception
- Source: Multiple ITLB address matches
- Transition address: 0xA000 0000
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
Exception code 0x140 is set in EXPEVT, initialization of VBR and SR isperformed, and a branch is made to PC = 0xA000 0000.
In the initialization processing, the VBR register is set to 0x0000 0000, and inSR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and theinterrupt mask bits (I3-I0) are set to 0xF.
CPU and system initialization are performed in the same way as in a manualreset.
Refer to Appendix A for the manual reset values for the various CPU coremodules set by the Initialize_Module function.
ITLBMULTIHIT(){
Initialize_Module(Manual);TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;EXPEVT = 0x00000140;VBR = 0x00000000;SR.MD = 1;SR.RB = 1;SR.BL = 1;SR.(I0-I3) = 0xF;SR.FD = 0;PC = 0xA0000000;
}
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4 OTLBMULTIHIT - Operand TLB Multiple-Hit Exception
- Source: Multiple UTLB address matches
- Transition address: 0xA000 0000
Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
Exception code 0x140 is set in EXPEVT, initialization of VBR and SR isperformed, and a branch is made to PC = 0xA000 0000.
In the initialization processing, the VBR register is set to 0x0000 0000, and inSR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and theinterrupt mask bits (I3-I0) are set to 0xF.
CPU and system initialization are performed in the same way as in a manualreset.
Refer to Appendix A for the manual reset values for the various CPU coremodules set by the Initialize_Module function.
OTLBMULTIHIT(){
Initialize_Module(Manual);TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;EXPEVT = 0x00000140;VBR = 0x00000000;SR.MD = 1;SR.RB = 1;SR.BL = 1;SR.(I0-I3) = 0xF;SR.FD = 0;PC = 0xA0000000;
}
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5.6.2 General exceptions
1 RTLBMISS - Read Data TLB Miss Exception
- Source: Address mismatch in UTLB address comparison
- Transition address: VBR + 0x0000 0400
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents are saved in SGR.
Exception code 0x040 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0400.
To speed up TLB miss processing, the offset is separate from that of otherexceptions.
RTLBMISS(){
TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000040;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000400;
}
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2 WTLBMISS - Write Data TLB Miss Exception
- Source: Address mismatch in UTLB address comparison
- Transition address: VBR + 0x0000 0400
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x060 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0400.
To speed up TLB miss processing, the offset is separate from that of otherexceptions.
WTLBMISS(){
TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000060;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000400;
}
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3 ITLBMISS - Instruction TLB Miss Exception
- Source: Address mismatch in ITLB address comparison
- Transition address: VBR + 0x0000 0400
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x040 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0400.
To speed up TLB miss processing, the offset is separate from that of otherexceptions.
ITLBMISS(){
TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000040;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000400;
}
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4 FIRSTWRITE - Initial Page Write Exception
- Source: TLB is hit in a store access, but dirty bit D = 0
- Transition address: VBR + 0x0000 0100
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x080 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
FIRSTWRITE(){
TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000080;SR.MD = 1; SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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5 READPROT - Data TLB Protection Violation Exception
- Source: The access does not agree with the UTLB protection information (PRbits) shown below.
- Transition address: VBR + 0x0000 0100
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
READPROT(){
TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x000000A0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
PR Privileged mode User mode
00 Only read access possible Access not possible
01 Read/write access possible Access not possible
10 Only read access possible Only read access possible
11 Read/write access possible Read/write access possible
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6 WRITEPROT - Write Data TLB Protection Violation Exception
- Source: The access does not agree with the UTLB protection information (PRbits) shown below.
- Transition address: VBR + 0x0000 0100
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x0C0 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
WRITEPROT(){
TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x000000C0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
PR Privileged mode User mode
00 Only read access possible Access not possible
01 Read/write access possible Access not possible
10 Only read access possible Only read access possible
11 Read/write access possible Read/write access possible
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7 EXECPROT - Instruction TLB Protection Violation Exception
- Source: The access does not agree with the ITLB protection information (PRbits) shown below.
- Transition address: VBR + 0x0000 0100
- Transition operations: The virtual address (32 bits) at which this exceptionoccurred is set in TEA, and the corresponding virtual page number (22 bits) isset in PTEH [31:10]. ASID in PTEH indicates the ASID when this exceptionoccurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
EXECPROT(){
TEA = EXCEPTION_ADDRESS;PTEH.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x000000A0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
PR Privileged mode User mode
0 Access possible Access not possible
1 Access possible Access possible
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8 RADDERR - Read Data Address Error
- Sources:
Word data access from other than a word boundary (2n +1)
Longword data access from other than a longword data boundary (4n +1, 4n +2, or 4n +3)
Quadword data access from other than a quadword data boundary (8n +1, 8n+ 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7)
Access to area 0x8000 00000xFFFF FFFF in user mode
- Transition address: VBR + 0x0000 0100
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100. For details, seeChapter 3: Memory management unit (MMU) on page 41.
RADDERR(){
TEA = EXCEPTION_ADDRESS;PTEN.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x000000E0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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9 WADDERR - Write Data Address Error
- Sources:
Word data access from other than a word boundary (2n +1)
Longword data access from other than a longword data boundary (4n +1, 4n +2, or 4n +3)
Quadword data access from other than a quadword data boundary (8n +1, 8n+ 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7)
Access to area 0x8000 00000 - 0xFFFF FFFF in user mode (except for thestore queue area 0xE000 0000 - 0xE3FF FFFF)
- Transition address: VBR + 0x0000 0100
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x100 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100. For details, seeChapter 3: Memory management unit (MMU) on page 41.
WADDERR({
TEA = EXCEPTION_ADDRESS;PTEN.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000100;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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10 IADDERR - Instruction Address Error
- Sources:
Instruction fetch from other than a word boundary (2n +1)
Instruction fetch from area 0x8000 00000 - 0xFFFF FFFF in user mode
- Transition address: VBR + 0x0000 0100
- Transition operations:The virtual address (32 bits) at which this exception occurred is set in TEA,and the corresponding virtual page number (22 bits) is set in PTEH [31:10].ASID in PTEH indicates the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurredare saved in the SPC and SSR. The R15 contents at this time are saved inSGR.
Exception code 0x0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100. For details, seeChapter 3: Memory management unit (MMU) on page 41.
IADDERR(){
TEA = EXCEPTION_ADDRESS;PTEN.VPN = PAGE_NUMBER;SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x000000E0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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11 TRAP - Unconditional trap
- Source: Execution of TRAPA instruction
- Transition address: VBR + 0x0000 0100
- Transition operations:As this is a processing-completion-type exception, the PC contents for theinstruction following the TRAPA instruction are saved in SPC. The value ofSR and R15 when the TRAPA instruction is executed are saved in SSR andSGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4,and the result is set in TRA [9]. Exception code 0x160 is set in EXPEVT. TheBL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR +0x0100.
TRAP(){
SPC = PC + 2;SSR = SR;SGR = R15;TRA = imm << 2; EXPEVT = 0x00000160;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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12 RESINST - General Illegal Instruction Exception
- Sources:
Decoding of an undefined instruction other than in a branch delay slot.
The opcode 0xFFFD is guaranteed to be defined in any SH-4 architecturerevision. Other unused opcodes may be treated as reserved in any particularSH-4 implementation.
Decoding in user mode of a privileged instruction not in a delay slot
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR
- Transition address: VBR + 0x0000 0100
- Transition operations:The PC contents for the instruction at which this exception occurred aresaved in SPC. The SR and R15 contents when this exception occurred aresaved in SSR and SGR.
Exception code 0x180 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
Note: The only undefined opcode which the architecture guarantees to cause a GeneralIllegal Instruction Exception is 0xFFFD.
RESINST(){
SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000180;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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13 ILLSLOT - Slot Illegal Instruction Exception
- Sources:
Decoding of an undefined instruction in a delay slot
The branches with delay slots are JMP, JSR, BRA, BRAF, BSR, BSRF, RTS,RTE, BT/S and BF/S. The opcode 0xFFFD is guaranteed to be undefined inany SH-4 architecture revision. Other unused opcodes may be treated asreserved in any particular SH-4 implementation.
Decoding of an instruction that modifies PC in a delay slot
Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE,BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
Decoding in user mode of a privileged instruction in a delay slot
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR
Decoding of a PC-relative MOV instruction or MOVA instruction in a delayslot ·
Transition address: VBR + 0x0000 0100
Transition operations:The PC contents for the preceding delayed branch instruction are saved inSPC. The SR contents when this exception occurred are saved in SSR. TheR15 contents at this time are saved in SGR.
Exception code 0x1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
Note: The only undefined opcode which the architecture guarantees to cause a Slot IllegalInstruction Exception is 0xFFFD.
ILLSLOT(){
SPC = PC - 2;SSR = SR;SGR = R15;EXPEVT = 0x000001A0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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14 FPUDIS - General FPU Disable Exception
- Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1
- Transition address: VBR + 0x0000 0100
Transition operations:The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code 0x800 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
Note: FPU instructions are instructions in which the first 4 bits of the instruction code areF (but excluding undefined instruction 0xFFFD), and the LDS, STS, LDS.L, andSTS.L instructions corresponding to FPUL and FPSCR.
FPUDIS(){
SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000800;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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15 SLOTFPUDIS - Slot FPU Disable Exception
- Source: Decoding of an FPU instruction in a delay slot with SR.FD =1
- Transition address: VBR + 0x0000 0100
- Transition operations:The PC contents for the preceding delayed branch instruction are saved inSPC. The SR and R15 contents when this exception occurred are saved inSSR and SGR.
Exception code 0x820 is set in EXPEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0100.
SLOTFPUDIS(){
SPC = PC - 2;SSR = SR;SGR = R15;EXPEVT = 0x00000820;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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16 UBRKBEFORE - User Breakpoint Pre-execution Trap
- Source: Fulfilling of a break condition set in the user break controller
- Transition address: VBR + 0x0000 0100, or DBR
- Transition operations:
The PC contents for the instruction at which the breakpoint is set are set inSPC. The SR and R15 contents when the break occurred are saved in SSRand SGR. Exception code 0x1E0 is set in EXPEVT.
The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC =VBR + 0x0100. It is also possible to branch to PC = DBR. For details of PC,etc., when a data break is set, see User Break Controller (UBC) Chapter in theST40 System Architecture Manual.
UBRKBEFORE(){
SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x000001E0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = (BRCR.UBDE==1 ? DBR : VBR + H00000100);
}
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17 UBRKAFTER - User Breakpoint Post-Execution Trap
- Source: Fulfilling of a break condition set in the user break controller
- Transition address: VBR + 0x0000 0100, or DBR
- Transition operations:
The PC of the instruction following that at which the breakpoint is set isplaced in SPC. The SR and R15 contents when the break occurred are savedin SSR and SGR. Exception code 0x1E0 is set in EXPEVT.
The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC =VBR + 0x0100. It is also possible to branch to PC = DBR. For details of PC,etc., when a data break is set, see User Break Controller (UBC) Chapter in theST40 System Architecture Manual.
UBRKAFTER(){
SPC = PC + 2;SSR = SR;SGR = R15;EXPEVT = 0x000001E0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = (BRCR.UBDE==1 ? DBR : VBR + H00000100);
}
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18 FPUEXC - FPU Exception
- Source: Exception due to execution of a floating-point operation
- Transition address: VBR + 0x0000 0100
- Transition operations:
The PC and SR contents for the instruction at which this exception occurredare saved in SPC and SSR. Exception code 0x120 is set in EXPEVT. The BL,MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR +0x0100. The contents of R15 are saved to SGR.
FPUEXC(){
SPC = PC;SSR = SR;SGR = R15;EXPEVT = 0x00000120;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000100;
}
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5.6.3 Interrupts
1 NMI - Non-Maskable Interrupt
- Source: Refer to relevant System Architecture Manual for details ofnon-maskable interrupt generation (NMI).
- Transition address: VBR + 0x0000 0600
Transition operations:
The PC and SR contents for the instruction at which this exception isaccepted are saved in SPC and SSR. The R15 contents at this time are savedin SGR.
Exception code 0x1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1in SR, and a branch is made to PC = VBR + 0x0600.
When the BL bit in SR is 0, this interrupt is not masked by the interruptmask bits in SR, and is accepted at the highest priority level. When the BL bitin SR is 1, a software setting can specify whether this interrupt is to bemasked or accepted. For details refer to the description of interruptprogramming in the appropriate System Architecture Manual.
NMI(){
SPC = PC;SSR = SR;SGR = R15;INTEVT = 0x000001C0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000600;
}
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2 IRLINT - IRL Interrupts
- Source: The interrupt mask bit setting in SR is smaller than the IRL (3-0)level, and the BL bit in SR is 0 (accepted at instruction boundary).
- Transition address: VBR + 0x0000 0600
- Transition operations:
The PC contents immediately after the instruction at which the interrupt isaccepted are set in SPC. The SR and R15 contents at the time of acceptanceare set in SSR and SGR.
The code corresponding to the IRL (3-0) level is set in INTEVT. For furtherdetails of the interrupt handling behavior, refer to the product leveldocumentation of the interrupt controller. The BL, MD, and RB bits are set to1 in SR, and a branch is made to VBR + 0x0600. The acceptance level is notset in the interrupt mask bits in SR. When the BL bit in SR is 1, the interruptis masked. For further details of the interrupt handling behavior, refer to theproduct level documentation of the interrupt controller.
IRLINT(){
SPC = PC;SSR = SR;SGR = R15;INTEVT = 0x00000200 ~ 0x000003C0;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000600;
}
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3 PERIPHINT - Peripheral Module Interrupts
- Source: The interrupt mask bit setting in SR is smaller than the peripheralmodule (Hitachi-UDI for example) interrupt level, and the BL bit in SR is 0(accepted at instruction boundary).
- Transition address: VBR + 0x0000 0600
- Transition operations:The PC contents immediately after the instruction at which the interrupt isaccepted are set in SPC. The SR and R15 contents at the time of acceptanceare set in SSR and SGR.
The code corresponding to the interrupt source is set in INTEVT. The BL,MD, and RB bits are set to 1 in SR, and a branch is made to VBR + 0x0600.The module interrupt levels should be set as values between 0x0 and 0xF inthe interrupt priority registers (IPRA-IPRC) in the interrupt controller. Forfurther details of the interrupt handling behavior, refer to the product leveldocumentation of the interrupt controller.
Module_interruption(){
SPC = PC;SSR = SR;SGR = R15;INTEVT = 0x00000400 ~ 0x00000B80;SR.MD = 1;SR.RB = 1;SR.BL = 1;PC = VBR + 0x00000600;
}
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5.6.4 Priority order with multiple exceptions
With some instructions, such as instructions that make two accesses to memory,and the indivisible pair comprising a delayed branch instruction and delay slotinstruction, multiple exceptions occur. Care is required in these cases, as theexception priority order differs from the normal order.
1 Instructions that make two accesses to memory.With MAC instructions, memory-to-memory arithmetic/logic instructions, andTAS instructions, two data transfers are performed by a single instruction, andan exception will be detected for each of these data transfers. In these cases,therefore, the following order is used to determine priority.
1.1 Data address error in first data transfer.
1.2 TLB miss in first data transfer.
1.3 TLB protection violation in first data transfer.
1.4 Data address error in second data transfer.
1.5 TLB miss in second data transfer.
1.6 TLB protection violation in second data transfer.
1.7 Initial page write exception in second data transfer.
2 Indivisible delayed branch instruction and delay slot instruction.As a delayed branch instruction and its associated delay slot instruction areindivisible, they are treated as a single instruction. Consequently, the priorityorder for exceptions that occur in these instructions differs from the usualpriority order. The priority order shown below is for the case where the delay slotinstruction has only one data transfer.
2.1 The delayed branch instruction is checked for priority levels 1 and 2.
2.2 The delay slot instruction is checked for priority levels 1 and 2.
2.3 A check is performed for priority level 3 in the delayed branch instruction andpriority level 3 in the delay slot instruction. (There is no priority rankingbetween these two.)
2.4 A check is performed for priority level 4 in the delayed branch instruction andpriority level 4 in the delay slot instruction. (There is no priority rankingbetween these two.)
If the delay slot instruction has a second data transfer, two checks areperformed in step b, as in 1 above.
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If the accepted exception (the highest-priority exception) is a delay slotinstruction re-execution type exception, the branch instruction PR registerwrite operation (PC PR operation performed in BSR, BSRF, JSR) is inhibited.
5.7 Usage notes1 Return from exception handling
1.1 Check the BL bit in SR with software.If SPC and SSR have been saved to external memory, set the BL bit in SR to1 before restoring them.
1.2 Issue an RTE instruction.When RTE is executed, the SPC contents are set in PC, the SSR contents areset in SR, and branch is made to the SPC address to return from theexception handling routine.
2 If an exception or interrupt occurs when SR.BL = 1
2.1 ExceptionWhen an exception other than a user break occurs, the CPUs internalregisters are set to their post-reset state, the registers of the other modulesretain their contents prior to the exception, and the CPU branches to thesame address as in a reset (0xA000 0000). The value in EXPEVT at this timeis 0x0000 0020. The value of the SPC and SSR registers is undefined.
2.2 InterruptIf an ordinary interrupt occurs, the interrupt request is held pending and isaccepted after the BL bit in SR has been cleared to 0 by software. If anonmaskable interrupt (NMI) occurs, it can be held pending or acceptedaccording to the setting made by software. In the sleep or standby state, aninterrupt is accepted even if the BL bit in SR is set to 1.
3 SPC when an exception occurs
3.1 Re-execution type exceptionThe PC value for the instruction in which the exception occurred is set inSPC, and the instruction is re-executed after returning from exceptionhandling. If an exception occurs in a delay slot instruction, the PC value forthe delay slot instruction is saved in SPC, regardless of whether or not thepreceding delay slot instruction condition is satisfied.
3.2 Completion type exception or interruptThe PC value for the instruction following that in which the exception
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occurred is set in SPC. If an exception occurs in a branch instruction withdelay slot, the PC value for the branch destination is saved in SPC.
4 An exception must not be generated in an RTE instruction delay slot, as theoperation will be undefined in this case.
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6Floating-pointunit6.1 Overview
The floating-point unit (FPU) has the following features:
• Conforms to IEEE754 standard
• 32 single-precision floating-point registers (can also be referenced as 16double-precision registers)
• Two rounding modes: Round to Nearest and Round to Zero
• Two denormalization modes: Flush to Zero and Treat Denormalized Number
• Six exception sources: FPU Error, Invalid Operation, Divide By Zero, Overflow,Underflow, and Inexact
• Comprehensive instructions: Single-precision, double-precision, graphicssupport, system control
When the FD bit in SR is set to 1, the FPU cannot be used, and an attempt toexecute an FPU instruction will cause an FPU disable exception.
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6.2 Floating-point formatAn IEEE754 floating-point number contains three fields: a sign (s), an exponent (e)and a fraction (f) in the format given in Figure 31.
The sign, s, is the sign of the represented number. If s is 0, the number is positive. Ifs is 1, the number is negative.
The exponent, e, is held as a biased value. The relationship between the biasedexponent, e, and the unbiased exponent, E, is given by e = E+bias, where bias is afixed positive number. The unbiased exponent, E, takes any value in the range[Emin-1, Emax+1]. The minimum and maximum values in that range, Emin-1 andEmax+1, designate special values such as positive zero, negative zero, positiveinfinity, negative infinity, denormalized numbers and “Not a Number” (NaN).
The fraction, f, specifies the binary digits that lie to the right of the binary point. Anormalized floating-point number has a leading bit of 1 which lies to the left of thebinary point. A denormalized floating-point number has a leading bit of 0 which liesto the left of the binary point. The leading bit is implicitly represented; it isdetermined by whether the number is normalized or denormalized, and is notexplicitly encoded. The implicit leading bit and the explicit fraction bits togetherform the significance of the floating-point number.
Floating-point number value v is determined as follows:
The value, v, of a floating-point number is determined as follows:
NaN: if E = Emax + 1 and f ≠ 0, then v is Not a Number irrespective of the sign s
Positive or negative infinity: if E = Emax + 1 and f = 0, then v = (-1)s (∞)
Normalized number: if Emin ≤ E ≤ Emax, then v = (-1)s 2E(1.f)
Denormalized number: if E = Emin - 1 and f ≠ 0, then v = (-1)s 2Emin(0.f)
Positive or negative zero: if E = Emin - 1 and f = 0, then v = (-1)s 0
Figure 31: IEEE754 floating-point representations
s e f
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The architecture supports two IEEE754 basic floating-point number formats:single-precision and double-precision.
Table 36 shows the ranges of the various numbers in hexadecimal notation.
Parameter Single-precision Double-precision
Total bit width 32 bits 64 bits
Sign bit 1 bit 1 bit
Exponent field 8 bits 11 bits
Fraction field 23 bits 52 bits
Precision 24 bits 53 bits
Bias +127 +1023
Emax +127 +1023
Emin -126 -1022
Table 35: Floating-point number formats and parameters
Type Single-precision Double-precision
sNaN (Signalingnot-a-number)
0x7FFFFFFF to 0x7FC00000
and
0xFFC00000 to0xFFFFFFFF
0x7FFFFFFF 0xFFFFFFFF to0x7FF80000 0x00000000and0xFFF80000 0x00000000 to0xFFFFFFFF 0xFFFFFFFF
qNaN (Quietnot-a-number)
0x7FBFFFFF to 0x7F800001
and
0xFF800001 to 0xFFBFFFFF
0x7FF7FFFF 0xFFFFFFFF to0x7FF00000 0x00000001and0xFFF00000 0x00000001 to0xFFF7FFFF 0xFFFFFFFF
+INF (Positive infinity) 0x7F800000 0x7FF00000 0x00000
+NORM (Positivenormalized number)
0x7F7FFFFF to 0x00800000 0x7FEFFFFF 0xFFFFFFFF to0x00100000 0x00000000
Table 36: Floating-point ranges
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6.2.1 Non-numbers (NaN)
Figure 32 shows the bit pattern of a non-number (NaN).
A floating-point number is a NaN if the exponent field contains the maximumrepresentable value and the fraction is non-zero, regardless of the value of the sign.In the figure above, x can have a value of 0 or 1. If the most significant bit of thefraction (N, in the figure above) is 1, the value is a signaling NaN (sNaN), otherwisethe value is a quiet NaN (qNaN).
An sNAN is input in an operation, except copy, FABS, and FNEG, that generates afloating-point value.
+DENORM (Positivedenormalized number)
0x007FFFFF to 0x00000001 0x000FFFFF 0xFFFFFFFF to0x00000000 0x00000001
+0.0 (Positive zero) 0x00000000 0x00000000 0x00000000
- 0.0 (Negative zero) 0x80000000 0x80000000 0x00000000
-DENORM (Negativedenormalized number)
0x80000001 to 0x807FFFFF 0x80000000 0x00000001 to0x800FFFFF 0xFFFFFFFF
-NORM (Negativenormalized number)
0x80800000 to 0xFF7FFFFF 0x80100000 0x00000000 to0xFFEFFFFF 0xFFFFFFFF
-INF (Negative infinity) 0xFF800000 0xFFF00000 0x00000000
Type Single-precision Double-precision
Table 36: Floating-point ranges
Figure 32: Single-precision NaN bit pattern
31
x 11111111 Nxxxxxxxxxxxxxxxxxxxxxx
30 23 22 0
N = 1: sNaNN = 0: qNaN
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• When the EN.V bit in the FPSCR register is 0, the operation result (output) is aqNaN.
• When the EN.V bit in the FPSCR register is 1, an invalid operation exceptionwill be generated. In this case, the contents of the operation destination registerare unchanged.
If a qNaN is input in an operation that generates a floating-point value, and ansNaN has not been input in that operation, the output will always be a qNaNirrespective of the setting of the EN.V bit in the FPSCR register. An exception willnot be generated in this case.
See the individual instruction descriptions for details of floating-point operationswhen a non-number (NaN) is input.
6.2.2 Denormalized numbers
For a denormalized number floating-point value, the exponent field is expressed as0, and the fraction field as a non-zero value.
When the DN bit in the FPU’s status register FPSCR is 1, a denormalized number(source operand or operation result) is always flushed to 0 in a floating-pointoperation that generates a value (an operation other than copy, FNEG, or FABS).
When the DN bit in FPSCR is 0, a denormalized number (source operand oroperation result) is processed as it is. See the individual instruction descriptions fordetails of floating-point operations when a denormalized number is input.
6.3 RoundingIn a floating-point instruction, rounding is performed when generating the finaloperation result from the intermediate result. Therefore, the result of combinationinstructions such as FMAC, FTRV, and FIPR will differ from the result when usinga basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once inFMAC, but twice in FADD, FSUB, and FMUL.
There are two rounding methods, the method to be used being determined by theRM field in FPSCR.
• RM = 00: Round to Nearest
• RM = 01: Round to Zero
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Round to Nearest:The value is rounded to the nearest expressible value. If there are two nearestexpressible values, the one with an LSB of 0 is selected.
If the unrounded value is 2Emax (2-2-P) or more, the result will be infinity with thesame sign as the unrounded value. The values of Emax and P, respectively, are 127and 24 for single-precision, and 1023 and 53 for double-precision.
Round to Zero:The digits below the round bit of the unrounded value are discarded.
If the unrounded value is larger than the maximum expressible absolute value, thevalue will be the maximum expressible absolute value.
6.4 Floating-point exceptionsFPU-related exceptions are as follows:
• General illegal instruction/slot illegal instruction exception
The exception occurs if an FPU instruction is executed when SR.FD = 1.
• FPU exceptions
The exception sources are as follows:
- FPU error (E): When FPSCR.DN = 0 and a denormalized number is input
- Invalid operation (V): In case of an invalid operation, such as NaN input
- Division by zero (Z): Division with a zero divisor
- Overflow (O): When the operation result overflows
- Underflow (U): When the operation result underflows
- Inexact exception (I): When overflow, underflow, or rounding occurs
The FPSCR cause field contains bits corresponding to all of above sources E, V,Z, O, U, and I, and the FPSCR flag and enable fields contain bits correspondingto sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled.
When an exception source occurs, the corresponding bit in the cause field is setto 1, and 1 is added to the corresponding bit in the flag field. When an exceptionsource does not occur, the corresponding bit in the cause field is cleared to 0, butthe corresponding bit in the flag field remains unchanged.
• Enable/disable exception handling
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The SH-4 CPU core supports enable exception handling and disable exceptionhandling.
Enable exception handling is initiated in the following cases:
- FPU error (E): FPSCR.DN = 0 and a denormalized number is input
- Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalidoperation)
- Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor
- Overflow (O): FPSCR.EN.O = 1 and instruction with any possibility of theoperation result overflowing
- Underflow (U): FPSCR.EN.U = 1 and instruction with any possibility of theoperation result underflowing
- Inexact exception (I): FPSCR.EN.I = 1 and instruction with any possibility ofan inexact operation result
These possibilities are shown in the individual instruction descriptions. Allexception events that originate in the FPU are assigned as the sameexception event. The meaning of an exception is determined by software byreading system register FPSCR and interpreting the information it contains.If no bits are set in the cause field of FPSCR when one or more of bits O, U, I,and V (in case of FTRV only) are set in the enable field, this indicates that anactual exception source is not generated. Also, the destination register is notchanged by any enable exception handling operation.
Except for the above, the FPU disables exception handling. In all processing,the bit corresponding to source V, Z, O, U, or I is set to 1, and disableexception handling is provided for each exception.
- Invalid operation (V): qNAN is generated as the result.
- Division by zero (Z): Infinity with the same sign as the unrounded value isgenerated.
- Overflow (O):
When rounding mode = RZ, the maximum normalized number, with the samesign as the unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unroundedvalue is generated.
- Underflow (U):
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When FPSCR.DN = 0, a denormalized number with the same sign as theunrounded value, or zero with the same sign as the unrounded value, isgenerated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, isgenerated.
- Inexact exception (I): An inexact result is generated.
6.5 Graphics support functionsThe SH-4 CPU core supports two kinds of graphics functions: new instructions forgeometric operations, and pair single-precision transfer instructions that enablehigh-speed data transfer.
6.5.1 Geometric operation instructions
Geometric operation instructions perform approximate-value computations. Toenable high-speed computation with a minimum of hardware, the SH-4 CPU coreignores comparatively small values in the partial computation results of fourmultiplications. Consequently, the error shown below is produced in the result of thecomputation:
Maximum error = MAX (individual multiplication result x 2-MIN (number of multipliersignificant digits1, number of multiplicand significant digits1)) + MAX (result value x 2-23, 2-149)
The number of significant digits is 24 for a normalized number and 23 for adenormalized number (number of leading zeros in the fractional part).
In future versions of the SuperH series, the above error is guaranteed, but the sameresult as SH-4 is not guaranteed.
FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for thefollowing purposes:
• Inner product (m does not= n):
This operation is generally used for surface/rear surface determination forpolygon surfaces.
• Sum of square of elements (m = n):
This operation is generally used to find the length of a vector.
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Since approximate-value computations are performed to enable high-speedcomputation, the inexact exception (I) bit in the cause field and flag field is alwaysset to 1 when an FIPR instruction is executed. Therefore, if the corresponding bit isset in the enable field, enable exception handling will be executed.
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FTRV XMTRX, FVn (n: 0, 4, 8, 12): This instruction is basically used for thefollowing purposes:
• Matrix (4 x 4). vector (4):
This operation is generally used for viewpoint changes, angle changes, ormovements called vector transformations (4-dimensional). Since affinetransformation processing for angle + parallel movement basically requires a 4 x4 matrix, the SH-4 CPU core supports 4-dimensional operations.
• Matrix (4 x 4) x matrix (4 x 4):
This operation requires the execution of four FTRV instructions.
Since approximate-value computations are performed to enable high-speedcomputation, the inexact exception (I) bit in the cause field and flag field is alwaysset to 1 when an FTRV instruction is executed. Therefore, if the corresponding bit isset in the enable field, enable exception handling will be executed. For the samereason, it is not possible to check all data types in the registers beforehand whenexecuting an FTRV instruction. If the V bit is set in the enable field, enableexception handling will be executed.
FRCHG: This instruction modifies banked registers. For example, when the FTRVinstruction is executed, matrix elements must be set in an array in the backgroundbank. However, to create the actual elements of a translation matrix, it is easier touse registers in the foreground bank. When the LDC instruction is used on FPSCR,this instruction expends 4 to 5 cycles in order to maintain the FPU state. With theFRCHG instruction, an FPSCR.FR bit modification can be performed in one cycle.
6.5.2 Pair single-precision data transfer
In addition to the powerful new geometric operation instructions, the SH-4 CPUcore also supports high-speed data transfer instructions.
When FPSCR.SZ = 1, the SH-4 CPU core can perform data transfer by means of pairsingle-precision data transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2 32-bit) data items to betransferred; that is, the transfer performance of these instructions is doubled.
• FSCHG - this instruction changes the value of the SZ bit in FPSCR, enablingfast switching between use and non-use of pair single-precision data transfer.
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7Instructionset7.1 Execution environment
PC
At the start of instruction execution, PC indicates the address of the instructionitself.
Data sizes and data types: The SH-4 instruction set is implemented with 16-bitfixed-length instructions. The SH-4 CPU core can use byte (8-bit), word (16-bit),longword (32-bit), and quadword (64-bit) data sizes for memory access.Single-precision floating-point data (32 bits) can be moved to and from memoryusing longword or quadword size. Double-precision floating-point data (64 bits) canbe moved to and from memory using longword size. When a double-precisionfloating-point operation is specified (FPSCR.PR = 1), the result of an operationusing quadword access will be undefined. When the SH-4 CPU core moves byte-sizeor word-size data from memory to a register, the data is sign-extended.
Load-store architecture
The SH-4 CPU core features a load-store architecture in which operations arebasically executed using registers. Except for bit-manipulation operations such aslogical AND that are executed directly in memory, operands in an operation thatrequires memory access are loaded into registers and the operation is executedbetween the registers.
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Delayed branches
Except for the two branch instructions BF and BT, the SH-4’s branch instructionsand RTE are delayed branches. In a delayed branch, the instruction following thebranch is executed before the branch destination instruction. This execution slotfollowing a delayed branch is called a delay slot. For example, the BRA executionsequence is as follows:
Delay slot
An illegal instruction exception may occur when a specific instruction is executed ina delay slot. See section 5, Exceptions. The instruction following BF/S or BT/S forwhich the branch is not taken is also a delay slot instruction.
T bit
The T bit in the status register (SR) is used to show the result of a compareoperation, and is referenced by a conditional branch instruction. An example of theuse of a conditional branch instruction is shown below.
In an RTE delay slot, status register (SR) bits are referenced as follows. Ininstruction access, the MD bit is used before modification, and in data access, theMD bit is accessed after modification. The other bits S, T, M, Q, FD, BL, and RBafter modification are used for delay slot instruction execution. The STC and STC.LSR instructions access all SR bits after modification.
Static sequence Dynamic sequence
BRA TARGET BRA TARGET
ADD next_2 R1, R0 ADDtarget_instr
R1, R0 ADD in delay slot is executedbefore branching to TARGET
ADD #1, R0 T bit is not changed by ADD operation
CMP/EQ R1, R0 If R0 = R1, T bit is set to 1
BT TARGET Branches to TARGET if T bit = 1 (R0 = R1)
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Constant values
An 8-bit constant value can be specified by the instruction code and an immediatevalue. 16-bit and 32-bit constant values can be defined as literal constant values inmemory, and can be referenced by a PC-relative load instruction.
There are no PC-relative load instructions for floating-point operations. However, itis possible to set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on asingle-precision floating-point register.
MOV.W @(disp, PC), Rn
MOV.L @(disp, PC), Rn
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7.2 Addressing modesAddressing modes and effective address calculation methods are shown in Table 37.When a location in virtual memory space is accessed (MMUCR.AT = 1), the effectiveaddress is translated into a physical memory address. If multiple virtual memoryspace systems are selected (MMUCR.SV = 0), the least significant bit of PTEH isalso referenced as the access ASID. See Chapter 3: Memory management unit(MMU) on page 41.
Addressingmode
Instructionformat
Effective address calculation methodCalculation
formula
Registerdirect
Rn Effective address is register Rn.(Operand is register Rn contents.)
—
Registerindirect
@Rn Effective address is register Rn contents. Rn → EA(EA: effectiveaddress)
Registerindirectwithpost-increment
@Rn+ Effective address is register Rn contents.A constant is added to Rn after instructionexecution: 1 for a byte operand, 2 for a wordoperand, 4 for a longword operand, 8 for a quadwordoperand.
Rn → EAAfterinstructionexecutionByte:Rn + 1 → RnWord:Rn + 2 → RnLongword:Rn + 4 → RnQuadword:Rn + 8 → Rn
Table 37: Addressing modes and effective addresses
Rn Rn
Rn Rn
1/2/4/8
+Rn + 1/2/4/8
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Registerindirectwithpre-decrement
@–Rn Effective address is register Rn contents,decremented by a constant beforehand:1 for a byte operand, 2 for a word operand,4 for a longword operand, 8 for a quadword operand.
Byte:Rn – 1 → RnWord:Rn – 2 → RnLongword:Rn – 4 → RnQuadword:Rn – 8 → RnRn → EA(Instructionexecutedwith Rn aftercalculation)
Registerindirect withdisplacement
@(disp:4,Rn)
Effective address is register Rn contents with4-bit displacement disp added. After disp iszero-extended, it is multiplied by 1 (byte), 2 (word),or 4 (longword), according to the operand size.
Byte: Rn +disp → EA
Word: Rn +disp × 2 → EA
Longword:Rn + disp × 4→ EA
Indexedregisterindirect
@(R0, Rn) Effective address is sum of register Rn and R0contents.
Rn + R0 →EA
Addressingmode
Instructionformat
Effective address calculation methodCalculation
formula
Table 37: Addressing modes and effective addresses
Rn
1/2/4/8
Rn – 1/2/4/8–Rn – 1/2/4/8
Rn
Rn + disp × 1/2/4+
×
1/2/4
disp(zero-extended)
Rn
R0
Rn + R0+
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GBR indirectwithdisplacement
@(disp:8,GBR)
Effective address is register GBR contents with8-bit displacement disp added. After disp iszero-extended, it is multiplied by 1 (byte), 2 (word),or 4 (longword), according to the operand size.
Byte: GBR +disp → EA
Word: GBR +disp × 2 → EA
Longword:GBR + disp ×4 → EA
Indexed GBRindirect
@(R0, GBR) Effective address is sum of register GBR and R0contents.
GBR + R0 →EA
Addressingmode
Instructionformat
Effective address calculation methodCalculation
formula
Table 37: Addressing modes and effective addresses
GBR
1/2/4
GBR+ disp × 1/2/4
+
×
disp(zero-extended)
GBR
R0
GBR + R0+
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PC-relativewithdisplacement
@(disp:8,PC)
Effective address is PC+4 with 8-bit displacementdisp added. After disp is zero-extended, it ismultiplied by 2 (word), or 4 (longword), accordingto the operand size. With a longword operand,the lower 2 bits of PC are masked.
Word: PC + 4+ disp × 2 →EA
Longword:PC &0xFFFFFFFC+ 4 + disp × 4→ EA
PC-relative disp:8 Effective address is PC+4 with 8-bit displacementdisp added after being sign-extended andmultiplied by 2.
PC + 4 + disp× 2 →Branch-Target
Addressingmode
Instructionformat
Effective address calculation methodCalculation
formula
Table 37: Addressing modes and effective addresses
PC
H'FFFFFFFC
PC + 4 + disp × 2
or PC & H'FFFFFFFC+ 4 + disp × 4
+4
2/4
×
+
& *
disp(zero-extended)
* With longword operand
OxFFFFFFFC
OxFFFFFFFC
2
+
×
disp(sign-extended)
4
+
PC
PC + 4 + disp × 2
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Note: For the addressing modes below that use a displacement (disp), the assemblerdescriptions in this manual show the value before scaling (×1, ×2, or ×4) is performedaccording to the operand size. This is done to clarify the operation of the chip. Refer tothe relevant assembler notation rules for the actual assembler descriptions.
PC-relative disp:12 Effective address is PC+4 with 12-bit displacementdisp added after being sign-extended andmultiplied by 2.
PC + 4 + disp× 2 →Branch-Target
Rn Effective address is sum of PC+4 and Rn. PC + 4 + Rn→Branch-Target
Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XORinstruction is zero-extended.
—
#imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQinstruction is sign-extended.
—
@ (disp:4, Rn) Register indirect with displacement@ (disp:8, GBR) GBR indirect with displacement@ (disp:8, PC) PC-relative with displacementdisp:8, disp:12 PC-relative
Addressingmode
Instructionformat
Effective address calculation methodCalculation
formula
Table 37: Addressing modes and effective addresses
2
+
×
disp(sign-extended)
4
+
PC
PC + 4 + disp × 2
PC
4
Rn
+
+ PC + 4 + Rn
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7.3 Instruction set summaryTable 38 shows the notation used in the following SH instruction list.
Item Format Description
Instructionmnemonic
OP.Sz SRC, DEST OP: Operation codeSz: SizeSRC: SourceDEST: Source and/or destination operand
Summary ofoperation
→, ← Transfer direction(xx) Memory operandM/Q/T SR flag bits& Logical AND of individual bits| Logical OR of individual bits∧ Logical exclusive-OR of individual bits~ Logical NOT of individual bits<<n, >>n n-bit shift
Instructioncode
MSB ↔ LSB mmmm: Register number (Rm, FRm)nnnn: Register number (Rn, FRn)0000: R0, FR00001: R1, FR1:1111: R15, FR15mmm: Register number (DRm, XDm, Rm_BANK)nnn: Register number (DRm, XDm, Rn_BANK)000: DR0, XD0, R0_BANK001: DR2, XD2, R1_BANK:111: DR14, XD14, R7_BANKmm: Register number (FVm)nn: Register number (FVn)00: FV001: FV410: FV811: FV12iiii: Immediate datadddd: Displacement
Privilegedmode
“Privileged” means the instruction can only be executed inprivileged mode.
Table 38: Notation used in instruction list
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Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instructionoperand(s).
T bit Value of T bit afterinstruction execution
—: No change
Instruction Operation Instruction code Privileged T bit
MOV #imm,Rn imm → sign extension → Rn 1110nnnniiiiiiii — —
MOV.W @(disp,PC),Rn (disp × 2 + PC + 4) → signextension → Rn
1001nnnndddddddd — —
MOV.L @(disp,PC),Rn (disp × 4 + PC & 0xFFFFFFFC+ 4) → Rn
1101nnnndddddddd — —
MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 — —
MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 — —
MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 — —
MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 — —
MOV.B @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0000 — —
MOV.W @Rm,Rn (Rm) → sign extension → Rn 0110nnnnmmmm0001 — —
MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 — —
MOV.B Rm,@-Rn Rn-1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 — —
MOV.W Rm,@-Rn Rn-2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 — —
MOV.L Rm,@-Rn Rn-4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 — —
MOV.B @Rm+,Rn (Rm)→ sign extension → Rn,Rm + 1 → Rm
0110nnnnmmmm0100 — —
MOV.W @Rm+,Rn (Rm) → sign extension → Rn,Rm + 2 → Rm
0110nnnnmmmm0101 — —
MOV.L @Rm+,Rn (Rm) → Rn, Rm + 4 → Rm 0110nnnnmmmm0110 — —
Table 39: Fixed-point transfer instructions
Item Format Description
Table 38: Notation used in instruction list
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MOV.B R0,@(disp,Rn) R0 → (disp + Rn) 10000000nnnndddd — —
MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd — —
MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd — —
MOV.B @(disp,Rm),R0 (disp + Rm) → sign extension→ R0
10000100mmmmdddd — —
MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → signextension → R0
10000101mmmmdddd — —
MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd — —
MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 — —
MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 — —
MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 — —
MOV.B @(R0,Rm),Rn (R0 + Rm) → sign extension→ Rn
0000nnnnmmmm1100 — —
MOV.W @(R0,Rm),Rn (R0 + Rm) → sign extension→ Rn
0000nnnnmmmm1101 — —
MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 — —
MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd — —
MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd — —
MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd — —
MOV.B @(disp,GBR),R0 (disp + GBR) →sign extension → R0
11000100dddddddd — —
MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →sign extension → R0
11000101dddddddd — —
MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd — —
MOVA @(disp,PC),R0 disp × 4 + PC & 0xFFFFFFFC+ 4 → R0
11000111dddddddd — —
MOVT Rn T → Rn 0000nnnn00101001 — —
Instruction Operation Instruction code Privileged T bit
Table 39: Fixed-point transfer instructions
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SWAP.B Rm,Rn Rm → swap lower 2 bytes→ REG
0110nnnnmmmm1000 — —
SWAP.W Rm,Rn Rm → swap upper/lowerwords → Rn
0110nnnnmmmm1001 — —
XTRCT Rm,Rn Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — —
Instruction Operation Instruction code Privileged T Bit
ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 — —
ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii — —
ADDC Rm,Rn Rn + Rm + T → Rn, carry → T 0011nnnnmmmm1110 — Carry
ADDV Rm,Rn Rn + Rm → Rn, overflow → T 0011nnnnmmmm1111 — Overflow
CMP/EQ #imm,R0 When R0 = imm, 1 → TOtherwise, 0 → T
10001000iiiiiiii — Comparisonresult
CMP/EQ Rm,Rn When Rn = Rm, 1 → TOtherwise, 0 → T
0011nnnnmmmm0000 — Comparisonresult
CMP/HS Rm,Rn When Rn ≥ Rm (unsigned),1 → TOtherwise, 0 → T
0011nnnnmmmm0010 — Comparisonresult
CMP/GE Rm,Rn When Rn ≥ Rm (signed), 1 →TOtherwise, 0 → T
0011nnnnmmmm0011 — Comparisonresult
CMP/HI Rm,Rn When Rn > Rm (unsigned),1 → TOtherwise, 0 → T
0011nnnnmmmm0110 — Comparisonresult
CMP/GT Rm,Rn When Rn > Rm (signed), 1 →TOtherwise, 0 → T
0011nnnnmmmm0111 — Comparisonresult
Table 40: Arithmetic operation instructions
Instruction Operation Instruction code Privileged T bit
Table 39: Fixed-point transfer instructions
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CMP/PZ Rn When Rn ≥ 0, 1 → TOtherwise, 0 → T
0100nnnn00010001 — Comparisonresult
CMP/PL Rn When Rn > 0, 1 → TOtherwise, 0 → T
0100nnnn00010101 — Comparisonresult
CMP/STR Rm,Rn When any bytes are equal,1 → TOtherwise, 0 → T
0010nnnnmmmm1100 — Comparisonresult
DIV1 Rm,Rn 1-step division (Rn ÷ Rm) 0011nnnnmmmm0100 — Calculationresult
DIV0S Rm,Rn MSB of Rn → Q,MSB of Rm → M, M^Q → T
0010nnnnmmmm0111 — Calculationresult
DIV0U 0 → M/Q/T 0000000000011001 — 0
DMULS.L Rm,Rn Signed, Rn × Rm → MAC,32 × 32 → 64 bits
0011nnnnmmmm1101 — —
DMULU.L Rm,Rn Unsigned, Rn × Rm → MAC,32 × 32 → 64 bits
0011nnnnmmmm0101 — —
DT Rn Rn – 1 → Rn; when Rn = 0,1 → TWhen Rn ≠ 0, 0 → T
0100nnnn00010000 — Comparisonresult
EXTS.B Rm,Rn Rm sign-extended frombyte → Rn
0110nnnnmmmm1110 — —
EXTS.W Rm,Rn Rm sign-extended fromword → Rn
0110nnnnmmmm1111 — —
EXTU.B Rm,Rn Rm zero-extended frombyte → Rn
0110nnnnmmmm1100 — —
EXTU.W Rm,Rn Rm zero-extended fromword → Rn
0110nnnnmmmm1101 — —
MAC.L @Rm+,@Rn+
Signed, (Rn) × (Rm) + MAC →MACRn + 4 → Rn, Rm + 4 → Rm32 × 32 + 64 → 64 bits
0000nnnnmmmm1111 — —
Instruction Operation Instruction code Privileged T Bit
Table 40: Arithmetic operation instructions
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MAC.W @Rm+,@Rn+
Signed, (Rn) × (Rm) + MAC →MACRn + 2 → Rn, Rm + 2 → Rm16 × 16 + 64 → 64 bits
0100nnnnmmmm1111 — —
MUL.L Rm,Rn Rn × Rm → MACL32 × 32 → 32 bits
0000nnnnmmmm0111 — —
MULS.W Rm,Rn Signed, Rn × Rm → MACL16 × 16 → 32 bits
0010nnnnmmmm1111 — —
MULU.W Rm,Rn Unsigned, Rn × Rm → MACL16 × 16 → 32 bits
0010nnnnmmmm1110 — —
NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — —
NEGC Rm,Rn 0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 — Borrow
SUB Rm,Rn Rn – Rm → Rn 0011nnnnmmmm1000 — —
SUBC Rm,Rn Rn – Rm – T → Rn, borrow →T
0011nnnnmmmm1010 — Borrow
SUBV Rm,Rn Rn – Rm → Rn, underflow →T
0011nnnnmmmm1011 — Underflow
Instruction Operation Instruction code Privileged T Bit
Table 40: Arithmetic operation instructions
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Instruction Operation Instruction code Privileged T Bit
AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 — —
AND #imm,R0 R0 & imm → R0 11001001iiiiiiii — —
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 +GBR)
11001101iiiiiiii — —
NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 — —
OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 — —
OR #imm,R0 R0 | imm → R0 11001011iiiiiiii — —
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 +GBR)
11001111iiiiiiii —
TAS.B @Rn When (Rn) = 0, 1 → TOtherwise, 0 → TIn both cases, 1 → MSB of(Rn)
0100nnnn00011011 — Testresult
TST Rm,Rn Rn & Rm; when result = 0,1 → TOtherwise, 0 → T
0010nnnnmmmm1000 — Testresult
TST #imm,R0 R0 & imm; when result = 0,1 → TOtherwise, 0 → T
11001000iiiiiiii — Testresult
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; whenresult = 0, 1 → TOtherwise, 0 → T
11001100iiiiiiii — Testresult
XOR Rm,Rn Rn ∧ Rm → Rn 0010nnnnmmmm1010 — —
XOR #imm,R0 R0 ∧ imm → R0 11001010iiiiiiii — —
XOR.B #imm,@(R0,GBR) (R0 + GBR) ∧ imm → (R0 +GBR)
11001110iiiiiiii — —
Table 41: Logic operation instructions
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Instruction Operation Instruction code Privileged T bit
ROTL Rn T ← Rn ← MSB 0100nnnn00000100 — MSB
ROTR Rn LSB → Rn → T 0100nnnn00000101 — LSB
ROTCL Rn T ← Rn ← T 0100nnnn00100100 — MSB
ROTCR Rn T → Rn → T 0100nnnn00100101 — LSB
SHAD Rm,Rn When Rn ≥ 0, Rn << Rm → RnWhen Rn < 0, Rn >> Rm →[MSB → Rn]
0100nnnnmmmm1100 — —
SHAL Rn T ← Rn ← 0 0100nnnn00100000 — MSB
SHAR Rn MSB → Rn → T 0100nnnn00100001 — LSB
SHLD Rm,Rn When Rn ≥ 0, Rn << Rm → RnWhen Rn < 0, Rn >> Rm →[0 → Rn]
0100nnnnmmmm1101 — —
SHLL Rn T ← Rn ← 0 0100nnnn00000000 — MSB
SHLR Rn 0 → Rn → T 0100nnnn00000001 — LSB
SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 — —
SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 — —
SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 — —
SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 — —
SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 — —
SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 — —
Table 42: Shift instructions
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Instruction Operation Instruction code Privileged T bit
BF label When T = 0, disp × 2 + PC +4 → PCWhen T = 1, nop
10001011dddddddd — —
BF/S label Delayed branch; when T = 0,disp × 2 + PC + 4 → PCWhen T = 1, nop
10001111dddddddd — —
BT label When T = 1, disp × 2 + PC +4 → PCWhen T = 0, nop
10001001dddddddd — —
BT/S label Delayed branch; when T = 1,disp × 2 + PC + 4 → PCWhen T = 0, nop
10001101dddddddd — —
BRA label Delayed branch, disp × 2 +PC + 4 → PC
1010dddddddddddd — —
BRAF Rn Rn + PC + 4 → PC 0000nnnn00100011 — —
BSR label Delayed branch, PC + 4 → PR,disp × 2 + PC + 4 → PC
1011dddddddddddd — —
BSRF Rn Delayed branch, PC + 4 → PR,Rn + PC + 4 → PC
0000nnnn00000011 — —
JMP @Rn Delayed branch, Rn → PC 0100nnnn00101011 — —
JSR @Rn Delayed branch, PC + 4 → PR,Rn → PC
0100nnnn00001011 — —
RTS Delayed branch, PR → PC 0000000000001011 — —
Table 43: Branch instructions
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Instruction Operation Instruction code Privileged T bit
CLRMAC 0 → MACH, MACL 0000000000101000 — —
CLRS 0 → S 0000000001001000 — —
CLRT 0 → T 0000000000001000 — 0
LDC Rm,SR Rm → SR 0100mmmm00001110 Privileged LSB
LDC Rm,GBR Rm → GBR 0100mmmm00011110 — —
LDC Rm,VBR Rm → VBR 0100mmmm00101110 Privileged —
LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged —
LDC Rm,SPC Rm → SPC 0100mmmm01001110 Privileged —
LDC Rm,DBR Rm → DBR 0100mmmm11111010 Privileged —
LDC Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged —
LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 Privileged LSB
LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 — —
LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Privileged —
LDC.L @Rm+,SSR (Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 Privileged —
LDC.L @Rm+,SPC (Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 Privileged —
LDC.L @Rm+,DBR (Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110 Privileged —
LDC.L @Rm+,Rn_BANK (Rm) → Rn_BANK,Rm + 4 → Rm
0100mmmm1nnn0111 Privileged —
LDS Rm,MACH Rm → MACH 0100mmmm00001010 — —
LDS Rm,MACL Rm → MACL 0100mmmm00011010 — —
LDS Rm,PR Rm → PR 0100mmmm00101010 — —
LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 →Rm
0100mmmm00000110 — —
LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 — —
LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 — —
Table 44: System control instructions
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LDTLB PTEH/PTEL → TLB 0000000000111000 Privileged —
MOVCA.L R0,@Rn R0 → (Rn) (without fetchingcache block)
0000nnnn11000011 — —
NOP No operation 0000000000001001 — —
OCBI @Rn Invalidates operand cacheblock
0000nnnn10010011 — —
OCBP @Rn Writes back and invalidatesoperand cache block
0000nnnn10100011 — —
OCBWB @Rn Writes back operand cacheblock
0000nnnn10110011 — —
PREF @Rn (Rn) → operand cache 0000nnnn10000011 — —
RTE Delayed branch, SSR/SPC →SR/PC
0000000000101011 Privileged —
SETS 1 → S 0000000001011000 — —
SETT 1 → T 0000000000011000 — 1
SLEEP Sleep or standby 0000000000011011 Privileged —
STC SR,Rn SR → Rn 0000nnnn00000010 Privileged —
STC GBR,Rn GBR → Rn 0000nnnn00010010 — —
STC VBR,Rn VBR → Rn 0000nnnn00100010 Privileged —
STC SSR,Rn SSR → Rn 0000nnnn00110010 Privileged —
STC SPC,Rn SPC → Rn 0000nnnn01000010 Privileged —
STC SGR,Rn SGR → Rn 0000nnnn00111010 Privileged —
STC DBR,Rn DBR → Rn 0000nnnn11111010 Privileged —
STC Rm_BANK,Rn Rm_BANK → Rn (m = 0 to 7) 0000nnnn1mmm0010 Privileged —
STC.L SR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 Privileged —
STC.L GBR,@-Rn Rn – 4 → Rn, GBR → (Rn) 0100nnnn00010011 — —
STC.L VBR,@-Rn Rn – 4 → Rn, VBR → (Rn) 0100nnnn00100011 Privileged —
Instruction Operation Instruction code Privileged T bit
Table 44: System control instructions
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STC.L SSR,@-Rn Rn – 4 → Rn, SSR → (Rn) 0100nnnn00110011 Privileged —
STC.L SPC,@-Rn Rn – 4 → Rn, SPC → (Rn) 0100nnnn01000011 Privileged —
STC.L SGR,@-Rn Rn – 4 → Rn, SGR → (Rn) 0100nnnn00110010 Privileged —
STC.L DBR,@-Rn Rn – 4 → Rn, DBR → (Rn) 0100nnnn11110010 Privileged —
STC.L Rm_BANK,@-Rn Rn – 4 → Rn,Rm_BANK → (Rn) (m = 0 to7)
0100nnnn1mmm0011 Privileged —
STS MACH,Rn MACH → Rn 0000nnnn00001010 — —
STS MACL,Rn MACL → Rn 0000nnnn00011010 — —
STS PR,Rn PR → Rn 0000nnnn00101010 — —
STS.L MACH,@-Rn Rn – 4 → Rn, MACH → (Rn) 0100nnnn00000010 — —
STS.L MACL,@-Rn Rn – 4 → Rn, MACL → (Rn) 0100nnnn00010010 — —
STS.L PR,@-Rn Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010 — —
TRAPA #imm PC + 2 → SPC, SR → SSR,#imm << 2 → TRA,0x160 → EXPEVT,VBR + 0x0100 → PC
11000011iiiiiiii — —
Instruction Operation Instruction code Privileged T bit
Table 44: System control instructions
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Instruction Operation Instruction code Privileged T bit
FLDI0 FRn 0x00000000 → FRn 1111nnnn10001101 — —
FLDI1 FRn 0x3F800000 → FRn 1111nnnn10011101 — —
FMOV FRm,FRn FRm → FRn 1111nnnnmmmm1100 — —
FMOV.S @Rm,FRn (Rm) → FRn 1111nnnnmmmm1000 — —
FMOV.S @(R0,Rm),FRn (R0 + Rm) → FRn 1111nnnnmmmm0110 — —
FMOV.S @Rm+,FRn (Rm) → FRn, Rm + 4 →Rm
1111nnnnmmmm1001 — —
FMOV.S FRm,@Rn FRm → (Rn) 1111nnnnmmmm1010 — —
FMOV.S FRm,@-Rn Rn-4 → Rn, FRm → (Rn) 1111nnnnmmmm1011 — —
FMOV.S FRm,@(R0,Rn) FRm → (R0 + Rn) 1111nnnnmmmm0111 — —
FMOV DRm,DRn DRm → DRn 1111nnn0mmm01100 — —
FMOV @Rm,DRn (Rm) → DRn 1111nnn0mmmm1000 — —
FMOV @(R0,Rm),DRn (R0 + Rm) → DRn 1111nnn0mmmm0110 — —
FMOV @Rm+,DRn (Rm) → DRn, Rm + 8 →Rm
1111nnn0mmmm1001 — —
FMOV DRm,@Rn DRm → (Rn) 1111nnnnmmm01010 — —
FMOV DRm,@-Rn Rn-8 → Rn, DRm →(Rn)
1111nnnnmmm01011 — —
FMOV DRm,@(R0,Rn) DRm → (R0 + Rn) 1111nnnnmmm00111 — —
FLDS FRm,FPUL FRm → FPUL 1111mmmm00011101 — —
FSTS FPUL,FRn FPUL → FRn 1111nnnn00001101 — —
FABS FRn FRn & 0x7FFF FFFF →FRn
1111nnnn01011101 — —
FADD FRm,FRn FRn + FRm → FRn 1111nnnnmmmm0000 — —
FCMP/EQ FRm,FRn When FRn = FRm, 1 →TOtherwise, 0 → T
1111nnnnmmmm0100 — Comparisonresult
Table 45: Floating-point single-precision instructions
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FCMP/GT FRm,FRn When FRn > FRm, 1 →TOtherwise, 0 → T
1111nnnnmmmm0101 — Comparisonresult
FDIV FRm,FRn FRn/FRm → FRn 1111nnnnmmmm0011 — —
FLOAT FPUL,FRn (float) FPUL → FRn 1111nnnn00101101 — —
FMAC FR0,FRm,FRn FR0*FRm + FRn → FRn 1111nnnnmmmm1110 — —
FMUL FRm,FRn FRn*FRm → FRn 1111nnnnmmmm0010 — —
FNEG FRn FRn ∧ 0x80000000 →FRn
1111nnnn01001101 — —
FSQRT FRn √FRn → FRn 1111nnnn01101101 — —
FSUB FRm,FRn FRn – FRm → FRn 1111nnnnmmmm0001 — —
FTRC FRm,FPUL (long) FRm → FPUL 1111mmmm00111101 — —
Instruction Operation Instruction code Privileged T bit
FABS DRn DRn & 0x7FFF FFFF FFFFFFFF → DRn
1111nnn001011101 — —
FADD DRm,DRn DRn + DRm → DRn 1111nnn0mmm00000 — —
FCMP/EQ DRm,DRn When DRn = DRm, 1 → TOtherwise, 0 → T
1111nnn0mmm00100 — Comparisonresult
FCMP/GT DRm,DRn When DRn > DRm, 1 → TOtherwise, 0 → T
1111nnn0mmm00101 — Comparisonresult
FDIV DRm,DRn DRn /DRm → DRn 1111nnn0mmm00011 — —
FCNVDS DRm,FPUL double_to_ float[DRm] →FPUL
1111mmm010111101 — —
FCNVSD FPUL,DRn float_to_ double [FPUL] →DRn
1111nnn010101101 — —
Table 46: Floating-point double-precision instructions
Instruction Operation Instruction code Privileged T bit
Table 45: Floating-point single-precision instructions
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FLOAT FPUL,DRn (float)FPUL → DRn 1111nnn000101101 — —
FMUL DRm,DRn DRn *DRm → DRn 1111nnn0mmm00010 — —
FNEG DRn DRn ^ 0x8000 0000 00000000 → DRn
1111nnn001001101 — —
FSQRT DRn √DRn → DRn 1111nnn001101101 — —
FSUB DRm,DRn DRn – DRm → DRn 1111nnn0mmm00001 — —
FTRC DRm,FPUL (long) DRm → FPUL 1111mmm000111101 — —
Instruction Operation Instruction code Privileged T bit
Table 46: Floating-point double-precision instructions
Instruction Operation Instruction code Privileged T bit
LDS Rm,FPSCR Rm → FPSCR 0100mmmm01101010 — —
LDS Rm,FPUL Rm → FPUL 0100mmmm01011010 — —
LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 — —
LDS.L @Rm+,FPUL (Rm) → FPUL, Rm+4 → Rm 0100mmmm01010110 — —
STS FPSCR,Rn FPSCR → Rn 0000nnnn01101010 — —
STS FPUL,Rn FPUL → Rn 0000nnnn01011010 — —
STS.L FPSCR,@-Rn Rn – 4 → Rn, FPSCR → (Rn) 0100nnnn01100010 — —
STS.L FPUL,@-Rn Rn – 4 → Rn, FPUL → (Rn) 0100nnnn01010010 — —
Table 47: Floating-point control instructions
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Instruction Operation Instruction Code Privileged T Bit
FMOV DRm,XDn DRm → XDn 1111nnn1mmm01100 — —
FMOV XDm,DRn XDm → DRn 1111nnn0mmm11100 — —
FMOV XDm,XDn XDm → XDn 1111nnn1mmm11100 — —
FMOV @Rm,XDn (Rm) → XDn 1111nnn1mmmm1000 — —
FMOV @Rm+,XDn (Rm) → XDn, Rm + 8 → Rm 1111nnn1mmmm1001 — —
FMOV @(R0,Rm),XDn (R0 + Rm) → XDn 1111nnn1mmmm0110 — —
FMOV XDm,@Rn XDm → (Rn) 1111nnnnmmm11010 — —
FMOV XDm,@-Rn Rn – 8 → Rn, XDm → (Rn) 1111nnnnmmm11011 — —
FMOV XDm,@(R0,Rn) XDm → (R0+Rn) 1111nnnnmmm10111 — —
FIPR FVm,FVn inner_product [FVm, FVn]→ FR[n+3]
1111nnmm11101101 — —
FTRV XMTRX,FVn transform_vector [XMTRX,FVn] → FVn
1111nn0111111101 — —
FRCHG ~FPSCR.FR → SPFCR.FR 1111101111111101 — —
FSCHG ~FPSCR.SZ → SPFCR.SZ 1111001111111101 — —
Table 48: Floating-point graphics acceleration instructions
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8Instructionspecification8.1 Overview
The behavior of instructions is specified using a simple notational language todescribe the effects of each instruction on the architectural state of the machine.
The language consists of the following features:
• A simple variable and type system.
• Expressions.
• Statements.
• Notation for the architectural state of the machine.
• An abstract sequential model of instruction execution.
These features are described in the following sections. Additional mechanisms aredefined to model memory, synchronization instructions, cache instructions andfloating-point. The final section gives example instruction specifications.
Each instruction is described using informal text as well as the formal notationallanguage. Sometimes it is inappropriate for one of these descriptions to convey thefull semantics. In such cases these two descriptions must be taken together toconstitute the full specification.
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8.2 Variables and typesVariables are used to hold state. The type of a variable determines the set of valuesthat the variable can take and the available operators to manipulate that variable.The supported scalar types are integers, booleans and bit-fields. One-dimensionalarrays of the scalar types are also supported.
The architectural state of the machine is represented by a set of variables. Each ofthese variables has an associated type, which is either a bit-field or an array ofbit-fields. Bit-fields are used to give a bit-accurate representation.
Additional variables are used to hold temporary values. The type of temporaryvariables is implicit, and determined by their context rather than explicitdeclaration. The type of a temporary variable is an integer, a boolean or an array ofthese.
8.2.1 Integer
An integer variable can take the value of any mathematical integer. No limits areimposed on the range of integers supported. Integers obey their standardmathematical properties. Integer operations do not overflow. The integer operatorsare defined so that singularities do not occur. For example, no definition is given tothe result of divide by zero; the operator is simply not available when the divisor iszero.
The representation of literal integer values is achieved using the followingnotations:
• Decimal numbers are represented by the regular expression: {0-9}+
• Hexadecimal numbers are represented by the regular expression: 0x{0-9a-fA-F}+
• Binary numbers are represented by the regular expression: 0b{0-1}+
These notations are standard and map onto integer values in the obvious way.Underscore characters (‘_’) can be inserted into any of the above literalrepresentations. These do not change the represented value but can be used asspacers to aid readability.
The notations allow only zero and positive numbers to be represented directly. Amonadic integer negation operator can subsequently be used to derive a negativevalue.
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8.2.2 Boolean
A boolean variable can take two values:
• Boolean false. The literal representation of boolean false is ‘FALSE’.
• Boolean true. The literal representation of boolean true is ‘TRUE’.
8.2.3 Bit-fields
Bit-fields are provided to define ‘bit-accurate’ storage.
Bit-fields containing arbitrary numbers of bits are supported. A bit-field of b bitscontains bits numbered from 0 (the least significant bit) up to b-1 (the mostsignificant bit). Each bit can take the value 0 or the value 1. Bit-fields are mappedto, and from, integers in the usual way. If bit i of a b-bit, bit-field, where i is in [0, b),is set then it contributes 2i to the integral value of the bit-field. The integral value ofthe bit-field as a whole is an integer in the range [0, 2b).
When a bit-field is read, it gives its integral value. When a bit-field is written withan integral value, the integer must be in the range of values supported by thebit-field. Typically, the only operations applied directly to bit-fields are conversionsto other types.
8.2.4 Arrays
One-dimensional arrays of the above types are also available. Indexing into ann-element array A is achieved using the notation A[i] where A is an array of sometype and i is an integer in the range [0, n). This selects the ith. element of the arrayA. If i is zero this selects the first entry, and if i is n-1 then this selects the last entry.The type of the selected element is the base type of the array.
Multi-dimensional arrays are not provided.
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8.2.5 Floating point values
Floating-point types and operators are not provided. Instead, the value in afloating-point register is represented as a bit-field. The organization of the bit-fieldis consistent with an IEEE754 format.
When a floating-point register is read, an integral representation of that bit-patternis returned. When an integral value is written into a floating-point register, thevalue written is the bit-pattern of that integer. Thus, reading and writing isachieved as bit-pattern transfers, and not by interpreting the bit-patterns as realnumbers.
The language does not provide direct means to interpret these bit-patterns as realnumbers. Instead, functions are provided which give the required functionality. Forexample, arithmetic on real numbers is represented using a function notation.
8.3 ExpressionsExpressions are constructed from monadic operators, dyadic operators andfunctions applied to variable and literal values.
There are no defined precedence and associativity rules for the operators.Parentheses are used to specify the expression unambiguously.
Sub-expressions can be evaluated in any order. If a particular evaluation order isrequired, then sub-expressions must be split into separate statements.
8.3.1 Integer arithmetic operators
Since the notation uses straightforward mathematical integers, the set of standardmathematical operators is available and already defined.
The standard dyadic operators are listed in Table 49.
Operation Description
i + j Integer addition
i - j Integer subtraction
i × j Integer multiplication
Table 49: Standard dyadic operators
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The standard monadic operators are described in Table 50.
The division operator truncates towards zero. The remainder operator is consistentwith this. The sign of the result of the remainder operator follows the sign of thedividend. Division or remainder with a divisor of zero results in a singularity, andits behavior is not defined.
For a numerator (n) and a denominator (d), the following properties hold where d≠0:
i / j Integer division
i \ j Integer remainder
Operator Description
- i Integer negation
|i| Integer modulus
Table 50: Standard monadic operators
Operation Description
Table 49: Standard dyadic operators
n d n d⁄( )× n\d( )+=
n–( ) d⁄ n d⁄( )– n d–( )⁄= =
n–( )\d n\d( )–=
n\ d–( ) n\d=
0 n\d( ) d<≤ where n 0≥ and d 0>
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8.3.2 Integer shift operators
The available integer shift operators are listed in Table 51.
The shift operators are defined on integers as follows where b ≥ 0:
Note that right shifting rounds the result towards minus infinity. This contrastswith division, which rounds towards zero, and is the reason why the right shiftdefinition is separate for positive and negative n.
8.3.3 Integer bitwise operators
The available integer bitwise operators are listed in Table 52.
Operation Description
n << b Integer left shift
n >> b Integer right shift
Table 51: Shift operators
n b« n 2b×=
n b»n 2
b⁄ where n 0≥
n 2b
1+–( ) 2b⁄ where n 0<
=
Operation Description
i ∧ j Integer bitwise AND
i ∨ j Integer bitwise OR
i ⊕ j Integer bitwise XOR
~ i Integer bitwise NOT
n<b FOR m> Integer bit-field extraction: extract m bits starting at bit b from integer n
n<b> Integer bit-field extraction: extract 1 bit starting at bit b from integer n
Table 52: Bitwise operators
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In order to define bitwise operations all integers are considered as having aninfinitely long two’s complement representation. Bit 0 is the least significant bit ofthis representation, bit 1 is the next higher bit, and so on. The value of bit b, whereb ≥ 0, in integer n is given by:
Care must be taken whenever the infinitely long two’s complement representationof a negative number is constructed. This representation will contain an infinitenumber of higher bits with the value 1 representing the sign. Typically, asubsequent conversion operation is used to discard these upper bits and return theresult back to a finite value.
Bitwise AND (∧ ), OR (∨ ), XOR (⊕ ) and NOT (∼ ) are defined on integers as follows,where b takes all values such that b ≥ 0:
Note: Bitwise NOT of any finite positive i will result in a value containing an infinitenumber of higher bits with the value 1 representing the sign.
Bitwise extraction is defined on integers as follows, where b ≥ 0 and m > 0:
The result of n<b FOR m> is an integer in the range [0, 2m).
BIT n b,( ) n 2⁄ b( )\2 where n 0≥=
BIT n– b,( ) 1 BIT n 1– b,( )– where n 0>=
BIT i j∧ b,( ) BIT i b,( ) BIT j b,( )×=
BIT i j∨ b,( ) BIT i j∧ b,( ) BIT i j⊕ b,( )+=
BIT i j⊕ b,( ) BIT i b,( ) BIT j b,( )+( )\2=
BIT ~i b,( ) 1 BIT i b,( )–=
n b FOR m⟨ ⟩ n b»( ) 2m
1–( )∧=
n b⟨ ⟩ n b FOR 1⟨ ⟩=
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8.3.4 Relational operators
Relational operators are defined to compare integral values and give a booleanresult.
8.3.5 Boolean operators
Boolean operators are defined to perform logical AND, OR, XOR and NOT. Theseoperators have boolean sources and result. Additionally, the conversion operatorINT is defined to convert a boolean source into an integer result.
Operation Description
i = j Result is true if i is equal to j, otherwise false
i ≠ j Result is true if i is not equal to j, otherwise false
i < j Result is true if i is less than j, otherwise false
i > j Result is true if i is greater than j, otherwise false
i ≤ j Result is true if i is less than or equal to j, otherwise false
i ≥ j Result is true if i is greater than or equal to j, otherwise false
Table 53: Relational operators
Operation Description
i AND j Result is true if i and j are both true, otherwise false
i OR j Result is true if either/both i and j are true, otherwise false
i XOR j Result is true if exactly one of i and j are true, otherwise false
NOT i Result is true if i is false, otherwise false
INT i Result is 0 if i is false, otherwise 1
Table 54: Boolean operators
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8.3.6 Single-value functions
In some cases it is inconvenient or inappropriate to describe an expression directlyin the specification language. In these cases a function call is used to reference theundescribed behavior.
A single-value function evaluates to a single value (the result), which can be used inan expression. The type of the result value can be determined by the expressioncontext from which the function is called. There are also multiple-value functionswhich evaluate to multiple values. These are only available in an assignmentcontext, and are described in Section 8.4.2: Assignment on page 190.
Functions can contain side-effects.
Scalar conversions
Two monadic functions are defined to support conversions between integralrepresentations of finite-precision signed and unsigned number spaces. Thesefunctions are often used to convert between bit-fields and integer values.
These two functions are defined as follows, where n > 0:
Function Description
ZeroExtendn(i) Convert integer i to an n-bit 2’s complement unsigned range
SignExtendn(i) Convert integer i to an n-bit 2’s complement signed range
Table 55: Integer conversion operators
ZeroExtendn i( ) i 0 FOR n⟨ ⟩=
SignExtendn i( )i 0 FOR n⟨ ⟩ where i n 1–⟨ ⟩ 0=
i 0 FOR n 1–( )⟨ ⟩ 2n
– where i n 1–⟨ ⟩ 1=
=
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For syntactic convenience, conversion functions are also defined for converting aninteger to a single bit and to a 32-bit register. Table 56 shows the additionalfunctions provided.
Floating-point conversions
The specification language manipulates floating-point values as integers containingthe associated IEEE754 bit-pattern. The layout of these bit-patterns is described inChapter 6: Floating-point unit on page 145. The language does not support afloating-point type.
Conversion functions are defined to support floating-point. Floating-point valuesare held as either scalar values in a single register, or vector values in multipleregisters. The available register formats are:
• One 32-bit value in a single-precision register.
• One 64-bit value in a double-precision register.
• Two 32-bit values in a pair of single-precision registers.
• Four 32-bit values in a four-entry vector of single-precision registers.
• Sixteen 32-bit values in a four-by-four matrix of single-precision registers.
Conversions are available to convert between register bit-fields in these formats andintegers or arrays of integers holding the appropriate IEEE754 bit-patterns.
Operation Description
Bit(i) Convert lowest bit of integer i to a 1-bit value
This is a convenient notation for i<0>
Register(i) Convert lowest 32 bits of integer i to a 32-bit value
This is a convenient notation for i<0 FOR 32>
Table 56: Conversion operators from integers to bit-fields
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The following conversions are provided to convert from floating-point registers:
The following conversions are provided to convert to floating-point registers:
Operation Description
FloatValue32(r) Convert a single-precision floating-point register into a 32-bit integerbit-pattern.
FloatValue64(r) Convert a double-precision floating-point register into a 64-bit integerbit-pattern.
FloatValuePair32(r) Convert a pair of single-precision floating-point registers into an arrayof 2 x 32-bit integer bit-patterns.
FloatValueVector32(r) Convert a 4-entry vector of single-precision floating-point registersinto an array of 4 x 32-bit integer bit-patterns.
FloatValueMatrix32(r) Convert a 16-entry matrix of single-precision floating-point registersinto an array of 16 x 32-bit integer bit-patterns.
Table 57: Conversion from floating-point register formats
Operation Description
FloatRegister32(i) Convert a 32-bit integer bit-pattern into a single-precisionfloating-point register.
FloatRegister64(i) Convert a 64-bit integer bit-pattern into a double-precisionfloating-point register.
FloatRegisterPair32(a) Convert an array of 2 x 32-bit integer bit-patterns into a pair ofsingle-precision floating-point registers.
FloatRegisterVector32(a) Convert an array of 4 x 32-bit integer bit-patterns into a 4-entryvector of single-precision floating-point registers.
FloatRegisterMatrix32(a) Convert an array of 16 x 32-bit integer bit-patterns into a16-entry matrix of single-precision floating-point registers.
Table 58: Conversion to floating-point register formats
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8.4 StatementsAn instruction specification consists of a sequence of statements. These statementsare processed sequentially in order to specify the effect of the instruction on thearchitectural state of the machine. The available statements are discussed in thissection.
Each statement has a semi-colon terminator. A sequence of statements can beaggregated into a statement block using ‘{’ to introduce the block and ‘}’ to terminatethe block. A statement block can be used anywhere that a statement can.
8.4.1 Undefined behavior
The statement:
UNDEFINED();
indicates that the resultant behavior is architecturally undefined.
A particular implementation can choose to specify an implementation-definedbehavior in such cases. It is very likely that any implementation-defined behaviorwill vary from implementation to implementation. Exploitation ofimplementation-defined behavior should be avoided to allow software to be portablebetween implementations.
In cases where architecturally undefined behavior can occur in user mode, theimplementation will ensure that implemented behavior does not break theprotection model. Thus, the implemented behavior will be some execution flow thatis permitted for that user mode thread.
8.4.2 Assignment
The ‘←’ operator is used to denote assignment of an expression to a variable. Anexample assignment statement is:
variable ← expression;
The expression can be constructed from variables, literals, operators and functionsas described in Section 8.3: Expressions on page 182. The expression is fullyevaluated before the assignment takes place. The variable can be an integer, aboolean, a bit-field or an array of one of these types.
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Assignment to architectural state
This is where the variable is part of the architectural state (as described inTable 59: Scalar architectural state on page 194). The type of the expression and thetype of the variable must match.
Assignment to a temporary
Alternatively, if the variable is not part of the architectural state, then it is atemporary variable. The type of the variable is determined by the type of expression.A temporary variable must be assigned to, before it is used in the instructionspecification.
Assignment of an undefined value
An assignment of the following form results in a variable being initialized with anarchitecturally undefined value:
variable ← UNDEFINED;
After assignment the variable will hold a value which is valid for its type. However,the value is architecturally undefined. The actual value can be unpredictable; thatis to say the value indicated by UNDEFINED can vary with each use ofUNDEFINED. Architecturally-undefined values can occur in both user andprivileged modes.
A particular implementation can choose to specify an implementation-defined valuein such cases. It is very likely that any implementation-defined values will varyfrom implementation to implementation. Exploitation of implementation-definedvalues should be avoided to allow software to be portable between implementations.
Assignment of multiple values
Multi-value functions are used to return multiple values, and are only availablewhen used in a multiple assignment context. The syntax consists of a list ofcomma-separated variables, an assignment symbol followed by a function call. Thefunction is evaluated and returns multiple results into the variables listed. Thenumber of variables and the number of results of the function must match. Theassigned variables must all be distinct (i.e. no aliases).
For example, a two-valued assignment from a function call with 3 parameters can berepresented as:
variable1, variable2 ← call(param1, param2, param3);
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8.4.3 Conditional
Conditional behavior is specified using ‘IF’, ‘ELSE IF’ and ‘ELSE’.
Conditions are expressions that result in a boolean value. If the condition after an‘IF’ is true, then its block of statements is executed and the whole conditional thencompletes. If the condition is false, then any ‘ELSE IF’ clauses are processed, inturn, in the same fashion. If no conditions are met and there is an ‘ELSE’ clausethen its block of statements is executed. Finally, if no conditions are met and there isno ‘ELSE’ clause, then the statement has no effect apart from the evaluation of thecondition expressions.
The ‘ELSE IF’ and ‘ELSE’ clauses are optional. In ambiguous cases, the ‘ELSE’matches with the nearest ‘IF’.
For example:
IF (condition1)block1
ELSE IF (condition2)block2
ELSEblock3
8.4.4 Repetition
Repetitive behavior is specified using the following construct:
REPEAT i FROM m FOR n STEP s block
The block of statements is iterated n times, with the integer i taking the values:
m, m + s, m + 2s, m + 3s, up to m + (n - 1) × s.
The behavior is equivalent to textually writing the block n times with i beingsubstituted with the appropriate value in each copy of the block.
The value of n must be greater or equal to 0, and the value of s must be non-zero.The values of the expressions for m, n and s must be constant across the iteration.The integer i must not be assigned to within the iterated block. The ‘STEP s’ can beomitted in which case the step-size takes the default value of 1.
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8.4.5 Exceptions
Exception handling is triggered by a THROW statement. When an exception isthrown, no further statements are executed from the instruction specification andcontrol passes to an exception handler. The actions associated with the launch of thehandler are not shown in the instruction specification, but are described separatelyin Chapter 5: Exceptions on page 105.
There are two forms of throw statement:
THROW type;
and:
THROW type, value;
where type indicates the type of exception which is launched, and value is anoptional argument to the exception handling sequence.
The full set of exceptions is described in Chapter 5: Exceptions on page 105.
8.4.6 Procedures
Procedure statements contain a procedure name followed by a list ofcomma-separated arguments contained within parentheses followed by asemi-colon. The execution of procedures typically causes side-effects to thearchitectural state of the machine.
Procedures are generally used where it is difficult or inappropriate to specify theeffect of an instruction using the abstract execution model. A fuller description ofthe effect of the instruction will be given in the surrounding text.
An example procedure with two parameters is:
proc(param1, param2);
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8.5 Architectural stateThe architectural state is described in Chapter 2: Programming model on page 21.The notations used in the model to refer to this state are summarized in Table 59and Table 60. Each item of scalar architectural state is a bit-field of a particularwidth. Each item of array architectural state is an array of bit-fields of a particularwidth.
Architectural stateType is a bit-fieldcontaining:
Description
MD (SR.MD) 1 bit User (0) or privileged (1) mode
PC 32 bits 32-bit program counter
MMUCR 32 bits For details of the MMU control register seeChapter 3: Memory management unit (MMU)on page 41.
FPSCR 32 bits 32-bit floating-point status and controlregister
GBR 32 bits Global base register
MACL 32 bits Multiply-accumulate low
MACH 32 bits Multiply-accumulate high
PR 32 bits Procedure link register
T 1 bit Condition code flag
S 1 bit Multiply-accumulate saturation flag
M 1 bit Divide-step M flag
Q 1 bit Divide-step Q flag
FPUL 32 bits FPU communication register
Ri where i is in [0, 15] 32 bits 16 x 32-bit general purpose registers
FRi where i is in [0, 31] 32 bits 32 x 32-bit floating-point registers
DR2i where i is in [0,15]
64 bits 16 x 64-bit floating-point registers
Table 59: Scalar architectural state
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Note: FR, FP, FV, MTRX and DR provide different views of the same architectural state.
There is no implicit meaning to the value held by the collection of bits in a register.The interpretation of the register is supplied by each instruction that reads orwrites the register value.
PC denotes the program counter of the currently executing instruction. PC’ denotesthe program counter of the next instruction that is to be executed.
Architectural stateType is an array of bit-fields each containing:
Description
FP2i where i is in [0, 31] 32 bits 32 pairs of 32-bit floating-point registers
FV4i where i is in [0, 15] 32 bits 16 vectors of 4 x 32-bit floating-point registers
MTRX16i where i is in [0, 3] 32 bits 4 matrices of 16 x 32-bit floating-pointregisters
MEM[i] where i is in [0, 232) 8 bits 232 bytes of memory
UTLB[i] where i is in [0,63] a UTLB entry Used for translation, for further details seeChapter 3: Memory management unit (MMU)on page 41.
Table 60: Array architectural state
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8.6 Memory modelInstruction specification uses a simple model of memory. It assumes, for example,that any caches have no architectural visibility. For typical well-disciplinedinstruction sequences these effects will not be architecturally visible. However, afuller description of the behavior in other cases is defined by the text of thearchitecture manual.
MEM is an array of bytes indexed by an effective address. Elements in arrays areselected using array indexing notation: MEM[i] selects the ith. entry in the MEMarray. The total range of array indices into MEM is [0, 232), though not all of thismemory is available on all implementations.
Array slicing can be used to view an array as consisting of elements of a larger size.The notation MEM[s FOR n], where n > 0, denotes a memory slice containing theelements MEM[s], MEM[s+1] through to MEM[s+n-1]. The type of this slice is abit-field exactly large enough to contain a concatenation of the n selected elements.In this case it contain 8n bits since the base type of MEM is byte.
The order of the concatenation depends on the endianness of the processor:
• If the processor is operating in a little-endian mode, the concatenation orderobeys the following condition as i (the byte number) varies in the range [0, n):
This equivalence states that byte number i, using little-endian byte numbering(i.e. byte 0 is bits 0 to 7), in the bit-field MEM[s FOR n] is the ith. byte in memorycounting upwards from MEM[s].
• If the processor is operating in a big-endian mode, the concatenation order obeysthe following condition as i (the byte number) varies in the range [0, n):
This equivalence states that byte number i, using big-endian byte numbering(i.e. byte 0 is bits 8n-8 to 8n-1), in the bit-field MEM[s FOR n] is the ith. byte inmemory counting upwards from MEM[s].
For syntactic convenience, functions and procedures are provided to read, write andswap memory. The basic primitives support aligned accesses. Misaligned read andwrite primitives support the instructions for misaligned load and store.
MEM s FOR n[ ]( ) 8i FOR 8⟨ ⟩ MEM s i+[ ]=
MEM s FOR n[ ]( ) 8 n 1– i–( ) FOR 8⟨ ⟩ MEM s i+[ ]=
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Additionally, mechanisms are provided for reading and writing pairs of values. Pairaccess requires that each half of the pair is endianness converted separately, andthat the lower half is written into memory at the provided address while the upperhalf is written into that address plus the object size. This maintains the ordering ofthe halves of the pair as they are transferred between registers and memory. Pairaccess is used only for loading and storing pairs of single-precision floating-pointregisters (see Chapter 6: Floating-point unit on page 145).
8.6.1 Support functions
The specification of the memory instructions relies on the support functions listed inTable 61. These functions are used to model the behavior of the memorymanagement unit described in Chapter 3: Memory management unit (MMU) onpage 41.
Function Description
AddressUnavailable(address) Returns true if the provided address is outside of theavailable part of the effective address space. For furtherdetails refer to Chapter 3: Memory management unit(MMU) on page 41.
MMU() Returns true if the MMU is enabled.
DataAccessMiss(address) Returns true if the provided address does not have amapping for a data access.
InstFetchMiss(address) Returns true if the provided address does not have amapping for an instruction fetch.
InstInvalidateMiss(address) Returns true if the provided address does not have amapping for an instruction invalidation.
ReadProhibited(address) Returns true if the provided address has no read permissionfor the current privilege.
WriteProhibited(address) Returns true if the provided address has no write permissionfor the current privilege.
ExecuteProhibited(address) Returns true if the provided address has no executepermission for the current privilege.
Table 61: Support functions for memory access
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More detailed properties of translation miss detection are not modelled here. Theconditions that determine whether an access is a translation miss or a hit depend onthe MMU and cache.
DataAccessMiss is used to check for the absence of a data translation. This functionis used for all data accesses when the MMU is enabled. InstFetchMiss is used tocheck for instruction fetches.
8.6.2 Reading memory
Functions are provided to read memory.
The ReadMemoryn function takes an integer parameter to indicate the addressbeing accessed. The number of bits being read (n) is one of 8, 16 or 32 bits. Therequired bytes are read from memory, interpreted according to endianness, and aninteger result returns the read bit-field value. If the read memory value is to beinterpreted as signed, then a sign-extension should be used on the result.
DirtyBit(address) Returns the value of the dirty bit (D) in the UTLB for thetranslation used for the specified address.
IsLittleEndian() Returns true if processor is little-endian.
Function Description
Table 61: Support functions for memory access
Function Description
ReadMemoryn(address) Aligned memory read of an n-bit value
ReadMemoryPairn(address) Aligned memory read of a pair of n-bit values
Table 62: Support functions to read memory
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The assignment:
result ← ReadMemoryn(a);
is equivalent to:
width ← n >> 3;IF (AddressUnavailable(a) OR ((a∧ (width-1)) ≠ 0)) THROWRADDERR,a;IF (MMU() AND DataAccessMiss(a)) THROW RTLBMISS,a;IF (MMU() AND ReadProhibited(a)) THROW READPROT,a;result ← MEM[a FOR width];
ReadMemoryPairn reads a pair of n-bit values. The alignment check requiresalignment for a 2n-bit access. The access maintains the ordering of the two halves ofthe pair, with endianness applied separately to each half. The assignment:
result ← ReadMemoryPairn(a);
is equivalent to:
width ← n >> 3;pairwidth ← n << 1;IF (AddressUnavailable(a) OR ((a∧ (pairwidth-1)) ≠ 0)) THROWRADDERR,a;IF (MMU() AND DataAccessMiss(a)) THROW RTLBMISS,a;IF (MMU() AND ReadProhibited(a)) THROW READPROT,a;low ← MEM[a FOR width];high ← MEM[a+width FOR width];result ← low + (high << n);
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8.6.3 Prefetching memory
A function is provided to denote memory prefetch.
This is used for a software-directed data prefetch from a specified effective address.This is a hint to give advance notice that particular data will be required. It isimplementation-specific as to whether a prefetch will be performed.
The statement:
result ← PrefetchMemory(a);
is equivalent to:
IF (NOT AddressUnavailable(address))IF (NOT (MMU() AND DataAccessMiss(address)))IF (NOT (MMU() AND ReadProhibited(address)))PREF(address);
result ← 0;
where PREF is a cache operation defined in Section 8.7: Cache model on page 202.This function does not raise exceptions. PrefetchMemory evaluates to zero forsyntactic convenience.
8.6.4 Writing memory
Procedures are provided to write memory.
The WriteMemoryn procedure takes an integer parameter to indicate the addressbeing accessed, followed by an integer parameter containing the value to be written.
Function Description
PrefetchMemory(address) Memory prefetch
Table 63: Support procedure to prefetch memory
Function Description
WriteMemoryn(address, value) Aligned memory write to an n-bit value
WriteMemoryPairn(address, value) Aligned memory write to a pair of n-bit values
Table 64: Support procedures to write memory
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The number of bits being written (n) is one of 8, 16 or 32 bits. The written value isinterpreted as a bit-field of the required size; all higher bits of the value arediscarded. The bytes are written to memory, ordered according to endianness. Thestatement:
WriteMemoryn(a, value);
is equivalent to:
width ← n >> 3;IF (AddressUnavailable(a) OR ((a∧ (width-1)) ≠ 0)) THROWWADDERR,a;IF (MMU() AND DataAccessMiss(a)) THROW WTLBMISS,a;IF (MMU() AND WriteProhibited(a)) THROW WRITEPROT,a;IF (MMU() AND NOT DirtyBit(a)) THROW FIRSTWRITE,a;MEM[a FOR width] ← value<0 FOR n>;
WriteMemoryPairn writes a pair of n-bit values. The alignment check requiresalignment for a 2n-bit access. The access maintains the ordering of the two halves ofthe pair, with endianness applied separately to each half. The statement:
WriteMemoryPairn(a, value);
is equivalent to:
width ← n >> 3;pairwidth ← n << 1;IF (AddressUnavailable(a) OR ((a∧ (pairwidth-1)) ≠ 0)) THROW WADDERR,a;IF (MMU() AND DataAccessMiss(a)) THROW WTLBMISS,a;IF (MMU() AND WriteProhibited(a)) THROW WRITEPROT,a;IF (MMU() AND NOT DirtyBit(a)) THROW FIRSTWRITE,a;MEM[a FOR width] ← value<0 FOR n>;
MEM[a+width FOR width] ← value<n FOR n>;
Sleep operations
The SLEEP operation is used to enter sleep mode. The effects of this operation isbeyond the scope of the specification language, and it is therefore modelled using
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procedure calls. The behavior of these procedure calls is elaborated in the text of themanual.
8.7 Cache modelCache operations are used to allocate, prefetch and cohere lines in caches. Theeffects of these operations are beyond the scope of the specification language, andare therefore modelled using procedure calls. The behavior of these procedure callsis elaborated in the text of the manual.
8.8 Floating-point modelThe floating-point specification is abstracted using functions to hide the low-leveldetails. Additional information is provided in a tabular form to describe special andexceptional cases. Chapter 6: Floating-point unit on page 145 provides a textualdescription of floating-point operation.
8.8.1 Functions to access SR and FPSCR
The floating-point instruction specifications use a function notation to access SRand FPSCR state. The used functions are described in Table 67.
Procedure Description
SLEEP() Procedure to enter sleep mode
Table 65: Procedures to model sleep operation
Procedure Description
ALLOCO(address) Procedure to allocate an operand cache block.
OCBI(address) Procedure to invalidate an operand cache block.
OCBP(address) Procedure to purge an operand cache block.
OCBWB(address) Procedure to write-back an operand cache block.
PREF (address) Procedure to prefetch an operand cache block.
Table 66: Procedures to model cache operations
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Function Description
FpuIsDisabled(SR) True if SR.FD is 1, otherwise false
FpuFlagI(FPSCR) True if FPSCR.FLAG.I (sticky flag for inexact) is 1, otherwise false
FpuFlagU(FPSCR) True if FPSCR.FLAG.U (sticky flag for underflow) is 1, otherwise false
FpuFlagO(FPSCR) True if FPSCR.FLAG.O (sticky flag for overflow) is 1, otherwise false
FpuFlagZ(FPSCR) True if FPSCR.FLAG.Z (sticky flag for divide by zero) is 1, otherwise false
FpuFlagV(FPSCR) True if FPSCR.FLAG.V (sticky flag for invalid) is 1, otherwise false
FpuCauseI(FPSCR) True if FPSCR.CAUSE.I (cause flag for inexact) is 1, otherwise false
FpuCauseU(FPSCR) True if FPSCR.CAUSE.U (cause flag for underflow) is 1, otherwise false
FpuCauseO(FPSCR) True if FPSCR.CAUSE.O (cause flag for overflow) is 1, otherwise false
FpuCauseZ(FPSCR) True if FPSCR.CAUSE.Z (cause flag for divide by zero) is 1, otherwise false
FpuCauseV(FPSCR) True if FPSCR.CAUSE.V (cause flag for invalid) is 1, otherwise false
FpuCauseE(FPSCR) True if FPSCR.CAUSE.E (cause flag for FPU error) is 1, otherwise false
FpuEnableI(FPSCR) True if FPSCR.ENABLE.I (exception enable for inexact) is 1, otherwise false
FpuEnableU(FPSCR) True if FPSCR.ENABLE.U (exception enable for underflow) is 1, otherwise false
FpuEnableO(FPSCR) True if FPSCR.ENABLE.O (exception enable for overflow) is 1, otherwise false
FpuEnableZ(FPSCR) True if FPSCR.ENABLE.Z (exception enable for divide by zero) is 1, otherwisefalse
FpuEnableV(FPSCR) True if FPSCR.ENABLE.V (exception enable for invalid) is 1, otherwise false
Table 67: SR and FPSCR access
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8.8.2 Functions to model floating-point behavior
Functions are used to model almost all of the floating-point behavior. Each functionis associated with a list of results and a list of parameters. The functionsencapsulate the computation associated with the instruction. This includeshandling of input denormalized values, special case detection, exceptional cases andthe floating-point arithmetic.
The following tables summarize the functions used by each instruction. The tableshows how the parameters are interpreted and how the results are computed. Thenth. parameter is denoted as Pn and the nth. result as RESn.
The parameters and results of these functions are all modeled as integer values. Forfloating-point parameters and results, these values are integer bit-patternsrepresenting the IEEE754 formats. Multi-value results are used to return tworesults: the computed result and a new value for FPSCR. If the new value of FPSCRcauses an exception to be raised, then the destination register will not be updatedwith the computed result.
Instruction Function RES0 RES1 P0, P1 P2
FADD.S FADD_S Single result of (P0 +IEEE754 P1) New FPSCR Single Old FPSCR
FADD.D FADD_D Double result of (P0 +IEEE754 P1) New FPSCR Double Old FPSCR
FSUB.S FSUB_S Single result of (P0 -IEEE754 P1) New FPSCR Single Old FPSCR
FSUB.D FSUB_D Double result of (P0 -IEEE754 P1) New FPSCR Double Old FPSCR
FMUL.S FMUL_S Single result of (P0 ×IEEE754 P1) New FPSCR Single Old FPSCR
FMUL.D FMUL_D Double result of (P0 ×IEEE754 P1) New FPSCR Double Old FPSCR
FDIV.S FDIV_S Single result of (P0 /IEEE754 P1) New FPSCR Single Old FPSCR
FDIV.D FDIV_D Double result of (P0 /IEEE754 P1) New FPSCR Double Old FPSCR
Table 68: Floating-point dyadic arithmetic
Instruction Function RES0 RES1 P0 P1
FABS.S FABS_S Single result of absolute P0 (not used) Single Old FPSCR
FABS.D FABS_D Double result of absolute P0 (not used) Double Old FPSCR
Table 69: Floating-point monadic arithmetic
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FNEG.S FNEG_S Single result of negating P0 (not used) Single Old FPSCR
FNEG.D FNEG_D Double result of negating of P0 (not used) Double Old FPSCR
FSQRT.S FSQRT_S Single result of IEEE754√P0 New FPSCR Single Old FPSCR
FSQRT.D FSQRT_D Double result of IEEE754√P0 New FPSCR Double Old FPSCR
Instruction Function RES0 RES1 P0, P1 P2
FCMPEQ.S FCMPEQ_S Boolean result of (P0 =IEEE754 P1) New FPSCR Single Old FPSCR
FCMPEQ.D FCMPEQ_D Boolean result of (P0 =IEEE754 P1) New FPSCR Double Old FPSCR
FCMPGT.S FCMPGT_S Boolean result of (P0 >IEEE754 P1) New FPSCR Single Old FPSCR
FCMPGT.D FCMPGT_D Boolean result of (P0 >IEEE754 P1) New FPSCR Double Old FPSCR
Table 70: Floating-point comparisons
Instruction Function RES0 RES1 P0 P1
FCNV.SD FCNV_SD P0 is converted to double result New FPSCR Single Old FPSCR
FCNV.DS FCNV_DS P0 is converted to single result New FPSCR Double Old FPSCR
FTRC.SL FTRC_SL P0 is converted to signed 32-bitinteger result
New FPSCR Single Old FPSCR
FTRC.DL FTRC_DL P0 is converted to signed 32-bitinteger result
New FPSCR Double Old FPSCR
FLOAT.LS FLOAT_LS P0 is converted to single result New FPSCR 32-bit int Old FPSCR
FLOAT.LD FLOAT_LD P0 is converted to double result New FPSCR 32-bit int Old FPSCR
Table 71: Floating-point conversions
Instruction Function RES0 RES1 P0, P1, P2 P3
FMAC.S FMAC_S Single result of fused (P0 × P1) + P2 New FPSCR Single Old FPSCR
Table 72: Floating-point multiply-accumulate
Instruction Function RES0 RES1 P0 P1
Table 69: Floating-point monadic arithmetic
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8.8.3 Floating-point special cases and exceptions
A special-case table is provided for each floating-point instruction that is consideredan operation and has at least one input that is interpreted as a floating-point value.This table enumerates all different possible combinations of input values and theresults returned by the instruction in the absence of an exception being raised.
The entries in the table are IEEE754 floating-point values as described in Chapter 6:Floating-point unit on page 145. Each cell entry in the table describes the resultreturned for a particular combination of floating-point inputs. If the result isinvariant, its value is given in the cell. If the result is variable, the name of theappropriate operation is entered in the cell. If the cell contains ‘n/a’ then thisindicates that an exception is always raised for that combination of inputs and thatthe implementation does not associate any value with the result.
8.9 Abstract sequential modelThis section describes the abstract sequential model that is used to specify howinstructions are executed on the SH4. It is described in terms of transitions in theexplicit architectural state of the device plus some hidden internal state held in PC”and PR” which are used to keep track of delayed state changes.
Section 8.9.1 describes the initial values taken by the internal state.
Section 8.9.2 describes the steps taken to execute each SHcompact instruction inthe abstract sequential model. Section describes the mechanisms used to modeldelayed branching.
Instruction Function RES0 RES1 P0 P1 P2
FIPR.S FIPR_S Single result of inner productof P0 with P1
New FPSCR Array of 4singles
Array of4 singles
OldFPSCR
FTRV.S FTRV_S Array of 4 single results ofmatrix transform of P0 with P1
New FPSCR Array of16 singles
Array of4 singles
OldFPSCR
Table 73: Special-purpose floating-point dyadic arithmetic
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8.9.1 Initial conditions
The hidden internal state used to keep track of delayed state changes areautomatically set to appropriate initial conditions at the beginning of a sequence ofinstructions.
The initial state is set as follows:
• PC” is set to PC+2
• PR” is set to the same value as PR
8.9.2 Instruction execution loop
The steps associated with executing each instruction are:
1 Check for asynchronous events, such as interrupt or reset, and initiate handlingif required. Asynchronous events are not accepted between a delayed branch anda delay slot. They are delayed until after the delay slot.
2 Check the current program counter (PC) for instruction address exceptions, andinitiate handling if required.
3 Fetch the instruction bytes from the address in memory, as indicated by thecurrent program counter, 2 bytes need to be fetched for each instruction.
4 Calculate the default values of PC’ and PR’. PC’ is set to the value of PC”, PR’ isset to the value of PR”.
5 Calculate the default values of PC” and PR” assuming continued sequentialexecution without procedure call or mode switch: PC” is PC’+2, while PR” isunchanged.
6 Decode and execute the instruction. This includes checks for synchronous events,such as exceptions and panics, and initiation of handling if required.Synchronous events are not accepted between a delayed branch and a delay slot.They are detected either before the delayed branch or after the delay slot.
The execution of an instruction can update the PC and PR state as follows:
• The instruction can change PC’ to achieve a branch after this instruction hascompleted. It must also update PC” to the value of PC’+2 to ensure correctsequential execution after the control flow.
• The instruction can change PR’ to load the procedure link register. It must alsoupdate PR” to the same value as PR’.
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• The instruction can change PC” and PR” to achieve a branch or procedure callafter the next instruction has completed.
Any changes made to PC’, PR’, PC” or PR” over-ride the default values.
7 Set the current program counter (PC) to the value of the next program counter(PC’) and PR to the value of PR’.
The actions associated with the handling of asynchronous and synchronous eventsare described in Chapter 5: Exceptions on page 105. The actions required by step 6depend on the instruction, and are specified by the instruction specification for thatinstruction. Step 7 specifies the behavior for PC overflow. Non-delayed And Delayed
8.9.3 State changes
Non-delayed and delayed state changes are used to model the branch mechanism.These correspond to non-delayed and delayed branches.
In the model, PC and PR are never written directly by an instruction. Instead, aninstruction writes to PC’ or PR’ to cause a non-delayed state change, or to PC” or PR”to cause a delayed state change:
• A non-delayed state change is achieved by updating PC’ or PR’ to over-ride theirdefault values. After the execution of this instruction, PC’ and PR’ get copied toPC and PR respectively, and then influence instruction execution. Hence, thereis no delay slot before the values of PC’ and PR’ propagate through to PC and PR.
• A delayed state change is achieved by updating PC” or PR” to over-ride theirdefault values. After the execution of this instruction, PC” and PR” get copied toPC’ and PR’ respectively. After the execution of the next instruction, PC’ and PR’get copied to PC and PR respectively, and then influence instruction execution.Hence, there is a delay slot before the values of PC’ and PR” propagate throughto PC and PR.
There are potential ambiguities when one instruction makes a delayed state changeand the immediately following instruction (which is in a delay slot) makes anon-delayed state change. These are handled as follows:
• The case of a delayed state change to PC immediately followed by a non-delayedstate change to PC does not occur. This is because delay slot instructions thatwrite to PC are illegal and cause an ILLSLOT exception.
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• The case of a delayed state change to PR immediately followed by a non-delayedstate change to PR can occur. The ambiguous cases are when a BSR, BSRF orJSR instruction is followed by an LDS that writes to PR. In this case the PR,observed by the instruction that dynamically follows the LDS instruction, is thevalue written by LDS not the value written by the sub-routine call. Thisbehavior follows from the model described above.
There are also potential ambiguities when one instruction makes a delayed statechange and the immediately following instruction (which is in a delay slot) readsfrom that state. These are handled as follows:
• The case of a delayed state change to PC immediately followed by a read of PCdoes not occur. This is because delay slot instructions that read from PC areillegal and cause an ILLSLOT exception.
• The case of a delayed state change to PR immediately followed by a read from PRcan occur. The ambiguous cases are when a BSR, BSRF or JSR instruction isfollowed by an STS that reads from PR. In this case the PR, observed by the STSinstruction, is the value written by the sub-routine call and not the previousvalue. This behavior is modeled explicitly in the definition of the STSinstruction. It reads the value from PR’ (rather than the intuitive read from PR).
8.10 Example instructions
8.10.1 ADD #imm, Rn
An example specification for this instruction is shown below.
ADD #imm, Rn
0111 n s
15 12 11 8 7 0
imm ← SignExtend8(s);op2 ← SignExtend32(Rn);op2 ← op2 + imm;Rn ← Register(op2);
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The top half of this figure shows the assembly syntax and the binary encoding of theinstruction. Particular fields within the encoding are identified by single characters.The opcode field, and any extension field, contain the literal encoding valuesassociated with that instruction. Reserved fields must be encoded with the literalvalue given in the figure. Operand fields contain register designators or immediateconstants.
The lower half of this figure specifies the effects of the execution of the instructionon the architectural state of the machine. The specification statements areorganized into 3 stages as follows:
1 The first two statements read all required source information:
imm ← SignExtend8(s);
op2 ← SignExtend32(Rn);
The first statement reads the value of s, interprets it as a sign-extended 8-bitinteger value and assigns this to a temporary integer called ‘imm’. The name‘imm’ corresponds to the name of the immediate used in the assembly syntax.The second statement reads the value of Rn register, interprets it as asign-extended 32-bit integer value and assigns this to a temporary integer calledop2.
2 The next statement implements the addition:
op2 ← op2 + imm;
This statement does not refer to any architectural state. It adds the 2 integers‘imm’ and ‘op2’ together, and assigns the result to a temporary integer called‘op2’. Note that since this is a conventional mathematical addition, the resultcan contain more significant bits of information than the sources.
3 The final statement updates the architectural state:
Rn ← Register(op2);
The integer ‘op2’ is converted back to a register bit-field, assigned to the Rnregister.
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8.10.2 FADD FRm, FRn
An example specification for this instruction is shown below.
The specification statements are organized as follows:
1 Read all required source information:
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValue32(FRm);
op2 ← FloatValue32(FRn);
Execute the instruction:IF (FpuIsDisabled(sr) AND IsDelaySlot())THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
FADD FRm, FRn
1111 n m 0000
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FADD_S(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op2);FPSCR ← ZeroExtend32(fps);
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THROW FPUDIS;op2, fps ← FADD_S(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))THROW FPUEXC, fps;IF (FpuCauseE(fps))THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))THROW FPUEXC, fps;
The behavior of the floating-point single-precision addition is modelled by theFADD_S procedure. This procedure is given the two source operands and thecurrent value of FPSCR, and calculates the result and the new value of FPSCR. It isresponsible for detecting special cases and exceptions, and setting the result andnew FPSCR values accordingly.
This instruction contains exception cases. These are detected by IF statements andare raised by THROW statements. When a THROW statement is executed, nofurther statements from the specification are processed. In exception cases, thisspecification makes no updates to architectural state. Instead, a handler is launchedfor the exception as described in Chapter 5: Exceptions on page 105. The THROWstatement includes arguments to specify the kind of exception and any necessaryparameters of that exception. For an FPUEXC exception, the THROW statementincludes an updated value of ‘fps’ which the exception handler uses to initializeFPSCR during the launch sequence.
2 Update the architectural state:
FRn ← FloatRegister32(op2);
FPSCR ← ZeroExtend32(fps);
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9Instructiondescriptions9.1 Alphabetical list of instructions
Instructions are listed in this section in alphabetical order.
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ADD Rm, RnDescription
This instruction adds Rm to Rn and places the result in Rn.
Operation
Note
ADD Rm, Rn
0011 n m 1100
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);op2 ← op2 + op1;Rn ← Register(op2);
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ADD #imm, RnDescription
This instruction adds Rn to the sign-extended 8-bit immediate s and places theresult in Rn.
Operation
Note
The ‘#imm’ in the assembly syntax represents the immediate s after sign extension.
ADD #imm, Rn
0111 n s
15 12 11 8 7 0
imm ← SignExtend8(s);op2 ← SignExtend32(Rn);op2 ← op2 + imm;Rn ← Register(op2);
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ADDC Rm, RnDescription
This instruction adds Rm, Rn and the T-bit. The result of the addition is placed in Rn.and the carry-out from the addition is placed in the T-bit.
Operation
Note
ADDC Rm, Rn
0011 n m 1110
15 12 11 8 7 4 3 0
t ← ZeroExtend1(T);op1 ← ZeroExtend32(SignExtend32(Rm));op2 ← ZeroExtend32(SignExtend32(Rn));op2 ← (op2 + op1) + t;t ← op2< 32 FOR 1 >;Rn ← Register(op2);T ← Bit(t);
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ADDV Rm, RnDescription
This instruction adds Rm to Rn and places the result in Rn. The T-bit is set to 1 if theaddition result is outside the 32-bit signed range, otherwise the T-bit is set to 0.
Operation
Note
ADDV Rm, Rn
0011 n m 1111
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);op2 ← op2 + op1;
t ← INT ((op2 < (- 231)) OR (op2 ≥ 231));Rn ← Register(op2);T ← Bit(t);
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AND Rm, RnDescription
This instruction performs bitwise AND of Rm with Rn and places the result in Rn.
Operation
Note
This instruction performs a 32-bit bitwise AND.
AND Rm, Rn
0010 n m 1001
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← ZeroExtend32(Rn);op2 ← op2 ∧ op1;Rn ← Register(op2);
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AND #imm, R0Description
This instruction performs bitwise AND of R0 with the zero-extended 8-bitimmediate i and places the result in R0.
Operation
Note
This instruction performs a 32-bit bitwise AND. The ‘#imm’ in the assembly syntaxrepresents the immediate i after zero extension.
AND #imm, R0
11001001 i
15 8 7 0
r0 ← ZeroExtend32(R0);imm ← ZeroExtend8(i);r0 ← r0 ∧ imm;R0 ← Register(r0);
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AND.B #imm, @(R0, GBR)Description
This instruction performs a bitwise AND of an immediate constant with 8 bits ofdata held in memory. The effective address is calculated by adding R0 and GBR. The8 bits of data at the effective address are read. A bitwise AND is performed of theread data with the zero-extended 8-bit immediate i. The result is written back to the8 bits of data at the same effective address.
Operation
Exceptions
WADDERR, WTLBMISS, READPROT, WRITEPROT, FIRSTWRITE
Note
Zero-extension is performed on the effective address computation allowing wraparound to occur.
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
AND.B #imm, @(R0, GBR)
11001101 i
15 8 7 0
r0 ← SignExtend32(R0);gbr ← SignExtend32(GBR);imm ← ZeroExtend8(i);address ← ZeroExtend32(r0 + gbr);value ← ZeroExtend8(ReadMemory8(address));value ← value ∧ imm;WriteMemory8(address, value);
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BF labelDescription
This instruction is a conditional branch. The 8-bit displacement s is sign-extended,doubled and added to PC+4 to form the target address. If the T-bit is 1, the branch isnot taken. If the T-bit is 0, the target address is copied to the PC.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
BF label
10001011 s
15 8 7 0
t ← ZeroExtend1(T);pc ← SignExtend32(PC);newpc ← SignExtend32(PC’);delayedpc ← SignExtend32(PC’’);label ← SignExtend8(s) << 1;IF (IsDelaySlot())
THROW ILLSLOT;IF (t = 0){
temp ← ZeroExtend32(pc + 4 + label);
newpc ← temp;delayedpc ← temp + 2;
}PC’ ← Register(newpc);PC’’ ← Register(delayedpc);
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This is not a delayed branch instruction. An ILLSLOT exception is raised if thisinstruction is executed in a delay slot.
The ‘label’ in the assembly syntax represents the immediate s after sign extensionand scaling.
If the branch target address is invalid then the IADDERR trap is not delivered untilafter the branch instruction completes its execution and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
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BF/S labelDescription
This instruction is a delayed conditional branch. The 8-bit displacement s issign-extended, doubled and added to PC+4 to form the target address. If the T-bit is1, the branch is not taken. If the T-bit is 0, the delay slot is executed and then thetarget address is copied to the PC.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The delay slot is executed before branching. An ILLSLOT exception is raised if thisinstruction is executed in a delay slot.
BF/S label
10001111 s
15 8 7 0
t ← ZeroExtend1(T);pc ← SignExtend32(PC);delayedpc ← SignExtend32(PC’’);label ← SignExtend8(s) << 1;IF (IsDelaySlot())
THROW ILLSLOT;IF (t = 0){
temp ← ZeroExtend32(pc + 4 + label);
delayedpc ← temp;}PC’’ ← Register(delayedpc);
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The ‘label’ in the assembly syntax represents the immediate s after sign extensionand scaling.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
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BRA labelDescription
This instruction is a delayed unconditional branch. The 12-bit displacement s issign-extended, doubled and added to PC+4 to form the target address. The delay slotis executed and then the target address is copied to the PC.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The delay slot is executed before branching. An ILLSLOT exception is raised if thisinstruction is executed in a delay slot.
The ‘label’ in the assembly syntax represents the immediate s after sign extensionand scaling.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
BRA label
1010 s
15 12 11 0
pc ← SignExtend32(PC);label ← SignExtend12(s) << 1;IF (IsDelaySlot())
THROW ILLSLOT;temp ← ZeroExtend32(pc + 4 + label);
delayedpc ← temp;PC’’ ← Register(delayedpc);
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BRAF RnDescription
This instruction is a delayed unconditional branch. The target address is calculatedby adding Rn to PC+4. If the least significant bit of the target address is set, anIADDERR exception is raised, otherwise, the delay slot is executed.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The delay slot is executed before branching occurs. An ILLSLOT exception is raisedif this instruction is executed in a delay slot.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
BRAF Rn
0000 n 00100011
15 12 11 8 7 0
pc ← SignExtend32(PC);op1 ← SignExtend32(Rn);IF (IsDelaySlot())
THROW ILLSLOT;target ← ZeroExtend32(pc + 4 + op1);
delayedpc ← target ∧ (~ 0x1);PC’’ ← Register(delayedpc);
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BRKDescription
The BRK instruction causes a pre-execution BREAK exception. This exception isgenerated even BRK is executed in a delay slot. BRK is typically reserved for use bythe debugger.
Operation
Exceptions
BREAK
BRK
0000000000111011
15 0
THROW BREAK;
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BSR labelDescription
This instruction is a delayed unconditional branch used for branching to asubroutine. The 12-bit displacement s is sign-extended, doubled and added to PC+4to form the target address. The delay slot is executed and then the target address iscopied to the PC. The address of the instruction immediately following the delay slotis copied to PR to indicate the return address.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The delay slot is executed before branching. An ILLSLOT exception is raised if thisinstruction is executed in a delay slot. The ‘label’ in the assembly syntax representsthe immediate s after sign extension and scaling.
BSR label
1011 s
15 12 11 0
pc ← SignExtend32(PC);label ← SignExtend12(s) << 1;IF (IsDelaySlot())
THROW ILLSLOT;delayedpr ← pc + 4;temp ← ZeroExtend32(pc + 4 + label);delayedpc ← temp;PR’’ ← Register(delayedpr);PC’’ ← Register(delayedpc);
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If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
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BSRF RnDescription
This instruction is a delayed unconditional branch used for branching to a farsubroutine. The target address is calculated by adding Rn to PC+4. If the leastsignificant bit of the target address is set, an IADDERR exception is raised,otherwise, the delay slot is executed. The address of the instruction immediatelyfollowing the delay slot is copied to PR to indicate the return address.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The delay slot is executed before branching and before PR is updated. An ILLSLOTexception is raised if this instruction is executed in a delay slot.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
BSRF Rn
0000 n 00000011
15 12 11 8 7 0
pc ← SignExtend32(PC);op1 ← SignExtend32(Rn);IF (IsDelaySlot())
THROW ILLSLOT;delayedpr ← pc + 4;target ← ZeroExtend32(pc + 4 + op1);
delayedpc ← target ∧ (~ 0x1);PR’’ ← Register(delayedpr);PC’’ ← Register(delayedpc);
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BT labelDescription
This instruction is a conditional branch. The 8-bit displacement s is sign-extended,doubled and added to PC+4 to form the target address. If the T-bit is 0, the branch isnot taken. If the T-bit is 1, the target address is copied to the PC.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
BT label
10001001 s
15 8 7 0
t ← ZeroExtend1(T);pc ← SignExtend32(PC);newpc ← SignExtend32(PC’);delayedpc ← SignExtend32(PC’’);label ← SignExtend8(s) << 1;IF (IsDelaySlot())
THROW ILLSLOT;IF (t = 1){
temp ← ZeroExtend32(pc + 4 + label);
newpc ← temp;delayedpc ← temp + 2;
}PC’ ← Register(newpc);PC’’ ← Register(delayedpc);
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This is not a delayed branch instruction. An ILLSLOT exception is raised if thisinstruction is executed in a delay slot.
The ‘label’ in the assembly syntax represents the immediate s after sign extensionand scaling.
If the branch target address is invalid then the IADDERR trap is not delivered untilafter the branch instruction completes its execution and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
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BT/S labelDescription
This instruction is a delayed conditional branch. The 8-bit displacement s issign-extended, doubled and added to PC+4 to form the target address. If the T-bit is0, the branch is not taken. If the T-bit is 1, the delay slot is executed and then thetarget address is copied to the PC.
Operation
Exceptions
ILLSLOT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The delay slot is executed before branching. An ILLSLOT exception is raised if thisinstruction is executed in a delay slot.
BT/S label
10001101 s
15 8 7 0
t ← ZeroExtend1(T);pc ← SignExtend32(PC);delayedpc ← SignExtend32(PC’’);label ← SignExtend8(s) << 1;IF (IsDelaySlot())
THROW ILLSLOT;IF (t = 1){
temp ← ZeroExtend32(pc + 4 + label);
delayedpc ← temp;}PC’’ ← Register(delayedpc);
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The ‘label’ in the assembly syntax represents the immediate s after sign extensionand scaling.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
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CLRMACDescription
This instruction clears MACL and MACH.
Operation
CLRMAC
0000000000101000
15 0
macl ← 0;mach ← 0;MACL ← ZeroExtend32(macl);MACH ← ZeroExtend32(mach);
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CLRSDescription
This instruction clears the S-bit.
Operation
CLRS
0000000001001000
15 0
s ← 0;S ← Bit(s);
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CLRTDescription
This instruction clears the T-bit.
Operation
CLRT
0000000000001000
15 0
t ← 0;T ← Bit(t);
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CMP/EQ Rm, RnDescription
This instruction sets the T-bit if the value of Rn is equal to the value of Rm,otherwise it clears the T-bit.
Operation
Note
CMP/EQ Rm, Rn
0011 n m 0000
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);t ← INT (op2 = op1);T ← Bit(t);
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CMP/EQ #imm, R0Description
This instruction sets the T-bit if the value of R0 is equal to the sign-extended 8-bitimmediate s, otherwise it clears the T-bit.
Operation
Note
The ‘#imm’ in the assembly syntax represents the immediate s after sign extension.
CMP/EQ #imm, R0
10001000 s
15 8 7 0
r0 ← SignExtend32(R0);imm ← SignExtend8(s);t ← INT (r0 = imm);T ← Bit(t);
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CMP/GE Rm, RnDescription
This instruction sets the T-bit if the signed value of Rn is greater than or equal tothe signed value of Rm, otherwise it clears the T-bit.
Operation
Note
CMP/GE Rm, Rn
0011 n m 0011
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);t ← INT (op2 ≥ op1);T ← Bit(t);
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CMP/GT Rm, RnDescription
This instruction sets the T-bit if the signed value of Rn is greater than the signedvalue of Rm, otherwise it clears the T-bit.
Operation
Note
CMP/GT Rm, Rn
0011 n m 0111
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);t ← INT (op2 > op1);T ← Bit(t);
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CMP/HI Rm, RnDescription
This instruction sets the T-bit if the unsigned value of Rn is greater than theunsigned value of Rm, otherwise it clears the T-bit.
Operation
Note
CMP/HI Rm, Rn
0011 n m 0110
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(SignExtend32(Rm));op2 ← ZeroExtend32(SignExtend32(Rn));t ← INT (op2 > op1);T ← Bit(t);
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CMP/HS Rm, RnDescription
This instruction sets the T-bit if the unsigned value of Rn is greater than or equal tothe unsigned value of Rm, otherwise it clears the T-bit.
Operation
Note
CMP/HS Rm, Rn
0011 n m 0010
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(SignExtend32(Rm));op2 ← ZeroExtend32(SignExtend32(Rn));t ← INT (op2 ≥ op1);T ← Bit(t);
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CMP/PL RnDescription
This instruction sets the T-bit if the signed value of Rn is greater than 0, otherwiseit clears the T-bit.
Operation
Note
CMP/PL Rn
0100 n 00010101
15 12 11 8 7 0
op1 ← SignExtend32(Rn);t ← INT (op1 > 0);T ← Bit(t);
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CMP/PZ RnDescription
This instruction sets the T-bit if the signed value of Rn is greater than or equal to 0,otherwise it clears the T-bit.
Operation
Note
CMP/PZ Rn
0100 n 00010001
15 12 11 8 7 0
op1 ← SignExtend32(Rn);t ← INT (op1 ≥ 0);T ← Bit(t);
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CMP/STR Rm, RnDescription
This instruction sets the T-bit if any byte in Rn has the same value as thecorresponding byte in Rm, otherwise it clears the T-bit.
Operation
Note
CMP/STR Rm, Rn
0010 n m 1100
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);temp ← op1 ⊕ op2;t ← INT (temp< 0 FOR 8 > = 0);t ← (INT (temp< 8 FOR 8 > = 0)) ∨ t;t ← (INT (temp< 16 FOR 8 > = 0)) ∨ t;t ← (INT (temp< 24 FOR 8 > = 0)) ∨ t;T ← Bit(t);
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DIV0S Rm, RnDescription
This instruction initializes the divide-step state for a signed division. The Q-bit isinitialized with the sign-bit of the dividend, and the M-bit with the sign-bit of thedivisor. The T-bit is initialized to 0 if the Q-bit and the M-bit are the same,otherwise it is initialized to 1.
Operation
Note
DIV0S Rm, Rn
0010 n m 0111
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);q ← op2< 31 FOR 1 >;m ← op1< 31 FOR 1 >;t ← m ⊕ q;Q ← Bit(q);M ← Bit(m);T ← Bit(t);
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DIV0UDescription
This instruction initializes the divide-step state for an unsigned division. The Q-bit,M-bit and T-bit are all set to 0.
Operation
DIV0U
0000000000011001
15 0
q ← 0;m ← 0;t ← 0;Q ← Bit(q);M ← Bit(m);T ← Bit(t);
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DIV1 Rm, RnDescription
This instruction is used to perform a single-bit divide-step for the division of adividend held in Rn by a divisor held in Rm. The Q-bit, M-bit and T-bit are used tohold additional state through a divide-step sequence. Each DIV1 consumes 1 bit ofthe dividend from Rn, and produces 1 bit of result. The divide initialization and stepinstructions do not detect divide-by-zero nor overflow. If required, these casesshould be checked using additional instructions.
Operation
Note
DIV1 Rm, Rn
0011 n m 0100
15 12 11 8 7 4 3 0
q ← ZeroExtend1(Q);m ← ZeroExtend1(M);t ← ZeroExtend1(T);op1 ← ZeroExtend32(SignExtend32(Rm));op2 ← ZeroExtend32(SignExtend32(Rn));oldq ← q;q ← op2< 31 FOR 1 >;op2 ← ZeroExtend32(op2 << 1) ∨ t;IF (oldq = m)
op2 ← op2 - op1;ELSE
op2 ← op2 + op1;q ← (q ⊕ m) ⊕ op2< 32 FOR 1 >;t ← 1 - (q ⊕ m);Rn ← Register(op2);Q ← Bit(q);T ← Bit(t);
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STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
DMULS.L Rm, RnDescription
This instruction multiplies the signed 32-bit value held in Rm with the signed 32-bitvalue held in Rn to give a full 64-bit result. The lower half of the result is placed inMACL and the upper half in MACH.
Operation
Note
DMULS.L Rm, Rn
0011 n m 1101
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);mac ← op2 × op1;macl ← mac;mach ← mac >> 32;MACL ← ZeroExtend32(macl);MACH ← ZeroExtend32(mach);
251PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
DMULU.L Rm, RnDescription
This instruction multiplies the unsigned 32-bit value held in Rm with the unsigned32-bit value held in Rn to give a full 64-bit result. The lower half of the result isplaced in MACL and the upper half in MACH.
Operation
Note
DMULU.L Rm, Rn
0011 n m 0101
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(SignExtend32(Rm));op2 ← ZeroExtend32(SignExtend32(Rn));mac ← op2 × op1;macl ← mac;mach ← mac >> 32;MACL ← ZeroExtend32(macl);MACH ← ZeroExtend32(mach);
252PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
DT RnDescription
This instruction subtracts 1 from Rn and placed the result in Rn. The T-bit is set ifthe result is zero, otherwise the T-bit is cleared.
Operation
Note
DT Rn
0100 n 00010000
15 12 11 8 7 0
op1 ← SignExtend32(Rn);op1 ← op1 - 1;t ← INT (op1 = 0);Rn ← Register(op1);T ← Bit(t);
253PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
EXTS.B Rm, RnDescription
This instruction reads the 8 least significant bits of Rm, sign-extends, and places theresult in Rn.
Operation
Note
EXTS.B Rm, Rn
0110 n m 1110
15 12 11 8 7 4 3 0
op1 ← SignExtend8(Rm);op2 ← op1;Rn ← Register(op2);
254PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
EXTS.W Rm, RnDescription
This instruction reads the 16 least significant bits of Rm, sign-extends, and placesthe result in Rn.
Operation
Note
EXTS.W Rm, Rn
0110 n m 1111
15 12 11 8 7 4 3 0
op1 ← SignExtend16(Rm);op2 ← op1;Rn ← Register(op2);
255PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
EXTU.B Rm, RnDescription
This instruction reads the 8 least significant bits of Rm, zero-extends, and places theresult in Rn.
Operation
Note
EXTU.B Rm, Rn
0110 n m 1100
15 12 11 8 7 4 3 0
op1 ← ZeroExtend8(Rm);op2 ← op1;Rn ← Register(op2);
256PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
EXTU.W Rm, RnDescription
This instruction reads the 16 least significant bits of Rm, zero-extends, and placesthe result in Rn.
Operation
Note
EXTU.W Rm, Rn
0110 n m 1101
15 12 11 8 7 4 3 0
op1 ← ZeroExtend16(Rm);op2 ← op1;Rn ← Register(op2);
257PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FABS DRnDescription
This floating-point instruction computes the absolute value of a double-precisionfloating-point number. It reads DRn, clears the sign bit and places the result in DRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FABS DRn
1111 n 001011101
15 12 11 9 8 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);op1 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← FABS_D(op1);DR2n ← FloatRegister64(op1);
258PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FABS FRnDescription
This floating-point instruction computes the absolute value of a single-precisionfloating-point number. It reads FRn, clears the sign bit and places the result in FRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FABS FRn
1111 n 01011101
15 12 11 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);op1 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← FABS_S(op1);FRn ← FloatRegister32(op1);
259PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FADD DRm, DRnDescription
This floating-point instruction performs a double-precision floating-point addition.It adds DRm to DRn and places the result in DRn. The rounding mode is determinedby FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FADD DRm, DRn
1111 n 0 m 00000
15 12 11 9 8 7 5 4 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);op2 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FADD_D(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;DR2n ← FloatRegister64(op2);FPSCR ← ZeroExtend32(fps);
260PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FADD FRm, FRnDescription
This floating-point instruction performs a single-precision floating-point addition. Itadds FRm to FRn and places the result in FRn. The rounding mode is determined byFPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FADD FRm, FRn
1111 n m 0000
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FADD_S(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op2);FPSCR ← ZeroExtend32(fps);
261PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FADD Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if either input is a signaling NaN, or ifthe inputs are differently signed infinities.
3 Error: an FPU error is signaled if FPSCR.DN is zero, neither input is a NaN andeither input is a denormalized number.
4 Inexact, underflow and overflow: these are checked together and can be signaledin combination. When inexact, underflow or overflow exceptions are requestedby the user, an exception is always raised regardless of whether that conditionarose.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
FPU error is indicated by heavy shading and always raises an exception. Invalidoperations are indicated by light shading and raise an exception if enabled. FPUdisabled, inexact, underflow and overflow cases are not shown.
The behavior of the normal ‘ADD’ case is described by the IEEE754 specification.
op1 →↓ op2
+NORM,-NORM
+0 -0 +INF -INF +DNORM,-DNORM
qNaN sNaN
+,-NORM ADD op2 op2 +INF -INF n/a qNaN qNaN
+0 op1 +0 +0 +INF -INF n/a qNaN qNaN
-0 op1 +0 -0 +INF -INF n/a qNaN qNaN
+INF +INF +INF +INF +INF qNaN n/a qNaN qNaN
-INF -INF -INF -INF qNaN -INF n/a qNaN qNaN
+, -DNORM n/a n/a n/a n/a n/a n/a qNaN qNaN
qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
sNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
262PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FCMP/EQ DRm, DRnDescription
This floating-point instruction performs a double-precision floating-point equalitycomparison. It sets the T-bit to 1 if DRm is equal to DRn, and otherwise sets the T-bitto 0.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FCMP/EQ DRm, DRn
1111 n 0 m 00100
15 12 11 9 8 7 5 4 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);op2 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;t, fps ← FCMPEQ_D(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;FPSCR ← ZeroExtend32(fps);T ← Bit(t);
263PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FCMP/EQ FRm, FRnDescription
This floating-point instruction performs a single-precision floating-point equalitycomparison. It sets the T-bit to 1 if FRm is equal to FRn, and otherwise sets the T-bitto 0.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FCMP/EQ Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
FCMP/EQ FRm, FRn
1111 n m 0100
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;t, fps ← FCMPEQ_S(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;FPSCR ← ZeroExtend32(fps);T ← Bit(t);
264PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if either input is a signaling NaN.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
Invalid operations are indicated by light shading and raise an exception if enabled.FPU disabled cases are not shown.
The behavior of the normal ‘CMPEQ’ case is described by the IEEE754 specification.
op1 →↓ op2
+NORM,-NORM
+0 -0 +INF -INF +DNORM,-DNORM
qNaN sNaN
+,-NORM CMPEQ false false false false false false false
+0 false true true false false false false false
-0 false true true false false false false false
+INF false false false true false false false false
-INF false false false false true false false false
+, -DNORM false false false false false CMPEQ false false
qNaN false false false false false false false false
sNaN false false false false false false false false
265PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FCMP/GT DRm, DRnDescription
This floating-point instruction performs a double-precision floating-pointgreater-than comparison. It sets the T-bit to 1 if DRn is greater than DRm, andotherwise sets the T-bit to 0.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FCMP/GT DRm, DRn
1111 n 0 m 00101
15 12 11 9 8 7 5 4 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);op2 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;t, fps ← FCMPGT_D(op2, op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;FPSCR ← ZeroExtend32(fps);T ← Bit(t);
266PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FCMP/GT FRm, FRnDescription
This floating-point instruction performs a single-precision floating-pointgreater-than comparison. It sets the T-bit to 1 if FRn is greater than FRm, andotherwise sets the T-bit to 0.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FCMP/GT Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
FCMP/GT FRm, FRn
1111 n m 0101
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;t, fps ← FCMPGT_S(op2, op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;FPSCR ← ZeroExtend32(fps);T ← Bit(t);
267PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if either input is a NaN.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
Invalid operations are indicated by light shading and raise an exception if enabled.FPU disabled cases are not shown.
The behavior of the normal ‘CMPGT’ case is described by the IEEE754 specification.
op2 →↓ op1
+NORM,-NORM
+0 -0 +INF -INF +DNORM,-DNORM
qNaN sNaN
+,-NORM CMPGT CMPGT CMPGT true false CMPGT false false
+0 CMPGT false false true false CMPGT false false
-0 CMPGT true false true false CMPGT false false
+INF false false false false false false false false
-INF true true true true false true false false
+, -DNORM CMPGT CMPGT CMPGT true false CMPGT false false
qNaN false false false false false false false false
sNaN false false false false false false false false
268PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FCNVDS DRm, FPULDescription
This floating-point instruction performs a double-precision to single-precisionfloating-point conversion. It reads a double-precision value from DRm, converts it tosingle-precision and places the result in FPUL. The rounding mode is determined byFPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FCNVDS DRm, FPUL
1111 m 010111101
15 12 11 9 8 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;fpul, fps ← FCNV_DS(op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FPSCR ← ZeroExtend32(fps);FPUL ← ZeroExtend32(fpul);
269PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FCNVSD FPUL, DRnDescription
This floating-point instruction performs a single-precision to double-precisionfloating-point conversion. It reads a single-precision value from FPUL, converts it todouble-precision and places the result in DRn. FPSCR.RM has no effect since theconversion is exact.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FCNVSD FPUL, DRn
1111 n 010101101
15 12 11 9 8 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);fpul ← SignExtend32(FPUL);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1, fps ← FCNV_SD(fpul, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;DR2n ← FloatRegister64(op1);FPSCR ← ZeroExtend32(fps);
270PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FCNVDS and FCNVSD Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if the input is a signaling NaN.
3 Error: an FPU error is signaled if FPSCR.DN is zero and the input is a denor-malized number.
4 Inexact, underflow and overflow: these are checked together and can be signaledin combination. These cases occur for FCNVDS but not for FCNVSD. When inex-act, underflow or overflow exceptions are requested by the user, an exception isalways raised for FCNVDS regardless of whether that condition arose.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
FPU error is indicated by heavy shading and always raises an exception. Invalidoperations are indicated by light shading and raise an exception if enabled. FPUdisabled, inexact, underflow and overflow cases are not shown.
The behavior of the normal ‘CNV’ case is described by the IEEE754 specification.
op1 → +NORM -NORM +0 -0 +INF -INF +DNORM,-DNORM
qNaN sNaN
CNV CNV +0 -0 +INF -INF n/a qNaN qNaN
271PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FDIV DRm, DRnDescription
This floating-point instruction performs a double-precision floating-point division. Itdivides DRn by DRm and places the result in DRn. The rounding mode is determinedby FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FDIV DRm, DRn
1111 n 0 m 00011
15 12 11 9 8 7 5 4 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);op2 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FDIV_D(op2, op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuEnableZ(fps) AND FpuCauseZ(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;DR2n ← FloatRegister64(op2);FPSCR ← ZeroExtend32(fps);
272PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FDIV FRm, FRnDescription
This floating-point instruction performs a single-precision floating-point division. Itdivides FRn by FRm and places the result in FRn. The rounding mode is determinedby FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FDIV FRm, FRn
1111 n m 0011
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FDIV_S(op2, op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuEnableZ(fps) AND FpuCauseZ(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op2);FPSCR ← ZeroExtend32(fps);
273PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FDIV Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if either input is a signaling NaN, or ifthe division is of a zero by a zero, or of an infinity by an infinity.
3 Divide-by-zero: a divide-by-zero is signaled if the divisor is zero and the dividendis a finite non-zero number.
4 Error: an FPU error is signaled if FPSCR.DN is zero, neither input is a NaN andeither of the following conditions is true: the divisor is a denormalized number,or the dividend is a denormalized number and the divisor is not a zero.
5 Inexact, underflow and overflow: these are checked together and can be signaledin combination. When inexact, underflow or overflow exceptions are requestedby the user, an exception is always raised regardless of whether that conditionarose.
If the instruction does not raise an exception, a result is generated as follows:
FPU error is indicated by heavy shading and always raises an exception. Invalidoperations and divide-by-zero are indicated by light shading and raise an exceptionif enabled. FPU disabled, inexact, underflow and overflow cases are not shown.
op2 →↓ op1
+NORM,-NORM
+0 -0 +INF -INF +DNORM,-DNORM
qNaN sNaN
+,-NORM DIV +0, -0 -0, +0 +INF, -INF -INF, +INF n/a qNaN qNaN
+0 +INF, -INF qNaN qNaN +INF -INF +INF, -INF qNaN qNaN
-0 -INF, +INF qNaN qNaN -INF +INF -INF, +INF qNaN qNaN
+INF +0, -0 +0 -0 qNaN qNaN n/a qNaN qNaN
-INF -0, +0 -0 +0 qNaN qNaN n/a qNaN qNaN
+, -DNORM n/a n/a n/a n/a n/a n/a qNaN qNaN
qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
sNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
274PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
The behavior of the normal ‘DIV’ case is described by the IEEE754 specification.
275PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FIPR FVm, FVnDescription
This floating-point instruction computes dot-product of two vectors, FVm and FVn,and places the result in element 3 of FVn. Each vector contains four single-precisionfloating-point values. The dot-product is specified as:
FRn+3 =
This is an approximate computation. The specified error in the result value:
spec_error =
where
rm =
E = unbiased exponent value of the result
ez < -252
epm = max (ep0, ep1, ep2, ep3)
epi = pre-normalized exponent of the product FRm+i and FRn+i
eFRm+i = biased exponent value of FRm+i
eFRn+i = biased exponent value of FRn+i
epi =
FRm i+ FR
n i+×i 0=
3
∑
0 if epm ez=( )
2epm 24–
2E 24– rm+
+ if epm ez≠( )
0 if round to– nearest–( )1 if round to– zero–( )
ez if FRm i+ 0.0=( )OR FR
n i+ 0.0=( )( )
max eFRm i+ 1( , ) max eFR
n i+ 1( , ) 254–+ otherwise
276PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FIPR Special Cases:
FIPR is an approximate instruction. Denormalized numbers are supported:
• When FPSCR.DN is 0, denormalized numbers are treated as their denormalizedvalue in the FIPR.S calculation. This instruction never signals an FPU error.
• When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is appliedbefore exception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
FIPR FVm, FVn
1111 n m 11101101
15 12 11 10 9 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValueVector32(FV4m);op2 ← FloatValueVector32(FV4n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2[3], fps ← FIPR_S(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FV4n ← FloatRegisterVector32(op2);FPSCR ← ZeroExtend32(fps);
277PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if any of the following arise:
• Any of the inputs is a signaling NaN.
• Multiplication of a zero by an infinity.
• Addition of differently signed infinities where none of the inputs is a qNaN.
The multiplication is performed with sufficient precision to avoid overflow, andtherefore the multiplication of any two finite numbers does not produce aninfinity. The multiplication result will be an infinity only if there is amultiplication of an infinity with a normalized number, an infinity with adenormalized number or an infinity with an infinity.
The addition of differently signed infinities is detected if there is (at least) onepositive infinity and (at least) one negative infinity in the set of 4 multiplicationresults.
3 Inexact, underflow and overflow: these are checked together and can be signaledin combination. This is an approximate instruction and inexact is signaledexcept where special cases occur. Precise details of the approximate inner-prod-uct algorithm, including the detection of underflow and overflow cases, areimplementation dependent. When inexact, underflow or overflow exceptions arerequested by the user, an exception is always raised regardless of whether thatcondition arose.
If the instruction does not raise an exception, a result is generated according to thefollowing tables. Where the behavior is not a special case, the instruction computesan approximate result using an implementation-dependent algorithm.
278PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FIPR Special Cases (continued):
Each of the 4 pairs of multiplication operands (op1 and op2) is selected fromcorresponding elements of the two 4-element source vectors and multiplied:
If any of the multiplications evaluates to qNaN, then the result of the instruction isqNaN and no further analysis need be performed. In the ‘FIPRMUL’, +0, -0, +INFand -INF cases, the 4 addition operands (labelled intermediate 0 to 3) are summed:
Inexact is signaled in the ‘FIPRADD’ case. Invalid operations are indicated by lightshading and raise an exception if enabled. FPU disabled, inexact, underflow andoverflow cases are not shown.
op1 →↓ op2
+,-NORM,+,-DENORM
+0 -0 +INF -INF qNaN sNaN
+,-NORM +,-DENORM FIPRMUL +0, -0 -0, +0 +INF, -INF -INF, +INF qNaN qNaN
+0 +0, -0 +0 -0 qNaN qNaN qNaN qNaN
-0 -0, +0 -0 +0 qNaN qNaN qNaN qNaN
+INF +INF, -INF qNaN qNaN +INF -INF qNaN qNaN
-INF -INF, +INF qNaN qNaN -INF +INF qNaN qNaN
qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
sNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
intermediate 0 → FIPRMUL, +0, -0 +INF -INF
↓ intermediate 2
intermediate 1→
↓ intermediate 3
FIPRMUL,+0, -0
+INF -INF FIPRMUL,+0, -0
+INF -INF FIPRMUL,+0, -0
+INF -INF
FIPRMUL,+0, -0
FIPRMUL, +0, -0 FIPRADD +INF -INF +INF +INF qNaN -INF qNaN -INF
+INF +INF +INF qNaN +INF +INF qNaN qNaN qNaN qNaN
-INF -INF qNaN -INF qNaN qNaN qNaN -INF qNaN -INF
+INF FIPRMUL, +0, -0 +INF +INF qNaN +INF +INF qNaN qNaN qNaN qNaN
+INF +INF +INF qNaN +INF +INF qNaN qNaN qNaN qNaN
-INF qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
-INF FIPRMUL, +0, -0 -INF qNaN -INF qNaN qNaN qNaN -INF qNaN -INF
+INF qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
-INF -INF qNaN -INF qNaN qNaN qNaN -INF qNaN -INF
279PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FLDS FRm, FPULDescription
This floating-point instruction copies FRm to FPUL.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FLDS FRm, FPUL
1111 m 00011101
15 12 11 8 7 0
sr ← ZeroExtend32(SR);op1 ← FloatValue32(FRm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;fpul ← op1;FPUL ← ZeroExtend32(fpul);
280PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FLDI0 FRnDescription
This floating-point instruction loads a constant representing the single-precisionfloating-point value of 0.0 into FRn.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FLDI0 FRn
1111 n 10001101
15 12 11 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← 0x00000000;FRn ← FloatRegister32(op1);
281PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FLDI1 FRnDescription
This floating-point instruction loads a constant representing the single-precisionfloating-point value of 1.0 into FRn.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FLDI1 FRn
1111 n 10011101
15 12 11 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← 0x3F800000;FRn ← FloatRegister32(op1);
282PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FLOAT FPUL, DRnDescription
This floating-point instruction performs a signed 32-bit integer to double-precisionfloating-point conversion. It reads a signed 32-bit integer value from FPUL,converts it to a double-precision range and places the result in DRn. In all cases theprovided integer value will be exactly represented in the destination floating-pointformat. FPSCR.RM has no effect since the conversion is exact.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FLOAT FPUL, DRn
1111 n 000101101
15 12 11 9 8 0
Available only when PR=1 and SZ=0
fpul ← SignExtend32(FPUL);sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1, fps ← FLOAT_LD(fpul, fps);DR2n ← FloatRegister64(op1);
283PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FLOAT FPUL, FRnDescription
This floating-point instruction performs a signed 32-bit integer to single-precisionfloating-point conversion. It reads a signed 32-bit integer value from FPUL,converts it to a single-precision range and places the result in FRn. In cases wherethe integer value cannot be exactly represented in the destination floating-pointformat, the rounding mode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FLOAT Special Cases:
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
FLOAT FPUL, FRn
1111 n 00101101
15 12 11 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);fpul ← SignExtend32(FPUL);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1, fps ← FLOAT_LS(fpul, fps);IF (FpuEnableI(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op1);FPSCR ← ZeroExtend32(fps);
284PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
1 Disabled: an exception is raised if the FPU is disabled.
2 Inexact: inexact can occur for FLOAT FPUL, FRn but not for FLOAT FPUL,DRn. When inexact exceptions are requested by the user, an exception is alwaysraised for FLOAT FPUL, FRn regardless of whether that condition arose. Over-flow and underflow do not occur for either of these instructions.
If the instruction does not raise an exception, the conversion is performed asindicated by the IEEE754 specification.
285PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMAC FR0, FRm, FRnDescription
This floating-point instruction performs a single-precision floating-pointmultiply-accumulate. It multiplies FR0 by FRm, adds this intermediate to FRn andplaces the result back to FRn. The multiplication and addition are performed as ifthe exponent and precision ranges were unbounded, followed by one rounding downto single-precision format. The rounding mode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FMAC FR0, FRm, FRn
1111 n m 1110
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);fr0 ← FloatValue32(FR0);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FMAC_S(fr0, op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op2);FPSCR ← ZeroExtend32(fps);
286PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMAC Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if any of the three inputs is a signalingNaN, there is a multiplication of a zero by an infinity, or there is an addition ofdifferently signed infinities.
The multiplication is performed with sufficient precision to avoid overflow, andtherefore the multiplication of any two finite numbers does not produce aninfinity. The multiplication result will be an infinity only if there is amultiplication of an infinity with a normalized number, an infinity with adenormalized number or an infinity with an infinity.
3 Error: an FPU error is signaled if FPSCR.DN is 0 and none of the inputs are aNaN and at least one of the inputs is a denormalized number.
4 Inexact, underflow and overflow: these are checked together and can be signaledin combination. The multiply-accumulate is implemented using a fused-macalgorithm, and these are detected during the conversion of the exactly evaluatedintermediate to the single-precision result. When inexact, underflow or overflowexceptions are requested by the user, an exception is always raised regardless ofwhether that condition arose.
If the instruction does not raise an exception, a result is generated according to thefollowing tables.
Firstly, the operands are checked for sNaN:
fr0 → other sNaN
op1 →↓ op2
other sNaN other sNaN
other qNaN qNaN qNaN
sNaN qNaN qNaN qNaN qNaN
287PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMAC Special Cases (continued):
If the result of the previous table is a qNaN, no further analysis is performed. In allother cases, fr0 and op1 are checked for a zero multiplied by an infinity:
If the result of the previous table is a qNaN, no further analysis is performed. In allother cases, the operands are checked for input qNaN values:
By this stage all operations involving sNaN or qNan operands have been dealt with.If the result of the previous table is a qNaN, no further analysis is performed. In allother cases, the operands are checked for the addition of differently signedinfinities:
fr0 →↓ op1
other +0 -0 +INF -INF
other
+0 qNaN qNaN
-0 qNaN qNaN
+INF qNaN qNaN
-INF qNaN qNaN
fr0 → other qNaN
op1 →↓ op2
other qNaN other qNaN
other qNaN qNaN qNaN
qNaN qNaN qNaN qNaN qNaN
fr0 → +other -other +INF -INF
op1 →↓ op2 +o
ther
-oth
er
+IN
F
-INF
+oth
er
-oth
er
+IN
F
-INF
+oth
er
-oth
er
+IN
F
-INF
+oth
er
-oth
er
+IN
F
-INF
+other
-other
+INF
qNaN
qNaN
qNaN
qNaN
qNaN
qNaN
-INF
qNaN
qNaN
qNaN
qNaN
qNaN
qNaN
288PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMAC Special Cases (continued):
If the result of the previous table is a qNaN, no further analysis is performed. In allother cases, fr0 and op1 are multiplied:
The empty cells in this table correspond to cases that have already been dealt with.If either source is denormalized, no further analysis is performed. In the‘FULLMUL’ case, a multiplication is performed without loss of precision. There isno rounding nor overflow, and this multiplication cannot produce an intermediateinfinity.
In the ‘FULLMUL’, +0, -0, +INF and -INF cases, the 2 addition operands (fr0*op1and op2) are summed:
The two empty cells in this table correspond to cases that have already been dealtwith. In the ‘FULLADD’ cases the fully-precise addition intermediate is rounded togive a single-precision result.
fr0 →↓ op1
+NORM,-NORM
+0 -0 +INF -INF +DNORM,-DNORM
+,-NORM FULLMUL +0, -0 -0, +0 +INF, -INF -INF, +INF n/a
+0 +0, -0 +0 -0 n/a
-0 -0, +0 -0 +0 n/a
+INF +INF, -INF +INF -INF n/a
-INF -INF, +INF -INF +INF n/a
+, -DNORM n/a n/a n/a n/a n/a n/a
(fr0*op1)→↓ op2
FULLMUL +0 -0 +INF -INF
+,-NORM FULLADD op2 op2 +INF -INF
+0 FULLADD +0 +0 +INF -INF
-0 FULLADD +0 -0 +INF -INF
+INF +INF +INF +INF +INF
-INF -INF -INF -INF -INF
+, -DNORM n/a n/a n/a n/a n/a
289PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
In the above tables, FPU error is indicated by heavy shading and always raises anexception. Invalid operations are indicated by light shading and raise an exception ifenabled. FPU disabled, inexact, underflow and overflow cases are not shown.
290PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV DRm, DRnDescription
This floating-point instruction reads a pair of single-precision floating-point valuesfrom DRm and copies them to DRn. This is a bit-by-bit copy with no interpretation orconversion of the values.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FMOV DRm, DRn
1111 n 0 m 01100
15 12 11 9 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);op1 ← FloatValuePair32(FP2m);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2 ← op1;FP2n ← FloatRegisterPair32(op2);
291PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV DRm, XDnDescription
This floating-point instruction reads a pair of single-precision floating-point valuesfrom DRm and copies them to XDn. This is a bit-by-bit copy with no interpretation orconversion of the values.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FMOV DRm, XDn
1111 n 1 m 01100
15 12 11 9 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);op1 ← FloatValuePair32(DR2m);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2 ← op1;XD2n ← FloatRegisterPair32(op2);
292PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV DRm, @RnDescription
This floating-point instruction stores a pair of single-precision floating-pointregisters to memory using register indirect with zero-displacement addressing. DRmis written as two consecutive 32-bit values to the effective address specified in Rn
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
FMOV DRm, @Rn
1111 n m 01010
15 12 11 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValuePair32(FP2m);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op2);WriteMemoryPair32(address, op1);
293PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV DRm, @-RnDescription
This floating-point instruction stores a pair of single-precision floating-pointregisters to memory using register indirect with pre-decrement addressing. Rn ispre-decremented by 8 to give the effective address. DRm is written as twoconsecutive 32-bit values to the effective address.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
FMOV DRm, @-Rn
1111 n m 01011
15 12 11 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValuePair32(FP2m);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op2 - 8);WriteMemoryPair32(address, op1);op2 ← address;Rn ← Register(op2);
294PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
295PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV DRm, @(R0, Rn)Description
This floating-point instruction stores a pair of single-precision floating-pointregisters to memory using register indirect addressing. The effective address isformed by adding R0 to Rn. DRm is written as two consecutive 32-bit values to theeffective address.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
FMOV DRm, @(R0, Rn)
1111 n m 00111
15 12 11 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);r0 ← SignExtend32(R0);op1 ← FloatValuePair32(FP2m);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(r0 + op2);WriteMemoryPair32(address, op1);
296PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV.S FRm, FRnDescription
This floating-point instruction reads a single-precision floating-point value fromFRm and copies it to FRn. This is a bit-by-bit copy with no interpretation orconversion of the value.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FMOV.S FRm, FRn
1111 n m 1100
15 12 11 8 7 4 3 0
Available only when SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2 ← op1;FRn ← FloatRegister32(op2);
297PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV.S FRm, @RnDescription
This floating-point instruction stores a single-precision floating-point register tomemory using register indirect with zero-displacement addressing. The 32-bit valueof FRm is written to the effective address specified in Rn
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
FMOV.S FRm, @Rn
1111 n m 1010
15 12 11 8 7 4 3 0
Available only when SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op2);WriteMemory32(address, op1);
298PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV.S FRm, @-RnDescription
This floating-point instruction stores a single-precision floating-point register tomemory using register indirect with pre-decrement addressing. Rn ispre-decremented by 4 to give the effective address. The 32-bit value of FRm iswritten to the effective address.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
FMOV.S FRm, @-Rn
1111 n m 1011
15 12 11 8 7 4 3 0
Available only when SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op2 - 4);WriteMemory32(address, op1);op2 ← address;Rn ← Register(op2);
299PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
300PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV.S FRm, @(R0, Rn)Description
This floating-point instruction stores a single-precision floating-point register tomemory using register indirect addressing. The effective address is formed byadding R0 to Rn. The 32-bit value of FRm is written to the effective address.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
FMOV.S FRm, @(R0, Rn)
1111 n m 0111
15 12 11 8 7 4 3 0
Available only when SZ=0
sr ← ZeroExtend32(SR);r0 ← SignExtend32(R0);op1 ← FloatValue32(FRm);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(r0 + op2);WriteMemory32(address, op1);
301PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV XDm, DRnDescription
This floating-point instruction reads a pair of single-precision floating-point valuesfrom XDm and copies them to DRn. This is a bit-by-bit copy with no interpretation orconversion of the values.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FMOV XDm, DRn
1111 n 0 m 11100
15 12 11 9 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValuePair32(XD2m);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2 ← op1;DR2n ← FloatRegisterPair32(op2);
302PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV XDm, XDnDescription
This floating-point instruction reads a pair of single-precision floating-point valuesfrom XDm and copies them to XDn. This is a bit-by-bit copy with no interpretation orconversion of the values.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FMOV XDm, XDn
1111 n 1 m 11100
15 12 11 9 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(XD2m);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2 ← op1;XD2n ← FloatRegister64(op2);
303PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV XDm, @RnDescription
This floating-point instruction stores a pair of single-precision floating-pointregisters to memory using register indirect with zero-displacement addressing. XDmis written as two consecutive 32-bit values to the effective address specified in Rn
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
FMOV XDm, @Rn
1111 n m 11010
15 12 11 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValuePair32(XD2m);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op2);WriteMemoryPair32(address, op1);
304PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV XDm, @-RnDescription
This floating-point instruction stores a pair of single-precision floating-pointregisters to memory using register indirect with pre-decrement addressing. Rn ispre-decremented by 8 to give the effective address. XDm is written as twoconsecutive 32-bit values to the effective address.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
FMOV XDm, @-Rn
1111 n m 11011
15 12 11 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValuePair32(XD2m);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op2 - 8);WriteMemoryPair32(address, op1);op2 ← address;Rn ← Register(op2);FPSCR ← ZeroExtend32(fps);
305PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
306PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV XDm, @(R0, Rn)Description
This floating-point instruction stores a pair of single-precision floating-pointregisters to memory using register indirect addressing. The effective address isformed by adding R0 to Rn. XDm is written as two consecutive 32-bit values to theeffective address.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
FMOV XDm, @(R0, Rn)
1111 n m 10111
15 12 11 8 7 5 4 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);r0 ← SignExtend32(R0);op1 ← FloatValuePair32(XD2m);op2 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(r0 + op2);WriteMemoryPair32(address, op1);
307PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV @Rm, DRnDescription
This floating-point instruction loads a pair of single-precision floating-pointregisters from memory using register indirect with zero-displacement addressing.Two consecutive 32-bit values are read from the effective address specified in Rmand loaded into DRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
FMOV @Rm, DRn
1111 n 0 m 1000
15 12 11 9 8 7 4 3 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);op2 ← ReadMemoryPair32(address);FP2n ← FloatRegisterPair32(op2);
308PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV @Rm+, DRnDescription
This floating-point instruction loads a pair of single-precision floating-pointregisters from memory using register indirect with post-increment addressing. Twoconsecutive 32-bit values are read from the effective address specified in Rm andloaded into DRn. Rm is post-incremented by 8.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
FMOV @Rm+, DRn
1111 n 0 m 1001
15 12 11 9 8 7 4 3 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);op2 ← ReadMemoryPair32(address);op1 ← op1 + 8;Rm ← Register(op1);FP2n ← FloatRegisterPair32(op2);
309PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV @(R0, Rm), DRnDescription
This floating-point instruction loads a pair of single-precision floating-pointregisters from memory using register indirect addressing. The effective address isformed by adding R0 to Rn. Two consecutive 32-bit values are read from the effectiveaddress and loaded into DRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
FMOV @(R0, Rm), DRn
1111 n 0 m 0110
15 12 11 9 8 7 4 3 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(r0 + op1);op2 ← ReadMemoryPair32(address);FP2n ← FloatRegisterPair32(op2);
310PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV.S @Rm, FRnDescription
This floating-point instruction loads a single-precision floating-point register frommemory using register indirect with zero-displacement addressing. A 32-bit value isread from the effective address specified in Rm and loaded into FRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
FMOV.S @Rm, FRn
1111 n m 1000
15 12 11 8 7 4 3 0
Available only when SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);op2 ← ReadMemory32(address);FR2n ← FloatRegister32(op2);
311PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV.S @Rm+, FRnDescription
This floating-point instruction loads a single-precision floating-point register frommemory using register indirect with post-increment addressing. A 32-bit value isread from the effective address specified in Rm and loaded into FRn. Rm ispost-incremented by 4.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
FMOV.S @Rm+, FRn
1111 n m 1001
15 12 11 8 7 4 3 0
Available only when SZ=0
sr ← ZeroExtend32(SR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);op2 ← ReadMemory32(address);op1 ← op1 + 4;Rm ← Register(op1);FRn ← FloatRegister32(op2);
312PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV.S @(R0, Rm), FRnDescription
This floating-point instruction loads a single-precision floating-point register frommemory using register indirect addressing. The effective address is formed byadding R0 to Rn. A 32-bit value is read from the effective address and loaded intoFRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
FMOV.S @(R0, Rm), FRn
1111 n m 0110
15 12 11 8 7 4 3 0
Available only when SZ=0
sr ← ZeroExtend32(SR);r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(r0 + op1);op2 ← ReadMemory32(address);FRn ← FloatRegister32(op2);
313PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV @Rm, XDnDescription
This floating-point instruction loads a pair of single-precision floating-pointregisters from memory using register indirect with zero-displacement addressing.Two consecutive 32-bit values are read from the effective address specified in Rmand loaded into XDn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
FMOV @Rm, XDn
1111 n 1 m 1000
15 12 11 9 8 7 4 3 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);op2 ← ReadMemoryPair32(address);XD2n ← FloatRegisterPair32(op2);
314PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV @Rm+, XDnDescription
This floating-point instruction loads a pair of single-precision floating-pointregisters from memory using register indirect with post-increment addressing. Twoconsecutive 32-bit values are read from the effective address specified in Rm andloaded into XDn. Rm is post-incremented by 8.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
FMOV @Rm+, XDn
1111 n 1 m 1001
15 12 11 9 8 7 4 3 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);op2 ← ReadMemoryPair32(address);op1 ← op1 + 8;Rm ← Register(op1);XD2n ← FloatRegisterPair32(op2);
315PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMOV @(R0, Rm), XDnDescription
This floating-point instruction loads a pair of single-precision floating-pointregisters from memory using register indirect addressing. The effective address isformed by adding R0 to Rn. Two consecutive 32-bit values are read from the effectiveaddress and loaded into XDn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
FMOV @(R0, Rm), XDn
1111 n 1 m 0110
15 12 11 9 8 7 4 3 0
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(r0 + op1);op2 ← ReadMemoryPair32(address);XD2n ← FloatRegisterPair32(op2);
316PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMUL DRm, DRnDescription
This floating-point instruction performs a double-precision floating-pointmultiplication. It multiplies DRm by DRn and places the result in DRn. Therounding mode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FMUL DRm, DRn
1111 n 0 m 00010
15 12 11 9 8 7 5 4 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);op2 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FMUL_D(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;DR2n ← FloatRegister64(op2);FPSCR ← ZeroExtend32(fps);
317PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FMUL FRm, FRnDescription
This floating-point instruction performs a single-precision floating-pointmultiplication. It multiplies FRm by FRn and places the result in FRn. The roundingmode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FMUL FRm, FRn
1111 n m 0010
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FMUL_S(op1, op2, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op2);FPSCR ← ZeroExtend32(fps);
318PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMUL Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if either input is a signaling NaN, or ifthis is a multiplication of a zero by an infinity.
3 Error: an FPU error is signaled if FPSCR.DN is zero, neither input is a NaN andeither input is a denormalized number.
4 Inexact, underflow and overflow: these are checked together and can be signaledin combination. When inexact, underflow or overflow exceptions are requestedby the user, an exception is always raised regardless of whether that conditionarose.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
FPU error is indicated by heavy shading and always raises an exception. Invalidoperations are indicated by light shading and raise an exception if enabled. FPUdisabled, inexact, underflow and overflow cases are not shown.
The behavior of the normal ‘MUL’ case is described by the IEEE754 specification.
op1 →↓ op2
+NORM,-NORM
+0 -0 +INF -INF +DNORM,-DNORM
qNaN sNaN
+,-NORM MUL +0, -0 -0, +0 +INF, -INF -INF, +INF n/a qNaN qNaN
+0 +0, -0 +0 -0 qNaN qNaN n/a qNaN qNaN
-0 -0, +0 -0 +0 qNaN qNaN n/a qNaN qNaN
+INF +INF, -INF qNaN qNaN +INF -INF n/a qNaN qNaN
-INF -INF, +INF qNaN qNaN -INF +INF n/a qNaN qNaN
+, -DNORM n/a n/a n/a n/a n/a n/a qNaN qNaN
qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
sNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
319PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FNEG DRnDescription
This floating-point instruction computes the negated value of a double-precisionfloating-point number. It reads DRn, inverts the sign bit and places the result inDRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FNEG DRn
1111 n 001001101
15 12 11 9 8 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);op1 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← FNEG_D(op1);DR2n ← FloatRegister64(op1);
320PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FNEG FRnDescription
This floating-point instruction computes the negated value of a single-precisionfloating-point number. It FRn, inverts the sign bit and places the result in FRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations. There are no special floating-point cases for this instruction.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FNEG FRn
1111 n 01001101
15 12 11 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← FNEG_S(op1);FRn ← FloatRegister32(op1);
321PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FRCHGDescription
This floating-point instruction toggles the FPSCR.FR bit. This has the effect ofswitching the basic and extended banks of the floating-point register file.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FRCHG
1111101111111101
15 0
Available only when PR=0
sr ← ZeroExtend32(SR);fr ← ZeroExtend1(SR.FR);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;fr ← fr ⊕ 1;SR.FR ← Bit(fr);
322PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FSCHGDescription
This floating-point instruction toggles the FPSCR.SZ bit. This has the effect ofchanging the size of the data transfer for subsequent floating-point loads, stores andmoves. Two transfer sizes are available: FPSCR.SZ = 0 indicates 32-bit transfer andFPSCR.SZ = 1 indicates 64-bit transfer.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FSCHG
1111001111111101
15 0
Available only when PR=0
sr ← ZeroExtend32(SR);sz ← ZeroExtend1(SR.SZ);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;sz ← sz ⊕ 1;SR.SZ ← Bit(sz);
323PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FSQRT DRnDescription
This floating-point instruction performs a double-precision floating-point squareroot. It extracts the square root of DRn and places the result in DRn. The roundingmode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FSQRT DRn
1111 n 001101101
15 12 11 9 8 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1, fps ← FSQRT_D(op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF (FpuEnableI(fps))
THROW FPUEXC, fps;DR2n ← FloatRegister64(op1);FPSCR ← ZeroExtend32(fps);
324PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FSQRT FRnDescription
This floating-point instruction performs a single-precision floating-point squareroot. It extracts the square root of FRn and places the result in FRn. The roundingmode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FSQRT FRn
1111 n 01101101
15 12 11 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1, fps ← FSQRT_S(op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF (FpuEnableI(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op1);FPSCR ← ZeroExtend32(fps);
325PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FSQRT Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if the input is a signaling NaN, or if thisis a square root of a number less than zero (including negative infinity and nega-tive normalized/denormalized numbers, but excluding negative zero).
3 Error: an FPU error is signaled if FPSCR.DN is zero and the input is a positivedenormalized number.
4 Inexact: only inexact is checked. When inexact exceptions are requested by theuser, an exception is always raised regardless of whether that condition arose.Overflow and underflow do not occur.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
FPU error is indicated by heavy shading and always raises an exception. Invalidoperations are indicated by light shading and raise an exception if enabled. FPUdisabled and inexact cases are not shown.
The behavior of the normal ‘SQRT’ case is described by the IEEE754 specification.
op1 → +NORM -NORM +0 -0 +INF -INF +DNORM -DNORM qNaN sNaN
SQRT qNaN +0 -0 +INF qNaN n/a qNaN qNaN qNaN
326PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FSTS FPUL, FRnDescription
This floating-point instruction copies FPUL to FRn.
This instruction is not considered an arithmetic operation, and it does not signalinvalid operations.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
FSTS FPUL, FRn
1111 n 00001101
15 12 11 8 7 0
sr ← ZeroExtend32(SR);fpul ← SignExtend32(FPUL);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← fpul;FRn ← FloatRegister32(op1);
327PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FSUB DRm, DRnDescription
This floating-point instruction performs a double-precision floating-pointsubtraction. It subtracts DRm from DRn and places the result in DRn. The roundingmode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FSUB DRm, DRn
1111 n 0 m 00001
15 12 11 9 8 7 5 4 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);op2 ← FloatValue64(DR2n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FSUB_D(op2, op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;DR2n ← FloatRegister64(op2);FPSCR ← ZeroExtend32(fps);
328PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FSUB FRm, FRnDescription
This floating-point instruction performs a single-precision floating-pointsubtraction. It subtracts FRm from FRn and places the result in FRn. The roundingmode is determined by FPSCR.RM.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FSUB FRm, FRn
1111 n m 0001
15 12 11 8 7 4 3 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);op2 ← FloatValue32(FRn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op2, fps ← FSUB_S(op2, op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;IF (FpuCauseE(fps))
THROW FPUEXC, fps;IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FRn ← FloatRegister32(op2);FPSCR ← ZeroExtend32(fps);
329PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FSUB Special Cases:
When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is applied beforeexception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if either input is a signaling NaN, or ifthe inputs are similarly signed infinities.
3 Error: an FPU error is signaled if FPSCR.DN is zero, neither input is a NaN andeither input is a denormalized number.
4 Inexact, underflow and overflow: these are checked together and can be signaledin combination. When inexact, underflow or overflow exceptions are requestedby the user, an exception is always raised regardless of whether that conditionarose.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
FPU error is indicated by heavy shading and always raises an exception. Invalidoperations are indicated by light shading and raise an exception if enabled. FPUdisabled, inexact, underflow and overflow cases are not shown.
The behavior of the normal ‘SUB’ case is described by the IEEE754 specification.
op2 →↓ op1
+NORM,-NORM
+0 -0 +INF -INF +DNORM,-DNORM
qNaN sNaN
+,-NORM SUB SUB SUB +INF -INF n/a qNaN qNaN
+0 op2 +0 -0 +INF -INF n/a qNaN qNaN
-0 op2 +0 +0 +INF -INF n/a qNaN qNaN
+INF -INF -INF -INF qNaN -INF n/a qNaN qNaN
-INF +INF +INF +INF +INF qNaN n/a qNaN qNaN
+, -DNORM n/a n/a n/a n/a n/a n/a qNaN qNaN
qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
sNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
330PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FTRC DRm, FPULDescription
This floating-point instruction performs a double-precision floating-point to signed32-bit integer conversion. It reads a double-precision value from DRm, converts it toa signed 32-bit integral range and places the result in FPUL. The conversion isachieved by rounding to zero (truncation) with saturation to the limits of the targetsigned integral range. The value of FPSCR.RM is ignored.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FTRC DRm, FPUL
1111 m 000111101
15 12 11 9 8 0
Available only when PR=1 and SZ=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue64(DR2m);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;fpul, fps ← FTRC_DL(op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;FPUL ← ZeroExtend32(fpul);FPSCR ← ZeroExtend32(fps);
331PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FTRC FRm, FPULDescription
This floating-point instruction performs a single-precision floating-point to signed32-bit integer conversion. It reads a single-precision value from FRm, converts it to asigned 32-bit integral range and places the result in FPUL. The conversion isachieved by rounding to zero (truncation) with saturation to the limits of the targetsigned integral range. The value of FPSCR.RM is ignored.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FTRC Special Cases:
Regardless of FPSCR.DN, denormalized numbers are treated as 0. Theseinstructions do not cause FPU Error.
FTRC FRm, FPUL
1111 m 00111101
15 12 11 8 7 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← FloatValue32(FRm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;fpul, fps ← FTRC_SL(op1, fps);IF (FpuEnableV(fps) AND FpuCauseV(fps))
THROW FPUEXC, fps;FPSCR ← ZeroExtend32(fps);FPUL ← ZeroExtend32(fpul);
332PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if the conversion overflows the targetrange. This is caused by out-of-range normalized numbers, infinities and NaNs.
If the instruction does not raise an exception, a result is generated according to thefollowing table.
Invalid operations are indicated by light shading and raise an exception if enabled.FPU disabled cases are not shown.
The behavior of the normal ‘TRC’ case is described by the IEEE754 specification,though only the round to zero rounding mode is supported by this instruction.
op1 → +NORM
(in range)
-NORM
(in range)
+0 -0 +INF or
+NORM(out ofrange)
-INF or
-NORM(out ofrange)
+DNORM,-DNORM
qNaN sNaN
TRC TRC 0 0 +231 - 1 -231 0 -231 -231
333PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FTRV XMTRX, FVnDescription
This floating-point instruction multiplies the matrix, XMTRX, with a vector, FVn,and places the resulting vector in FVn. The matrix contains sixteen single-precisionfloating-point values. The vector contains four single-precision floating-pointvalues. The matrix-vector multiplication is specified as:
FRn =
FRn+1 =
FRn+2 =
FRn+3 =
This is an approximate computation. The specified error in the pth. element value ofthe result vector:
spec_errorp =
where
rm =
E = unbiased exponent value of the result
ez < -252
epm = max (ep0, ep1, ep2, ep3)
epi = pre-normalized exponent of the product XFp+ix4 and FRn+i
XFi 4× FR
n i+×i 0=
3
∑
XF1 i 4×+ FR
n i+×i 0=
3
∑
XF2 i 4×+ FR
n i+×i 0=
3
∑
XF3 i 4×+ FR
n i+×i 0=
3
∑
0 if epm ez=( )
2epm 24–
2E 24– rm+
+ if epm ez≠( )
0 if round to– nearest–( )1 if round to– zero–( )
334PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
eXFp+ix4 = biased exponent value of XFp+ix4
eFRn+i = biased exponent value of FRn+i
epi =
Operation
Exceptions
SLOTFPUDIS, FPUDIS, FPUEXC
FTRV Special Cases:
FTRV is an approximate instruction. Denormalized numbers are supported:
• When FPSCR.DN is 0, denormalized numbers are treated as their denormalizedvalue in the FTRV.S calculation. This instruction never signals an FPU error.
ez if XFp i 4×+ 0.0=( )OR FR
n i+ 0.0=( )( )
max eXFp i 4×+ 1( , ) max eFR
n i+ 1( , ) 254–+ otherwise
FTRV XMTRX, FVn
1111 n 0111111101
15 12 11 10 9 0
Available only when PR=0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);xmtrx ← FloatValueMatrix32(XMTRX);op1 ← FloatValueVector32(FV4n);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1, fps ← FTRV_S(xmtrx, op1, fps);IF (((FpuEnableV(fps) OR FpuEnableI(fps)) OR FpuEnableO(fps)) OR FpuEnableU(fps))
THROW FPUEXC, fps;FV4n ← FloatRegisterVector32(op1);FPSCR ← ZeroExtend32(fps);
335PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
• When FPSCR.DN is 1, a positive denormalized number is treated as +0 and anegative denormalized number as -0. This flush-to-zero treatment is appliedbefore exception detection and special case handling.
Exceptional conditions are checked in the order given below. Execution of theinstruction is terminated once any check detects an exceptional condition.
1 Disabled: an exception is raised if the FPU is disabled.
2 Invalid: an invalid operation is signaled if any of the inputs is a signaling NaN,there is a multiplication of a zero by an infinity, or there is an addition of differ-ently signed infinities where none of the inputs is a qNaN.
The multiplication is performed with sufficient precision to avoid overflow, andtherefore the multiplication of any two finite numbers does not produce aninfinity. The multiplication result will be an infinity only if there is amultiplication of an infinity with a normalized number, an infinity with adenormalized number or an infinity with an infinity.
The addition of differently signed infinities is detected if there is (at least) onepositive infinity and (at least) one negative infinity in the set of 4 multiplicationresults in any of the 4 inner-products calculated by this instruction.
This instruction is not capable of checking its inputs for invalid operations andraising an invalid operation exception accordingly. Instead, this instructionalways raises an invalid operation exception if this exception is requested by theuser. If this exception is not requested by the user, then qNaN results arecorrectly produced for invalid operations as described above.
3 Inexact, underflow and overflow: these are checked together and can be signaledin combination. This is an approximate instruction and inexact is signaledexcept where special cases occur. Precise details of the approximate inner-prod-uct algorithm, including the detection of underflow and overflow cases, areimplementation dependent. When inexact, underflow or overflow exceptions arerequested by the user, an exception is always raised regardless of whether thatcondition arose.
If the instruction does not raise an exception, results are generated according to thefollowing tables. The special case tables are applied separately with the appropriatevector operands to each of the four inner-products calculated by this instruction.
336PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FTRV Special Cases (continued):
Each of the 4 pairs of multiplication operands (op1 and op2) is selected fromcorresponding elements of the two 4-element source vectors and multiplied:
If any of the multiplications evaluates to qNaN, then the result of the instruction isqNaN and no further analysis need be performed. In the ‘FTRVMUL’, +0, -0, +INFand -INF cases, the 4 addition operands (labelled intermediate 0 to 3) are summed:
Inexact is signaled in the ‘FTRVADD’ case. Exception cases are not indicated byshading for this instruction. Where the behavior is not a special case, the instructioncomputes an approximate result using an implementation-dependent algorithm.
op1 →↓ op2
+,-NORM,+,-DENORM
+0 -0 +INF -INF qNaN sNaN
+,-NORM +,-DENORM FTRVMUL +0, -0 -0, +0 +INF, -INF -INF, +INF qNaN qNaN
+0 +0, -0 +0 -0 qNaN qNaN qNaN qNaN
-0 -0, +0 -0 +0 qNaN qNaN qNaN qNaN
+INF +INF, -INF qNaN qNaN +INF -INF qNaN qNaN
-INF -INF, +INF qNaN qNaN -INF +INF qNaN qNaN
qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
sNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
intermediate 0 → FTRVMUL, +0, -0 +INF -INF
↓ intermediate 2
intermediate 1→
↓ intermediate 3
FTRVMUL,+0, -0
+INF -INF FTRVMUL,+0, -0
+INF -INF FTRVMUL,+0, -0
+INF -INF
FTRVMUL,+0, -0
FTRVMUL, +0, -0 FTRVADD +INF -INF +INF +INF qNaN -INF qNaN -INF
+INF +INF +INF qNaN +INF +INF qNaN qNaN qNaN qNaN
-INF -INF qNaN -INF qNaN qNaN qNaN -INF qNaN -INF
+INF FTRVMUL, +0, -0 +INF +INF qNaN +INF +INF qNaN qNaN qNaN qNaN
+INF +INF +INF qNaN +INF +INF qNaN qNaN qNaN qNaN
-INF qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
-INF FTRVMUL, +0, -0 -INF qNaN -INF qNaN qNaN qNaN -INF qNaN -INF
+INF qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN qNaN
-INF -INF qNaN -INF qNaN qNaN qNaN -INF qNaN -INF
337PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
JMP @RnDescription
This instruction is a delayed unconditional branch used for jumping to the targetaddress specified in Rn.
Operation
Exceptions
ILLSLOT
Note
The delay slot is executed before branching. An ILLSLOT exception is raised if thisinstruction is executed in a delay slot.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
JMP @Rn
0100 n 00101011
15 12 11 8 7 0
op1 ← SignExtend32(Rn);IF (IsDelaySlot())
THROW ILLSLOT;target ← op1;delayedpc ← target ∧ (~ 0x1);PC’’ ← Register(delayedpc);
338PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
JSR @RnDescription
This instruction is a delayed unconditional branch used for jumping to thesubroutine starting at the target address specified in Rn. The address of theinstruction immediately following the delay slot is copied to PR to indicate thereturn address.
Operation
Exceptions
ILLSLOT
Note
The delay slot is executed before branching and before PR is updated. An ILLSLOTexception is raised if this instruction is executed in a delay slot.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
JSR @Rn
0100 n 00001011
15 12 11 8 7 0
pc ← SignExtend32(PC);op1 ← SignExtend32(Rn);IF (IsDelaySlot())
THROW ILLSLOT;delayedpr ← pc + 4;target ← op1;delayedpc ← target ∧ (~ 0x1);PR’’ ← Register(delayedpr);PC’’ ← Register(delayedpc);
339PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDC Rm, GBRDescription
This instruction copies Rm to GBR.
Operation
Note
LDC Rm, GBR
0100 m 00011110
15 12 11 8 7 0
op1 ← SignExtend32(Rm);gbr ← op1;GBR ← Register(gbr);
340PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDC Rm, SRDescription
This instruction copies Rm to SR, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
LDC Rm, SR
0100 m 00001110
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);sr ← op1;SR ← Register(sr);
341PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDC Rm, VBRDescription
This instruction copies Rm to VBR, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
LDC Rm, VBR
0100 m 00101110
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);vbr← op1;VBR ← Register(vbr);
342PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDC Rm, SSRDescription
This instruction copies Rm to SSR, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
LDC Rm, SSR
0100 m 00111110
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);ssr ← op1;SSR ← Register(ssr);
343PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDC Rm, SPCDescription
This instruction copies Rm to SPC, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
LDC Rm, SPC
0100 m 01001110
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);spc ← op1;SPC ← Register(spc);
344PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDC Rm, DBRDescription
This instruction copies Rm to DBR, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
LDC Rm, SPC
0100 m 11111010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);dbr← op1;DBR ← Register(dbr);
345PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDC Rm, Rn_BANKDescription
This instruction copies Rm to Rn_BANK, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
LDC Rm, Rn_BANK
0100 m 1 n 1110
15 12 11 8 7 6 4 3 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);rn_bank← op1;Rn_BANK ← Register(rn_bank);
346PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDC.L @Rm+, GBRDescription
This instruction loads GBR from memory using register indirect withpost-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into GBR. Rm is post-incremented by 4.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
LDC.L @Rm+, GBR
0100 m 00010111
15 12 11 8 7 0
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);gbr ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);GBR ← Register(gbr);
347PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDC.L @Rm+, SRDescription
This instruction loads SR from memory using register indirect with post-incrementaddressing. A 32-bit value is read from the effective address specified in Rm andloaded into SR. Rm is post-incremented by 4. This is a privileged instruction.
Operation
Exceptions
RESINST, RADDERR, RTLBMISS, READPROT
Note
LDC.L @Rm+, SR
0100 m 00000111
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);sr ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);SR ← Register(sr);
348PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDC.L @Rm+, VBRDescription
This instruction loads VBR from memory using register indirect withpost-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into VBR. Rm is post-incremented by 4. This is aprivileged instruction.
Operation
Exceptions
RESINST, RADDERR, RTLBMISS, READPROT
Note
LDC.L @Rm+, VBR
0100 m 00100111
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);vbr ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);VBR ← Register(vbr);
349PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDC.L @Rm+, SSRDescription
This instruction loads SSR from memory using register indirect withpost-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into SSR. Rm is post-incremented by 4. This is aprivileged instruction.
Operation
Exceptions
RESINST, RADDERR, RTLBMISS, READPROT
Note
LDC.L @Rm+, SR
0100 m 00110111
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);ssr ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);SSR ← Register(ssr);
350PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDC.L @Rm+, SPCDescription
This instruction loads SPC from memory using register indirect withpost-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into SPC. Rm is post-incremented by 4. This is aprivileged instruction.
Operation
Exceptions
RESINST, RADDERR, RTLBMISS, READPROT
Note
LDC.L @Rm+, SPC
0100 m 01000111
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);spc ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);SPC ← Register(spc);
351PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDC.L @Rm+, DBRDescription
This instruction loads SR from memory using register indirect with post-incrementaddressing. A 32-bit value is read from the effective address specified in Rm andloaded into DBR. Rm is post-incremented by 4. This is a privileged instruction.
Operation
Exceptions
RESINST, RADDERR, RTLBMISS, READPROT
Note
LDC.L @Rm+, DBR
0100 m 11110110
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);dbr ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);DBR ← Register(dbr);
352PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDC.L @Rm+, Rn_BANKDescription
This instruction loads Rn_BANK from memory using register indirect withpost-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into Rn_BANK. Rm is post-incremented by 4. This is aprivileged instruction.
Operation
Exceptions
RESINST, RADDERR, RTLBMISS, READPROT
Note
LDC.L @Rm+, Rn_BANK
0100 m 1 n 0111
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);rn_bank ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);Rn_BANK ← Register(rn_bank);
353PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDS Rm, FPSCRDescription
This floating-point instruction copies Rm to FPSCR. The setting of FPSCR does notcause any floating-point exceptional conditions to be signaled.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
Note
LDS Rm, FPSCR
0100 m 01101010
15 12 11 8 7 0
sr ← ZeroExtend32(SR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;fps, pr, sz, fr ← UnpackFPSCR(op1);FPSCR ← ZeroExtend32(fps);SR.PR ← Bit(pr);SR.SZ ← Bit(sz);SR.FR ← Bit(fr);
354PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDS.L @Rm+, FPSCRDescription
This floating-point instruction loads FPSCR from memory using register indirectwith post-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into FPSCR. Rm is post-incremented by 4. The setting ofFPSCR does not cause any floating-point exceptional conditions to be signaled.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
LDS.L @Rm+, FPSCR
0100 m 01100110
15 12 11 8 7 0
sr ← ZeroExtend32(SR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);value ← ReadMemory32(address);fps, pr, sz, fr ← UnpackFPSCR(value);op1 ← op1 + 4;Rm ← Register(op1);FPSCR ← ZeroExtend32(fps);SR.PR ← Bit(pr);SR.SZ ← Bit(sz);SR.FR ← Bit(fr);
355PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDS Rm, FPULDescription
This floating-point instruction copies Rm to FPUL.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
Note
LDS Rm, FPUL
0100 m 01011010
15 12 11 8 7 0
sr ← ZeroExtend32(SR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;fpul ← op1;FPUL ← ZeroExtend32(fpul);
356PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDS.L @Rm+, FPULDescription
This floating-point instruction loads FPUL from memory using register indirectwith post-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into FPUL. Rm is post-incremented by 4.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, RADDERR, RTLBMISS, READPROT
Note
LDS.L @Rm+, FPUL
0100 m 01010110
15 12 11 8 7 0
sr ← ZeroExtend32(SR);op1 ← SignExtend32(Rm);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1);fpul ← ReadMemory32(address);op1 ← op1 + 4;Rm ← Register(op1);FPUL ← ZeroExtend32(fpul);
357PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDS Rm, MACHDescription
This instruction copies Rm to MACH.
Operation
Note
LDS Rm, MACH
0100 m 00001010
15 12 11 8 7 0
op1 ← SignExtend32(Rm);mach ← op1;MACH ← ZeroExtend32(mach);
358PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDS.L @Rm+, MACHDescription
This instruction loads MACH from memory using register indirect withpost-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into MACH. Rm is post-incremented by 4.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
LDS.L @Rm+, MACH
0100 m 00000110
15 12 11 8 7 0
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);mach ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);MACH ← ZeroExtend32(mach);
359PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDS Rm, MACLDescription
This instruction copies Rm to MACL.
Operation
Note
LDS Rm, MACL
0100 m 00011010
15 12 11 8 7 0
op1 ← SignExtend32(Rm);macl ← op1;MACL ← ZeroExtend32(macl);
360PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDS.L @Rm+, MACLDescription
This instruction loads MACL from memory using register indirect withpost-increment addressing. A 32-bit value is read from the effective addressspecified in Rm and loaded into MACL. Rm is post-incremented by 4.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
LDS.L @Rm+, MACL
0100 m 00010110
15 12 11 8 7 0
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);macl ← SignExtend32(ReadMemory32(address));op1 ← op1 + 4;Rm ← Register(op1);MACL ← ZeroExtend32(macl);
361PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDS Rm, PRDescription
This instruction copies Rm to PR.
Operation
Note
LDS Rm, PR
0100 m 00101010
15 12 11 8 7 0
op1 ← SignExtend32(Rm);newpr ← op1;delayedpr ← newpr;PR’ ← Register(newpr);PR’’ ← Register(delayedpr);
362PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
LDS.L @Rm+, PRDescription
This instruction loads PR from memory using register indirect with post-incrementaddressing. A 32-bit value is read from the effective address specified in Rm andloaded into PR. Rm is post-incremented by 4.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
LDS.L @Rm+, PR
0100 m 00100110
15 12 11 8 7 0
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);newpr ← SignExtend32(ReadMemory32(address));delayedpr ← newpr;op1 ← op1 + 4;Rm ← Register(op1);PR’ ← Register(newpr);PR’’ ← Register(delayedpr);
363PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
LDTLBDescription
This instruction loads the contents of the PTEH/PTEL registers into the UTLB(unified translation lookaside buffer) specified by MMUCR.URC (random counterfield in the MMC control register).
LDTLB is a privileged instruction, and can only be used in privileged mode. Use ofthis instruction in user mode will cause a RESINST trap.
Operation
Exceptions
RESINST
Note
As this instruction loads the contents of the PTEH/PTEL registers into a UTLBentry, it should be used either with the MMU disabled, or in the P1 or P2 virtualspace with the MMU enabled (see Chapter 3: Memory management unit (MMU) onpage 41, for details). After this instruction is issued, there must be at least one
LDTLB
0000000000111000
15 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
UTLB[MMUCR.URC].ASID ← PTEH.ASIDUTLB[MMUCR.URC].VPN ← PTEH.VPNUTLB[MMUCR.URC].PPN ← PTEH.PPNUTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0UTLB[MMUCR.URC].SH ← PTEL.SHUTLB[MMUCR.URC].PR ← PTEL.PRUTLB[MMUCR.URC].WT ← PTEL.WTUTLB[MMUCR.URC].C ← PTEL.CUTLB[MMUCR.URC].D ← PTEL.DUTLB[MMUCR.URC].V ← PTEL.V
364PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
instruction between the LDTLB instruction and the execution of an instruction fromthe areas P0, U0, and P3 (i.e. via a BRAF, BSRF, JMP, JSR, RTS, or RTE).
365PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MAC.L @Rm+, @Rn+Description
This instruction reads the signed 32-bit value at the effective address specified inRn, and then post-increments Rn by 4. It also reads the signed 32-bit value at theeffective address specified in Rm, and then post-increments Rm by 4. These 2 valuesare multiplied together to give a 64-bit result, and this result is added to the 64-bitaccumulator held in MACL and MACH. This accumulation gives an output with 65bits of precision.
If the S-bit is 0, the result is the lower 64 bits of the accumulation. If the S-bit is 1,the result is calculated by saturating the accumulation to the signed range [-248,248). In either case, the 64-bit result is split into low and high halves, which areplaced into MACL and MACH respectively.
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
If Rm and Rn refer to the same register (i.e. m = n), then this register will bepost-incremented twice. The instruction will read two long-words from consecutivememory locations.
Operation
MAC.L @Rm+, @Rn+
0000 n m 1111
15 12 11 8 7 4 3 0
366PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
macl ← ZeroExtend32(MACL);mach ← ZeroExtend32(MACH);s ← ZeroExtend1(S);m_field ← ZeroExtend4(m);n_field ← ZeroExtend4(n);m_address ← SignExtend32(Rm);n_address ← SignExtend32(Rn);value2 ← SignExtend32(ReadMemory32(ZeroExtend32(n_address)));n_address ← n_address + 4;IF (n_field = m_field){
m_address ← m_address + 4;n_address ← n_address + 4;
}value1 ← SignExtend32(ReadMemory32(ZeroExtend32(m_address)));m_address ← m_address + 4;mul ← value2 × value1;mac ← (mach << 32) + macl;result ← mac + mul;IF (s = 1)
IF (((result ⊕ mac) ∧ (result ⊕ mul))< 63 FOR 1 > = 1)IF (mac< 63 FOR 1 > = 0)
result ← 247 - 1;ELSE
result ← - 247;ELSE
result ← SignedSaturate48(result);macl ← result;mach ← result >> 32;Rm ← Register(m_address);Rn ← Register(n_address);MACL ← ZeroExtend32(macl);MACH ← ZeroExtend32(mach);
MAC.L @Rm+, @Rn+
367PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MAC.W @Rm+, @Rn+Description
This instruction reads the signed 16-bit value at the effective address specified inRn, and then post-increments Rn by 2. It also reads the signed 16-bit value at theeffective address specified in Rm, and then post-increments Rm by 2. These 2 valuesare multiplied together to give a 32-bit result.
If the S-bit is 0, the 32-bit multiply result is added to the 64-bit accumulator held inMACL and MACH. This accumulation gives an output with 65 bits of precision, andthe result is the lower 64 bits of the accumulation. The result is split into low andhigh halves, which are placed into MACL and MACH respectively.
If the S-bit is 1, the 32-bit multiply result is added to the 32-bit accumulator held inMACL. This accumulation gives an output with 33 bits of precision, and is saturatedto the signed range [-231, 231), and then placed in MACL. If the accumulationoverflows this signed range, then MACH is set to 1 to denote overflow otherwiseMACH is unchanged.
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
If Rm and Rn refer to the same register (i.e. m = n), then this register will bepost-incremented twice. The instruction will read two words from consecutivememory locations.
Operation
MAC.W @Rm+, @Rn+
0100 n m 1111
15 12 11 8 7 4 3 0
368PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
macl ← ZeroExtend32(MACL);mach ← ZeroExtend32(MACH);s ← ZeroExtend1(S);m_field ← ZeroExtend4(m);n_field ← ZeroExtend4(n);m_address ← SignExtend32(Rm);n_address ← SignExtend32(Rn);value2 ← SignExtend16(ReadMemory16(ZeroExtend32(n_address)));n_address ← n_address + 2;IF (n_field = m_field){
m_address ← m_address + 2;n_address ← n_address + 2;
}value1 ← SignExtend16(ReadMemory16(ZeroExtend32(m_address)));m_address ← m_address + 2;mul ← value2 × value1;IF (s = 1){
macl ← SignExtend32(macl) + mul;temp ← SignedSaturate32(macl);IF (macl = temp)
result ← (mach << 32) ∨ ZeroExtend32(macl);ELSE
result ← (0x1 << 32) ∨ ZeroExtend32(temp);}ELSE
result ← ((mach << 32) + macl) + mul;macl ← result;mach ← result >> 32;Rm ← Register(m_address);Rn ← Register(n_address);MACL ← ZeroExtend32(macl);MACH ← ZeroExtend32(mach);
MAC.W @Rm+, @Rn+
369PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV Rm, RnDescription
This instruction copies the value of Rm to Rn.
Operation
Note
MOV Rm, Rn
0110 n m 0011
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← op1;Rn ← Register(op2);
370PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV #imm, RnDescription
This instruction sign-extends the 8-bit immediate s and places the result in Rn.
Operation
Note
The ‘#imm’ in the assembly syntax represents the immediate s after sign extension.
MOV #imm, Rn
1110 n s
15 12 11 8 7 0
imm ← SignExtend8(s);op2 ← imm;Rn ← Register(op2);
371PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.B Rm, @RnDescription
This instruction stores a byte to memory using register indirect withzero-displacement addressing. The effective address is specified in Rn. The byte tobe stored is held in the lowest 8 bits of Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
MOV.B Rm, @Rn
0010 n m 0000
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(op2);WriteMemory8(address, op1);
372PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.B Rm, @-RnDescription
This instruction stores a byte to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 1 to give the effective address. The byte to bestored is held in the lowest 8 bits of Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.B Rm, @-Rn
0010 n m 0100
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(op2 - 1);WriteMemory8(address, op1);op2 ← address;Rn ← Register(op2);
373PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.B Rm, @(R0, Rn)Description
This instruction stores a byte to memory using register indirect addressing. Theeffective address is formed by adding R0 to Rn. The byte to be stored is held in thelowest 8 bits of Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.B Rm, @(R0, Rn)
0000 n m 0100
15 12 11 8 7 4 3 0
r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(r0 + op2);WriteMemory8(address, op1);
374PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.B R0, @(disp, GBR)Description
This instruction stores a byte to memory using GBR-relative with displacementaddressing. The effective address is formed by adding GBR to the zero-extended8-bit immediate i. The byte to be stored is held in the lowest 8 bits of R0.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extension.
MOV.B R0, @(disp, GBR)
11000000 i
15 8 7 0
gbr ← SignExtend32(GBR);r0 ← SignExtend32(R0);disp ← ZeroExtend8(i);address ← ZeroExtend32(disp + gbr);WriteMemory8(address, r0);
375PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.B R0, @(disp, Rn)Description
This instruction stores a byte to memory using register indirect with displacementaddressing. The effective address is formed by adding Rn and the zero-extended4-bit immediate i. The byte to be stored is held in the lowest 8 bits of R0.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extension.
MOV.B R0, @(disp, Rn)
10000000 n i
15 8 7 4 3 0
r0 ← SignExtend32(R0);disp ← ZeroExtend4(i);op2 ← SignExtend32(Rn);address ← ZeroExtend32(disp + op2);WriteMemory8(address, r0);
376PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.B @Rm, RnDescription
This instruction loads a signed byte from memory using register indirect withzero-displacement addressing. The effective address is specified in Rm. The byte isloaded from the effective address, sign-extended and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
MOV.B @Rm, Rn
0110 n m 0000
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);op2 ← SignExtend8(ReadMemory8(address));Rn ← Register(op2);
377PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.B @Rm+, RnDescription
This instruction loads a signed byte from memory using register indirect withpost-increment addressing. The byte is loaded from the effective address specified inRm and sign-extended. Rm is post-incremented by 1, and then the loaded byte isplaced in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
If Rm and Rn refer to the same register (i.e. m = n), the result placed in this registerwill be the sign-extended byte loaded from memory.
MOV.B @Rm+, Rn
0110 n m 0100
15 12 11 8 7 4 3 0
m_field ← ZeroExtend4(m);n_field ← ZeroExtend4(n);op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);op2 ← SignExtend8(ReadMemory8(address));IF (m_field = n_field)
op1 ← op2;ELSE
op1 ← op1 + 1;Rm ← Register(op1);Rn ← Register(op2);
378PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.B @(R0, Rm), RnDescription
This instruction loads a signed byte from memory using register indirectaddressing. The effective address is formed by adding R0 to Rm. The byte is loadedfrom the effective address, sign-extended and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.B @(R0, Rm), Rn
0000 n m 1100
15 12 11 8 7 4 3 0
r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);address ← ZeroExtend32(r0 + op1);op2 ← SignExtend8(ReadMemory8(address));Rn ← Register(op2);
379PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.B @(disp, GBR), R0Description
This instruction loads a signed byte from memory using GBR-relative withdisplacement addressing. The effective address is formed by adding GBR to thezero-extended 8-bit immediate i. The byte is loaded from the effective address,sign-extended and placed in R0.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extension.
MOV.B @(disp, GBR), R0
11000100 i
15 8 7 0
gbr ← SignExtend32(GBR);disp ← ZeroExtend8(i);address ← ZeroExtend32(disp + gbr);r0 ← SignExtend8(ReadMemory8(address));R0 ← Register(r0);
380PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.B @(disp, Rm), R0Description
This instruction loads a signed byte from memory using register indirect withdisplacement addressing. The effective address is formed by adding Rm to thezero-extended 4-bit immediate i. The byte is loaded from the effective address,sign-extended and placed in R0.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extension.
MOV.B @(disp, Rm), R0
10000100 m i
15 8 7 4 3 0
disp ← ZeroExtend4(i);op2 ← SignExtend32(Rm);address ← ZeroExtend32(disp + op2);r0 ← SignExtend8(ReadMemory8(address));R0 ← Register(r0);
381PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.L Rm, @RnDescription
This instruction stores a long-word to memory using register indirect withzero-displacement addressing. The effective address is specified in Rn. Thelong-word to be stored is held in Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
MOV.L Rm, @Rn
0010 n m 0010
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(op2);WriteMemory32(address, op1);
382PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.L Rm, @-RnDescription
This instruction stores a long-word to memory using register indirect withpre-decrement addressing. Rn is pre-decremented by 4 to give the effective address.The long-word to be stored is held in Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.L Rm, @-Rn
0010 n m 0110
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(op2 - 4);WriteMemory32(address, op1);op2 ← address;Rn ← Register(op2);
383PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.L Rm, @(R0, Rn)Description
This instruction stores a long-word to memory using register indirect addressing.The effective address is formed by adding R0 to Rn. The long-word to be stored isheld in Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.L Rm, @(R0, Rn)
0000 n m 0110
15 12 11 8 7 4 3 0
r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(r0 + op2);WriteMemory32(address, op1);
384PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.L R0, @(disp, GBR)Description
This instruction stores a long-word to memory using GBR-relative withdisplacement addressing. The effective address is formed by adding GBR to thezero-extended 8-bit immediate i multiplied by 4. The long-word to be stored is heldin R0.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.L R0, @(disp, GBR)
11000010 i
15 8 7 0
gbr ← SignExtend32(GBR);r0 ← SignExtend32(R0);disp ← ZeroExtend8(i) << 2;address ← ZeroExtend32(disp + gbr);WriteMemory32(address, r0);
385PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.L Rm, @(disp, Rn)Description
This instruction stores a long-word to memory using register indirect with displacementaddressing. The effective address is formed by adding Rn to the zero-extended 4-bitimmediate i multiplied by 4. The long-word to be stored is held in Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.L Rm, @(disp, Rn)
0001 n m i
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);disp ← ZeroExtend4(i) << 2;op3 ← SignExtend32(Rn);address ← ZeroExtend32(disp + op3);WriteMemory32(address, op1);
386PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.L @Rm, RnDescription
This instruction loads a signed long-word from memory using register indirect withzero-displacement addressing. The effective address is specified in Rm. Thelong-word is loaded from the effective address and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
MOV.L @Rm, Rn
0110 n m 0010
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);op2 ← SignExtend32(ReadMemory32(address));Rn ← Register(op2);
387PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.L @Rm+, RnDescription
This instruction loads a signed long-word from memory using register indirect withpost-increment addressing. The long-word is loaded from the effective addressspecified in Rm. Rm is post-incremented by 4, and then the loaded long-word isplaced in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
If Rm and Rn refer to the same register (i.e. m = n), the result placed in this registerwill be the sign-extended byte loaded from memory.
MOV.L @Rm+, Rn
0110 n m 0110
15 12 11 8 7 4 3 0
m_field ← ZeroExtend4(m);n_field ← ZeroExtend4(n);op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);op2 ← SignExtend32(ReadMemory32(address));IF (m_field = n_field)
op1 ← op2;ELSE
op1 ← op1 + 4;Rm ← Register(op1);Rn ← Register(op2);
388PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.L @(R0, Rm), RnDescription
This instruction loads a signed long-word from memory using register indirectaddressing. The effective address is formed by adding R0 to Rm. The long-word isloaded from the effective address and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.L @(R0, Rm), Rn
0000 n m 1110
15 12 11 8 7 4 3 0
r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);address ← ZeroExtend32(r0 + op1);op2 ← SignExtend32(ReadMemory32(address));Rn ← Register(op2);
389PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.L @(disp, GBR), R0Description
This instruction loads a signed long-word from memory using GBR-relative withdisplacement addressing. The effective address is formed by adding GBR to thezero-extended 8-bit immediate i multiplied by 4. The long-word is loaded from theeffective address and placed in R0.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.L @(disp, GBR), R0
11000110 i
15 8 7 0
gbr ← SignExtend32(GBR);disp ← ZeroExtend8(i) << 2;address ← ZeroExtend32(disp + gbr);r0 ← SignExtend32(ReadMemory32(address));R0 ← Register(r0);
390PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.L @(disp, PC), RnDescription
This instruction loads a signed long-word from memory using PC-relative withdisplacement addressing. The effective address is formed by calculating PC+4,clearing the lowest 2 bits, and adding the zero-extended 8-bit immediate imultiplied by 4. This address calculation ensures that the effective address iscorrectly aligned for a long-word access regardless of the PC alignment. Thelong-word is loaded from the effective address and placed in Rn.
Operation
Exceptions
ILLSLOT, RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
An ILLSLOT exception is raised if this instruction is executed in a delay slot.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.L @(disp, PC), Rn
1101 n i
15 12 11 8 7 0
pc ← SignExtend32(PC);disp ← ZeroExtend8(i) << 2;IF (IsDelaySlot())
THROW ILLSLOT;address ← ZeroExtend32(disp + ((pc + 4) ∧ (~ 0x3)));op2 ← SignExtend32(ReadMemory32(address));Rn ← Register(op2);
391PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.L @(disp, Rm), RnDescription
This instruction loads a signed long-word from memory using register indirect withdisplacement addressing. The effective address is formed by adding Rm to thezero-extended 4-bit immediate i multiplied by 4. The long-word is loaded from theeffective address and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.L @(disp, Rm), Rn
0101 n m i
15 12 11 8 7 4 3 0
disp ← ZeroExtend4(i) << 2;op2 ← SignExtend32(Rm);address ← ZeroExtend32(disp + op2);op3 ← SignExtend32(ReadMemory32(address));Rn ← Register(op3);
392PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.W Rm, @RnDescription
This instruction stores a word to memory using register indirect withzero-displacement addressing. The effective address is specified in Rn. The word tobe stored is held in the lowest 16 bits of Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
MOV.W Rm, @Rn
0010 n m 0001
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(op2);WriteMemory16(address, op1);
393PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.W Rm, @-RnDescription
This instruction stores a word to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 2 to give the effective address. The word to bestored is held in the lowest 16 bits of Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.W Rm, @-Rn
0010 n m 0101
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(op2 - 2);WriteMemory16(address, op1);op2 ← address;Rn ← Register(op2);
394PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.W Rm, @(R0, Rn)Description
This instruction stores a word to memory using register indirect addressing. Theeffective address is formed by adding R0 to Rn. The word to be stored is held in thelowest 16 bits of Rm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.W Rm, @(R0, Rn)
0000 n m 0101
15 12 11 8 7 4 3 0
r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);address ← ZeroExtend32(r0 + op2);WriteMemory16(address, op1);
395PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.W R0, @(disp, GBR)Description
This instruction stores a word to memory using GBR-relative with displacementaddressing. The effective address is formed by adding GBR to the zero-extended8-bit immediate i multiplied by 2. The word to be stored is held in the lowest 16 bitsof R0.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.W R0, @(disp, GBR)
11000001 i
15 8 7 0
gbr ← SignExtend32(GBR);r0 ← SignExtend32(R0);disp ← ZeroExtend8(i) << 1;address ← ZeroExtend32(disp + gbr);WriteMemory16(address, r0);
396PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.W R0, @(disp, Rn)Description
This instruction stores a word to memory using register indirect with displacementaddressing. The effective address is formed by adding Rn to the zero-extended 4-bitimmediate i multiplied by 2. The word to be stored is held in the lowest 16 bits ofRm.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.W R0, @(disp, Rn)
10000001 n i
15 8 7 4 3 0
r0 ← SignExtend32(R0);disp ← ZeroExtend4(i) << 1;op2 ← SignExtend32(Rn);address ← ZeroExtend32(disp + op2);WriteMemory16(address, r0);
397PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.W @Rm, RnDescription
This instruction loads a signed word from memory using register indirect withzero-displacement addressing. The effective address is specified in Rm. The word isloaded from the effective address, sign-extended and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
MOV.W @Rm, Rn
0110 n m 0001
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);op2 ← SignExtend16(ReadMemory16(address));Rn ← Register(op2);
398PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.W @Rm+, RnDescription
This instruction loads a signed word from memory using register indirect withpost-increment addressing. The word is loaded from the effective address specifiedin Rm and sign-extended. Rm is post-incremented by 2, and then the loaded word isplaced in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
If Rm and Rn refer to the same register (i.e. m = n), the result placed in this registerwill be the sign-extended byte loaded from memory.
MOV.W @Rm+, Rn
0110 n m 0101
15 12 11 8 7 4 3 0
m_field ← ZeroExtend4(m);n_field ← ZeroExtend4(n);op1 ← SignExtend32(Rm);address ← ZeroExtend32(op1);op2 ← SignExtend16(ReadMemory16(address));IF (m_field = n_field)
op1 ← op2;ELSE
op1 ← op1 + 2;Rm ← Register(op1);Rn ← Register(op2);
399PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.W @(R0, Rm), RnDescription
This instruction loads a signed word from memory using register indirectaddressing. The effective address is formed by adding R0 to Rm. The word is loadedfrom the effective address, sign-extended and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
MOV.W @(R0, Rm), Rn
0000 n m 1101
15 12 11 8 7 4 3 0
r0 ← SignExtend32(R0);op1 ← SignExtend32(Rm);address ← ZeroExtend32(r0 + op1);op2 ← SignExtend16(ReadMemory16(address));Rn ← Register(op2);
400PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.W @(disp, GBR), R0Description
This instruction loads a signed word from memory using GBR-relative withdisplacement addressing. The effective address is formed by adding GBR to thezero-extended 8-bit immediate i multiplied by 2. The word is loaded from theeffective address, sign-extended and placed in R0.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.W @(disp, GBR), R0
11000101 i
15 8 7 0
gbr ← SignExtend32(GBR);disp ← ZeroExtend8(i) << 1;address ← ZeroExtend32(disp + gbr);r0 ← SignExtend16(ReadMemory16(address));R0 ← Register(r0);
401PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV.W @(disp, PC), RnDescription
This instruction loads a signed word from memory using PC-relative withdisplacement addressing. The effective address is formed by calculating PC+4, andadding the zero-extended 8-bit immediate i multiplied by 2. The word is loaded fromthe effective address, sign-extended and placed in Rn.
Operation
Exceptions
ILLSLOT, RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
An ILLSLOT exception is raised if this instruction is executed in a delay slot.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.W @(disp, PC), Rn
1001 n i
15 12 11 8 7 0
pc ← SignExtend32(PC);disp ← ZeroExtend8(i) << 1;IF (IsDelaySlot())
THROW ILLSLOT;address ← ZeroExtend32(disp + (pc + 4));op2 ← SignExtend16(ReadMemory16(address));Rn ← Register(op2);
402PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV.W @(disp, Rm), R0Description
This instruction loads a signed word from memory using register indirect withdisplacement addressing. The effective address is formed by adding Rm to thezero-extended 4-bit immediate i multiplied by 2. The word is loaded from theeffective address, sign-extended and placed in Rn.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOV.W @(disp, Rm), R0
10000101 m i
15 8 7 4 3 0
disp ← ZeroExtend4(i) << 1;op2 ← SignExtend32(Rm);address ← ZeroExtend32(disp + op2);r0 ← SignExtend16(ReadMemory16(address));R0 ← Register(r0);
403PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOVA @(disp, PC), R0Description
This instruction calculates an effective address using PC-relative with displacementaddressing. The effective address is formed by calculating PC+4, clearing the lowest2 bits, and adding the zero-extended 8-bit immediate i multiplied by 4. This addresscalculation ensures that the effective address is correctly aligned for a long-wordaccess regardless of the PC alignment. The effective address is placed in R0.
Operation
Exceptions
ILLSLOT
Note
The instructions only computes the effective address, no memory request is made.
An ILLSLOT exception is raised if this instruction is executed in a delay slot.
The ‘disp’ in the assembly syntax represents the immediate i after zero extensionand scaling.
MOVA @(disp, PC), R0
11000111 i
15 8 7 0
pc ← SignExtend32(PC);disp ← ZeroExtend8(i) << 2;IF (IsDelaySlot())
THROW ILLSLOT;r0 ← disp + ((pc + 4) ∧ (~ 0x3));R0 ← Register(r0);
404PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOVCA.L R0, @RnDescription
This instruction stores the long-word in R0 to memory at the effective addressspecified in Rn. It provides a hint to the implementation that it is not necessary toretrieve the data of this operand cache block from memory. It isimplementation-specific as to whether the memory access will occur.
The effective address specified in Rn identifies a surrounding block of memory,which starts at an address aligned to the cache block size and has a size equal to thecache block size. The cache block size is implementation dependent.
MOVCA.L checks for address error, translation miss and protection exception cases.
Apart from the written long-word, the value of all other locations in the memoryblock targeted by a MOVCA.L becomes architecturally undefined. Programs mustnot rely on these values. For compatibility with other implementations, softwaremust exercise care when using MOVCA.L.
Operation
MOVCA.L R0, @Rn
0000 n 11000011
15 12 11 8 7 0
r0 ← SignExtend32(R0);op1 ← SignExtend32(Rn);IF (AddressUnavailable(op1))
THROW WADDERR, op1;IF (MMU() AND DataAccessMiss(op1))
THROW WTLBMISS, op1;IF (MMU() AND WriteProhibited(op1)) THROW WRITEPROT, op1;IF (MMU() AND NOT DirtyBit(op1)) THROW FIRSTWRITE, op1ALLOCO(op1);address ← ZeroExtend32(op1);WriteMemory32(op1, r0);
405PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
406PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOVT RnDescription
This instruction copies the T-bit to Rn.
Operation
Note
MOVT Rn
0000 n 00101001
15 12 11 8 7 0
t ← ZeroExtend1(T);op1 ← t;Rn ← Register(op1);
407PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MUL.L Rm, RnDescription
This instruction multiplies the 32-bit value in Rm by the 32-bit value in Rn, andplaces the least significant 32 bits of the result in MACL. The most significant 32bits of the result are not provided, and MACH is not modified.
Operation
Note
MUL.L Rm, Rn
0000 n m 0111
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);macl ← op1 × op2;MACL ← ZeroExtend32(macl);
408PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MULS.W Rm, RnDescription
This instruction multiplies the signed lowest 16 bits of Rm by the signed lowest 16bits of Rn, and places the full 32-bit result in MACL. MACH is not modified.
Operation
Note
MULS.W Rm, Rn
0010 n m 1111
15 12 11 8 7 4 3 0
op1 ← SignExtend16(SignExtend32(Rm));op2 ← SignExtend16(SignExtend32(Rn));macl ← op1 × op2;MACL ← ZeroExtend32(macl);
409PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MULU.W Rm, RnDescription
This instruction multiplies the unsigned lowest 16 bits of Rm by the unsigned lowest16 bits of Rn, and places the full 32-bit result in MACL. MACH is not modified.
Operation
Note
MULU.W Rm, Rn
0010 n m 1110
15 12 11 8 7 4 3 0
op1 ← ZeroExtend16(SignExtend32(Rm));op2 ← ZeroExtend16(SignExtend32(Rn));macl ← op1 × op2;MACL ← ZeroExtend32(macl);
410PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
NEG Rm, RnDescription
This instruction subtracts Rm from zero and places the result in Rn.
Operation
Note
NEG Rm, Rn
0110 n m 1011
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← - op1;Rn ← Register(op2);
411PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
NEGC Rm, RnDescription
This instruction subtracts Rm and the T-bit from zero and places the result in Rn.The borrow from the subtraction is placed in the T-bit.
Operation
Note
NEGC Rm, Rn
0110 n m 1010
15 12 11 8 7 4 3 0
t ← ZeroExtend1(T);op1 ← ZeroExtend32(Rm);op2 ← (- op1) - t;t ← op2< 32 FOR 1 >;Rn ← Register(op2);T ← Bit(t);
412PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
NOPDescription
This instruction performs no operation.
Operation
NOP
0000000000001001
15 0
413PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
NOT Rm, RnDescription
This instruction performs a bitwise NOT on Rm and places the result in Rn.
Operation
Note
NOT Rm, Rn
0110 n m 0111
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← ~ op1;Rn ← Register(op2);
414PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
OCBI @RnDescription
This instruction invalidates an operand cache block (if any) that corresponds to aspecified effective address. If the data in the operand cache block is dirty, it isdiscarded without write-back to memory. Immediately after execution of OCBI,assuming no exception was raised, it is guaranteed that the targeted memory blockin physical address space is not present in the operand cache.
The effective address specified in Rn identifies a surrounding block of memory,which starts at an address aligned to the cache block size and has a size equal to thecache block size. The cache block size is implementation dependent.
OCBI invalidates an implementation-dependent amount of data. For compatibilitywith other implementations, software must exercise care when using OCBI.
OCBI checks for address error, translation miss and protection exception cases.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
OCBI @Rn
0000 n 10010011
15 12 11 8 7 0
op1 ← SignExtend32(Rn);IF (AddressUnavailable(op1))
THROW WADDERR, op1;IF (MMU() AND DataAccessMiss(op1))
THROW WTLBMISS, op1;IF (MMU() AND WriteProhibited(op1))
THROW WRITEPROT, op1;IF (MMU() AND NOT DirtyBit(op1)) THROW FIRSTWRITE, op1OCBI(op1);
415PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
OCBP @RnDescription
This instruction purges an operand cache block (if any) that corresponds to aspecified effective address. If the data in the operand cache block is dirty, it iswritten back to memory before being discarded. Immediately after execution ofOCBP, assuming no exception was raised, it is guaranteed that the targetedmemory block in physical address space is not present in the operand cache.
The effective address specified in Rn identifies a surrounding block of memory,which starts at an address aligned to the cache block size and has a size equal to thecache block size. The cache block size is implementation dependent.
OCBP checks for address error, translation miss and protection exception cases.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
OCBP @Rn
0000 n 10100011
15 12 11 8 7 0
op1 ← SignExtend32(Rn);IF (AddressUnavailable(op1))
THROW RADDERR, op1;IF (MMU() AND DataAccessMiss(op1))
THROW RTLBMISS, op1;IF (MMU() AND (ReadProhibited(op1) AND WriteProhibited(op1)))
THROW READPROT, op1;OCBP(op1);
416PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
OCBWB @RnDescription
This instruction write-backs an operand cache block (if any) that corresponds to aspecified effective address. If the data in the operand cache block is dirty, it iswritten back to memory but is not discarded. Immediately after execution ofOCBWB, assuming no exception was raised, it is guaranteed that the targetedmemory block in physical address space will not be dirty in the operand cache.
The effective address specified in Rn identifies a surrounding block of memory,which starts at an address aligned to the cache block size and has a size equal to thecache block size. The cache block size is implementation dependent.
OCBWB checks for address error, translation miss and protection exception cases.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
OCBWB @Rn
0000 n 10110011
15 12 11 8 7 0
op1 ← SignExtend32(Rn);IF (AddressUnavailable(op1))
THROW RADDERR, op1;IF (MMU() AND DataAccessMiss(op1))
THROW RTLBMISS, op1;IF (MMU() AND (ReadProhibited(op1) AND WriteProhibited(op1)))
THROW READPROT, op1;OCBWB(op1);
417PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
OR Rm, RnDescription
This instruction performs a bitwise OR of Rm with Rn and places the result in Rn.
Operation
Note
OR Rm, Rn
0010 n m 1011
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← ZeroExtend32(Rn);op2 ← op2 ∨ op1;Rn ← Register(op2);
418PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
OR #imm, R0Description
This instruction performs a bitwise OR of R0 with the zero-extended 8-bitimmediate i and places the result in R0.
Operation
Note
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
OR #imm, R0
11001011 i
15 8 7 0
r0 ← ZeroExtend32(R0);imm ← ZeroExtend8(i);r0 ← r0 ∨ imm;R0 ← Register(r0);
419PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
OR.B #imm, @(R0, GBR)Description
This instruction performs a bitwise OR of an immediate constant with 8 bits of dataheld in memory. The effective address is calculated by adding R0 and GBR. The 8bits of data at the effective address are read. A bitwise OR is performed of the readdata with the zero-extended 8-bit immediate i. The result is written back to the 8bits of data at the same effective address.
Operation
Exceptions
WADDERR, WTLBMISS, READPROT, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
OR.B #imm, @(R0, GBR)
11001111 i
15 8 7 0
r0 ← SignExtend32(R0);gbr ← SignExtend32(GBR);imm ← ZeroExtend8(i);address ← ZeroExtend32(r0 + gbr);value ← ZeroExtend8(ReadMemory8(address));value ← value ∨ imm;WriteMemory8(address, value);
420PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
PREF @RnDescription
This instruction indicates a software-directed data prefetch from the specifiedeffective address. Software can use this instruction to give advance notice thatparticular data will be required. It is implementation-specific as to whether aprefetch will be performed.
The effective address specified in Rn identifies a surrounding block of memory,which starts at an address aligned to the cache block size and has a size equal to thecache block size. The cache block size is implementation dependent.
Any OTLBMULTIHIT or RADDERR exception is delivered, other exceptions arediscarded and the prefetch has no effect.
The semantics of a PREF instruction, when applied to an address in the storequeues range (0xE0000000 to 0xE3FFFFFF) is quite different to that elsewhere.For details refer to Section 4.6: Store queues on page 101.
Operation
Exceptions
RADDERR, OTLBMULTIHIT
Note
PREF @Rn
0000 n 10000011
15 12 11 8 7 0
op1 ← SignExtend32(Rn);IF (AddressUnavailable(op1))
THROW RADDERR, op1IF (NOT (MMU() AND DataAccessMiss(op1)))
IF (NOT (MMU() AND ReadProhibited(op1)))PREF(op1);
421PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
ROTCL RnDescription
This instruction performs a one-bit left rotation of the bits held in Rn and the T-bit.The 32-bit value in Rn is shifted one bit to the left, the least significant bit is giventhe old value of the T-bit, and the bit that is shifted out is moved to the T-bit.
Operation
Note
ROTCL Rn
0100 n 00100100
15 12 11 8 7 0
t ← ZeroExtend1(T);op1 ← ZeroExtend32(Rn);op1 ← (op1 << 1) ∨ t;t ← op1< 32 FOR 1 >;Rn ← Register(op1);T ← Bit(t);
422PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
ROTCR RnDescription
This instruction performs a one-bit right rotation of the bits held in Rn and the T-bit.The 32-bit value in Rn is shifted one bit to the right, the most significant bit is giventhe old value of the T-bit, and the bit that is shifted out is moved to the T-bit.
Operation
Note
ROTCR Rn
0100 n 00100101
15 12 11 8 7 0
t ← ZeroExtend1(T);op1 ← ZeroExtend32(Rn);oldt ← t;t ← op1< 0 FOR 1 >;op1 ← (op1 >> 1) ∨ (oldt << 31);Rn ← Register(op1);T ← Bit(t);
423PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
ROTL RnDescription
This instruction performs a one-bit left rotation of the bits held in Rn. The 32-bitvalue in Rn is shifted one bit to the left, and the least significant bit is given thevalue of the bit that is shifted out. The bit that is shifted out of the operand is alsocopied to the T-bit.
Operation
Note
ROTL Rn
0100 n 00000100
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);t ← op1< 31 FOR 1 >;op1 ← (op1 << 1) ∨ t;Rn ← Register(op1);T ← Bit(t);
424PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
ROTR RnDescription
This instruction performs a one-bit right rotation of the bits held in Rn. The 32-bitvalue in Rn is shifted one bit to the right, and the most significant bit is given thevalue of the bit that is shifted out. The bit that is shifted out of the operand is alsocopied to the T-bit.
Operation
Note
ROTR Rn
0100 n 00000101
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);t ← op1< 0 FOR 1 >;op1 ← (op1 >> 1) ∨ (t << 31);Rn ← Register(op1);T ← Bit(t);
425PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
RTEDescription
This instruction returns from an exception or interrupt handling routine byrestoring the PC and SR values from SPC and SSR. Program execution continuesfrom the address specified by the restored PC value.
RTE is a privileged instruction, and can only be used in privileged mode. Use of thisinstruction in user mode will cause an RESINST exception.
Operation
Exceptions
RESINST, ILLSLOT
Note
Since this is a delayed branch instruction, the instruction in the delay slot isexecuted before branching and must not generate an exception.
An ILLSLOT exception is raised if this instruction is executed in a delay slot.
Interrupts are not accepted between this instruction and the instruction in thedelay slot.
RTE
0000000000101011
15 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
ssr ← SignExtend32(SSR);pc ← SignExtend32(PC)
IF (IsDelaySlot())THROW ILLSLOT;
target ← pc;delayedpc ← target ∧ (~ 0x1);PC’’ ← Register(delayedpc);
426PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
The SR value defined prior to RTE execution is used to fetch the instruction in theRTE delay slot. However, the value of SR used during execution of the instruction inthe delay slot, is that restored from SSR by the RTE instruction. It is recommendedthat, because of this feature, privileged instructions should not be placed in thedelay slot.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
The behavior is architecturally undefined if the instruction in an RTE delay slotraises an exception. For this reason, it is recommended that only simple instructionsthat cannot generate exceptions are placed in RTE delay slots (unless considerablecare is taken).
427PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
RTSDescription
This instruction is a delayed unconditional branch used for returning from asubroutine. The value in PR specifies the target address.
Operation
Exceptions
ILLSLOT
Note
Since this is a delayed branch instruction, the delay slot is executed beforebranching. An ILLSLOT exception is raised if this instruction is executed in a delayslot.
If the branch target address is invalid then IADDERR trap is not delivered untilafter the instruction in the delay slot has executed and the PC has advanced to thetarget address, that is the exception is associated with the target instruction not thebranch.
RTS
0000000000001011
15 0
pr ← SignExtend32(PR);IF (IsDelaySlot())
THROW ILLSLOT;target ← pr;delayedpc ← target ∧ (~ 0x1);PC’’ ← Register(delayedpc);
428PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SETSDescription
This instruction sets the S-bit to 1.
Operation
SETS
0000000001011000
15 0
s ← 1;S ← Bit(s);
429PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SETTDescription
This instruction sets the T-bit to 1.
Operation
SETT
0000000000011000
15 0
t ← 1;T ← Bit(t);
430PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SHAD Rm, RnDescription
This instruction performs an arithmetic shift of Rn, with the dynamic shift directionand shift amount indicated by Rm, and places the result in Rn. If Rm is zero, no shiftis performed. If Rm is greater than zero, this is a left shift and the shift amount isgiven by the least significant 5 bits of Rm. If Rm is less than zero, this is anarithmetic right shift and the shift amount is given by the least significant 5 bits ofRm subtracted from 32. In the case where Rm indicates an arithmetic right shift by32, the result is filled with copies of the sign-bit of the original Rn.
Operation
Note
SHAD Rm, Rn
0100 n m 1100
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);shift_amount ← ZeroExtend5(op1);IF (op1 ≥ 0)
op2 ← op2 << shift_amount;ELSE IF (shift_amount ≠ 0)
op2 ← op2 >> (32 - shift_amount);ELSE IF (op2 < 0)
op2 ← - 1;ELSE
op2 ← 0;Rn ← Register(op2);
431PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SHAL RnDescription
Arithmetically shifts Rn to the left by one bit and places the result in Rn. The bitthat is shifted out of the operand is moved to T-bit.
Operation
Note
SHAL Rn
0100 n 00100000
15 12 11 8 7 0
op1 ← SignExtend32(Rn);t ← op1< 31 FOR 1 >;op1 ← op1 << 1;Rn ← Register(op1);T ← Bit(t);
432PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SHAR RnDescription
Arithmetically shifts Rn to the right by one bit and places the result in Rn. The bitthat is shifted out of the operand is moved to T-bit.
Operation
Note
SHAR Rn
0100 n 00100001
15 12 11 8 7 0
op1 ← SignExtend32(Rn);t ← op1< 0 FOR 1 >;op1 ← op1 >> 1;Rn ← Register(op1);T ← Bit(t);
433PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SHLD Rm, RnDescription
This instruction performs a logical shift of Rn, with the dynamic shift direction andshift amount indicated by Rm, and places the result in Rn. If Rm is zero, no shift isperformed. If Rm is greater than zero, this is a left shift and the shift amount isgiven by the least significant 5 bits of Rm. If Rm is less than zero, this is a logicalright shift and the shift amount is given by the least significant 5 bits of Rmsubtracted from 32. In the case where Rm indicates a logical right shift by 32, theresult is 0.
Operation
Note
SHLD Rm, Rn
0100 n m 1101
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← ZeroExtend32(Rn);shift_amount ← ZeroExtend5(op1);IF (op1 ≥ 0)
op2 ← op2 << shift_amount;ELSE IF (shift_amount ≠ 0)
op2 ← op2 >> (32 - shift_amount);ELSE
op2 ← 0;Rn ← Register(op2);
434PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SHLL RnDescription
This instruction performs a logical left shift of Rn by 1 bit and places the result inRn. The bit that is shifted out is moved to the T-bit.
Operation
Note
SHLL Rn
0100 n 00000000
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);t ← op1< 31 FOR 1 >;op1 ← op1 << 1;Rn ← Register(op1);T ← Bit(t);
435PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SHLL2 RnDescription
This instruction performs a logical left shift of Rn by 2 bits and places the result inRn. The bits that are shifted out are discarded.
Operation
Note
SHLL2 Rn
0100 n 00001000
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);op1 ← op1 << 2;Rn ← Register(op1);
436PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SHLL8 RnDescription
This instruction performs a logical left shift of Rn by 8 bits and places the result inRn. The bits that are shifted out are discarded.
Operation
Note
SHLL8 Rn
0100 n 00011000
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);op1 ← op1 << 8;Rn ← Register(op1);
437PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SHLL16 RnDescription
This instruction performs a logical left shift of Rn by 16 bits and places the result inRn. The bits that are shifted out are discarded.
Operation
Note
SHLL16 Rn
0100 n 00101000
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);op1 ← op1 << 16;Rn ← Register(op1);
438PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SHLR RnDescription
This instruction performs a logical right shift of Rn by 1 bit and places the result inRn. The bit that is shifted out is moved to the T-bit.
Operation
Note
SHLR Rn
0100 n 00000001
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);t ← op1< 0 FOR 1 >;op1 ← op1 >> 1;Rn ← Register(op1);T ← Bit(t);
439PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SHLR2 RnDescription
This instruction performs a logical right shift of Rn by 2 bits and places the result inRn. The bits that are shifted out are discarded.
Operation
Note
SHLR2 Rn
0100 n 00001001
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);op1 ← op1 >> 2;Rn ← Register(op1);
440PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SHLR8 RnDescription
This instruction performs a logical right shift of Rn by 8 bits and places the result inRn. The bits that are shifted out are discarded.
Operation
Note
SHLR8 Rn
0100 n 00011001
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);op1 ← op1 >> 8;Rn ← Register(op1);
441PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SHLR16 RnDescription
This instruction performs a logical right shift of Rn by 16 bits and places the resultin Rn. The bits that are shifted out are discarded.
Operation
Note
SHLR16 Rn
0100 n 00101001
15 12 11 8 7 0
op1 ← ZeroExtend32(Rn);op1 ← op1 >> 16;Rn ← Register(op1);
442PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SLEEPDescription
This instruction places the CPU in the power-down state.
In power-down mode, the CPU retains its internal state, but immediately stopsexecuting instructions and waits for an interrupt request. The PC at the point ofsleep is the address of the instruction immediately following the SLEEP instruction.This property ensures that when the CPU receives an interrupt request, and exitsthe power-down state, the SPC will contain the address of the instruction followingthe SLEEP.
SLEEP is a privileged instruction, and can only be used in privileged mode. Use ofthis instruction in user mode will cause an RESINST exception.
Operation
Exceptions
RESINST
Note
The effect of SLEEP upon rest of system depends upon the system architecture.Refer to the system architecture manual of the appropriate product for furtherdetails.
SLEEP
0000000000011011
15 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
SLEEP()
443PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC SR, RnDescription
This instruction copies SR to Rn, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
STC SR, Rn
0000 n 00000010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
sr ← SignExtend32(SR);op1 ← srRn ← Register(op1);
444PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC VBR, RnDescription
This instruction copies VBR to Rn, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
STC VBR, Rn
0000 n 00100010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
vbr ← SignExtend32(VBR);op1 ← vbrRn ← Register(op1);
445PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC SSR, RnDescription
This instruction copies SSR to Rn, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
STC SSR, Rn
0000 n 00110010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
ssr ← SignExtend32(SSR);op1 ← ssrRn ← Register(op1);
446PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC SPC, RnDescription
This instruction copies SPC to Rn, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
STC SPC, Rn
0000 n 01000010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
spc ← SignExtend32(SPC);op1 ← spcRn ← Register(op1);
447PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC SGR, RnDescription
This instruction copies SGR to Rn, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
STC SGR, Rn
0000 n 00111010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
sgr ← SignExtend32(SGR);op1 ← sgrRn ← Register(op1);
448PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC DBR, RnDescription
This instruction copies DBR to Rn, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
STC DBR, Rn
0000 n 11111010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
dbr ← SignExtend32(DBR);op1 ← dbrRn ← Register(op1);
449PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC Rm_BANK, RnDescription
This instruction copies Rm_BANK to Rn, it is a privileged instruction.
Operation
Exceptions
RESINST
Note
STC Rm_BANK, Rn
0000 n 1 m 0010
15 12 11 8 7 6 4 3 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm_BANK);op2 ← op1;Rn ← Register(op2);
450PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC.L SR, @-RnDescription
This instruction stores SR to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of SR is written to the effective address. This is a privileged instruction.
Operation
Exceptions
RESINST, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L SR, @-Rn
0100 n 00000011
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
sr ← SignExtend32(SR);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, sr);op1 ← address;Rn ← Register(op1);
451PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC.L VBR, @-RnDescription
This instruction stores VBR to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of VBR is written to the effective address. This is a privileged instruction.
Operation
Exceptions
RESINST, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L VBR, @-Rn
0100 n 00100011
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
vbr ← SignExtend32(VBR);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, vbr);op1 ← address;Rn ← Register(op1);
452PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC.L SSR, @-RnDescription
This instruction stores SSR to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of SSR is written to the effective address. This is a privileged instruction.
Operation
Exceptions
RESINST, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L SSR, @-Rn
0100 n 00110011
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
ssr ← SignExtend32(SSR);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, ssr);op1 ← address;Rn ← Register(op1);
453PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC.L SPC, @-RnDescription
This instruction stores SPC to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of SPC is written to the effective address. This is a privileged instruction.
Operation
Exceptions
RESINST, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L SPC, @-Rn
0100 n 01000011
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
spc ← SignExtend32(SPC);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, spc);op1 ← address;Rn ← Register(op1);
454PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC.L SGR, @-RnDescription
This instruction stores SGR to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of SGR is written to the effective address. This is a privileged instruction.
Operation
Exceptions
RESINST, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L SGR, @-Rn
0100 n 00110010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
sgr ← SignExtend32(SGR);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, sgr);op1 ← address;Rn ← Register(op1);
455PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC.L DBR, @-RnDescription
This instruction stores DBR to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of DBR is written to the effective address. This is a privileged instruction.
Operation
Exceptions
RESINST, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L DBR, @-Rn
0100 n 11110010
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
dbr ← SignExtend32(DBR);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, dbr);op1 ← address;Rn ← Register(op1);
456PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC.L Rm_BANK, @-RnDescription
This instruction stores Rm_BANK to memory using register indirect withpre-decrement addressing. Rn is pre-decremented by 4 to give the effective address.The 32-bit value of Rm_BANK is written to the effective address. This is aprivileged instruction.
Operation
Exceptions
RESINST, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L Rm_BANK, @-Rn
0100 n 1 m 0011
15 12 11 8 7 0
md ← ZeroExtend1(MD);
IF (md = 0)THROW RESINST;
op1 ← SignExtend32(Rm_BANK);op2 ← SignExtend32(Rn);address ← ZeroExtend32(op2 - 4);WriteMemory32(address, op1);op2 ← address;Rn ← Register(op2);
457PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STC GBR, RnDescription
This instruction copies GBR to Rn.
Operation
Note
STC GBR, Rn
0000 n 00010010
15 12 11 8 7 0
gbr ← SignExtend32(GBR);op1 ← gbr;Rn ← Register(op1);
458PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STC.L GBR, @-RnDescription
This instruction stores GBR to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of GBR is written to the effective address.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STC.L GBR, @-Rn
0100 n 00010011
15 12 11 8 7 0
gbr ← SignExtend32(GBR);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, gbr);op1 ← address;Rn ← Register(op1);
459PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STS FPSCR, RnDescription
This floating-point instruction copies FPSCR to Rn.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
STS FPSCR, Rn
0000 n 01101010
15 12 11 8 7 0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← fps;Rn ← Register(op1);
460PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STS.L FPSCR, @-RnDescription
This floating-point instruction stores FPSCR to memory using register indirect withpre-decrement addressing. Rn is pre-decremented by 4 to give the effective address.The 32-bit value of FPSCR is written to the effective address.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STS.L FPSCR, @-Rn
0100 n 01100010
15 12 11 8 7 0
sr ← ZeroExtend32(SR);fps ← ZeroExtend32(FPSCR);op1 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;value ← fps;address ← ZeroExtend32(op1 - 4);WriteMemory32(address, value);op1 ← address;Rn ← Register(op1);
461PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STS FPUL, RnDescription
This floating-point instruction copies FPUL to Rn.
Operation
Exceptions
SLOTFPUDIS, FPUDIS
STS FPUL, Rn
0000 n 01011010
15 12 11 8 7 0
sr ← ZeroExtend32(SR);fpul ← SignExtend32(FPUL);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;op1 ← fpul;Rn ← Register(op1);
462PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STS.L FPUL, @-RnDescription
This floating-point instruction stores FPUL to memory using register indirect withpre-decrement addressing. Rn is pre-decremented by 4 to give the effective address.The 32-bit value of FPUL is written to the effective address.
Operation
Exceptions
SLOTFPUDIS, FPUDIS, WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STS.L FPUL, @-Rn
0100 n 01010010
15 12 11 8 7 0
sr ← ZeroExtend32(SR);fpul ← SignExtend32(FPUL);op1 ← SignExtend32(Rn);IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;IF (FpuIsDisabled(sr))
THROW FPUDIS;address ← ZeroExtend32(op1 - 4);WriteMemory32(address, fpul);op1 ← address;Rn ← Register(op1);
463PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STS MACH, RnDescription
This instruction copies MACH to Rn.
Operation
STS MACH, Rn
0000 n 00001010
15 12 11 8 7 0
mach ← SignExtend32(MACH);op1 ← mach;Rn ← Register(op1);
464PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STS.L MACH, @-RnDescription
This instruction stores MACH to memory using register indirect withpre-decrement addressing. Rn is pre-decremented by 4 to give the effective address.The 32-bit value of MACH is written to the effective address.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STS.L MACH, @-Rn
0100 n 00000010
15 12 11 8 7 0
mach ← SignExtend32(MACH);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, mach);op1 ← address;Rn ← Register(op1);
465PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STS MACL, RnDescription
This instruction copies MACL to Rn.
Operation
STS MACL, Rn
0000 n 00011010
15 12 11 8 7 0
macl ← SignExtend32(MACL);op1 ← macl;Rn ← Register(op1);
466PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STS.L MACL, @-RnDescription
This instruction stores MACL to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of MACL is written to the effective address.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STS.L MACL, @-Rn
0100 n 00010010
15 12 11 8 7 0
macl ← SignExtend32(MACL);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, macl);op1 ← address;Rn ← Register(op1);
467PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
STS PR, RnDescription
This instruction copies PR to Rn.
Operation
Note
STS PR, Rn
0000 n 00101010
15 12 11 8 7 0
pr ← SignExtend32(PR’);op1 ← pr;Rn ← Register(op1);
468PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
STS.L PR, @-RnDescription
This instruction stores PR to memory using register indirect with pre-decrementaddressing. Rn is pre-decremented by 4 to give the effective address. The 32-bitvalue of PR is written to the effective address.
Operation
Exceptions
WADDERR, WTLBMISS, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
STS.L PR, @-Rn
0100 n 00100010
15 12 11 8 7 0
pr ← SignExtend32(PR’);op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1 - 4);WriteMemory32(address, pr);op1 ← address;Rn ← Register(op1);
469PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SUB Rm, RnDescription
This instruction subtracts Rm from Rn and places the result in Rn.
Operation
Note
SUB Rm, Rn
0011 n m 1000
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);op2 ← op2 - op1;Rn ← Register(op2);
470PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SUBC Rm, RnDescription
This instruction subtracts Rm and the T-bit from Rn and places the result in Rn. Theborrow from the subtraction is placed in the T-bit.
Operation
Note
SUBC Rm, Rn
0011 n m 1010
15 12 11 8 7 4 3 0
t ← ZeroExtend1(T);op1 ← ZeroExtend32(SignExtend32(Rm));op2 ← ZeroExtend32(SignExtend32(Rn));op2 ← (op2 - op1) - t;t ← op2< 32 FOR 1 >;Rn ← Register(op2);T ← Bit(t);
471PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SUBV Rm, RnDescription
This instruction subtracts Rm from Rn and places the result in Rn. The T-bit is set to1 if the subtraction result is outside the 32-bit signed range, otherwise the T-bit isset to 0.
Operation
Note
SUBV Rm, Rn
0011 n m 1011
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);op2 ← op2 - op1;
t ← INT ((op2 < (- 231)) OR (op2 ≥ 231));Rn ← Register(op2);T ← Bit(t);
472PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
SWAP.B Rm, RnDescription
This instruction swaps the values of the lower 2 bytes in Rm and places the result inRn. Bits [0,7] take the value of bits [8,15]. Bits [8,15] take the value of bits [0,7]. Bits[16,31] are unchanged.
Operation
Note
SWAP.B Rm, Rn
0110 n m 1000
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← ((op1< 16 FOR 16 > << 16) ∨ (op1< 0 FOR 8 > << 8)) ∨ op1< 8 FOR 8 >;Rn ← Register(op2);
473PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
SWAP.W Rm, RnDescription
This instruction swaps the values of the 2 words in Rm and places the result in Rn.Bits [0,15] take the value of bits [16,31]. Bits [16,31] take the value of bits [0,15].
Operation
Note
SWAP.W Rm, Rn
0110 n m 1001
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← (op1< 0 FOR 16 > << 16) ∨ op1< 16 FOR 16 >;Rn ← Register(op2);
474PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
TAS.B @RnDescription
This instruction performs a test-and-set operation on the byte data at the effectiveaddress specified in Rn. It begins by purging the operand cache block containing theaccessed memory location. The 8 bits of data at the effective address are read frommemory. If the read data is 0 the T-bit is set, otherwise the T-bit is cleared. Thehighest bit of the 8-bit data (bit 7) is set, and the result is written back to thememory at the same effective address.
This test-and-set is atomic from the CPU perspective. This instruction cannot beinterrupted during its operation.
Operation
Exceptions
WADDERR, WTLBMISS, READPROT, WRITEPROT, FIRSTWRITE
Note
The TAS.B instruction guarantees atomicity of access to all components of the corebut not necessarily the entire address space. Refer to the system architecturemanual of the appropriate product to determine the properties of individual targetsin the address map.
TAS.B @Rn
0100 n 00011011
15 12 11 8 7 0
op1 ← SignExtend32(Rn);address ← ZeroExtend32(op1);OCBP(address)value ← ZeroExtend8(ReadMemory8(address));t ← INT (value = 0);value ← value ∨ (1 << 7);WriteMemory8(address, value);T ← Bit(t);
475PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
TRAPA #immDescription
This instruction causes a pre-execution trap. The value of the zero-extended 8-bitimmediate i is used by the handler launch sequence to characterize the trap.
Operation
Exceptions
ILLSLOT, TRAP
Note
An ILLSLOT exception is raised if this instruction is executed in a delay slot.
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
TRAPA #imm
11000011 i
15 8 7 0
imm ← ZeroExtend8(i);IF (IsDelaySlot())
THROW ILLSLOT;THROW TRAP, imm;
476PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
TST Rm, RnDescription
This instruction performs a bitwise AND of Rm with Rn. If the result is 0, the T-bit isset, otherwise the T-bit is cleared.
Operation
Note
TST Rm, Rn
0010 n m 1000
15 12 11 8 7 4 3 0
op1 ← SignExtend32(Rm);op2 ← SignExtend32(Rn);t ← INT ((op1 ∧ op2) = 0);T ← Bit(t);
477PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
TST #imm, R0Description
This instruction performs a bitwise AND of R0 with the zero-extended 8-bitimmediate i. If the result is 0, the T-bit is set, otherwise the T-bit is cleared.
Operation
Note
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
TST #imm, R0
11001000 i
15 8 7 0
r0 ← SignExtend32(R0);imm ← ZeroExtend8(i);t ← INT ((r0 ∧ imm) = 0);T ← Bit(t);
478PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
TST.B #imm, @(R0, GBR)Description
This instruction performs a bitwise test of an immediate constant with 8 bits of dataheld in memory. The effective address is calculated by adding R0 and GBR. The 8bits of data at the effective address are read. A bitwise AND is performed of the readdata with the zero-extended 8-bit immediate i. If the result is 0, the T-bit is set,otherwise the T-bit is cleared.
Operation
Exceptions
RADDERR, RTLBMISS, READPROT
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
TST.B #imm, @(R0, GBR)
11001100 i
15 8 7 0
r0 ← SignExtend32(R0);gbr ← SignExtend32(GBR);imm ← ZeroExtend8(i);address ← ZeroExtend32(r0 + gbr);value ← ZeroExtend8(ReadMemory8(address));t ← ((value ∧ imm) = 0);T ← Bit(t);
479PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
XOR Rm, RnDescription
This instruction performs a bitwise XOR of Rm with Rn and places the result in Rn.
Operation
Note
XOR Rm, Rn
0010 n m 1010
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← ZeroExtend32(Rn);op2 ← op2 ⊕ op1;Rn ← Register(op2);
480PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
XOR #imm, R0Description
This instruction performs a bitwise XOR of R0 with the zero-extended 8-bitimmediate i and places the result in R0.
Operation
Note
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
XOR #imm, R0
11001010 i
15 8 7 0
r0 ← ZeroExtend32(R0);imm ← ZeroExtend8(i);r0 ← r0 ⊕ imm;R0 ← Register(r0);
481PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
XOR.B #imm, @(R0, GBR)Description
This instruction performs a bitwise XOR of an immediate constant with 8 bits ofdata held in memory. The effective address is calculated by adding R0 and GBR. The8 bits of data at the effective address are read. A bitwise XOR is performed of theread data with the zero-extended 8-bit immediate i. The result is written back to the8 bits of data at the same effective address.
Operation
Exceptions
WADDERR, WTLBMISS, READPROT, WRITEPROT, FIRSTWRITE
Note
The effective address calculation is performed using 32-bit zero extension to causewrap around if the address-space bounds are exceeded.
The ‘#imm’ in the assembly syntax represents the immediate i after zero extension.
XOR.B #imm, @(R0, GBR)
11001110 i
15 8 7 0
r0 ← SignExtend32(R0);gbr ← SignExtend32(GBR);imm ← ZeroExtend8(i);address ← ZeroExtend32(r0 + gbr);value ← ZeroExtend8(ReadMemory8(address));value ← value ⊕ imm;WriteMemory8(address, value);
482PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
XTRCT Rm, RnDescription
This instruction extracts the lower 16-bit word from Rm and the upper 16-bit wordfrom Rn, swaps their order, and places the result in Rn. Bits [0,15] of Rn take thevalue of bits [16,31] of the original Rn. Bits [16,31] of Rn take the value of bits [0,15]of Rm.
Operation
Note
XTRCT Rm, Rn
0010 n m 1101
15 12 11 8 7 4 3 0
op1 ← ZeroExtend32(Rm);op2 ← ZeroExtend32(Rn);op2 ← op2< 16 FOR 16 > ∨ (op1< 0 FOR 16 > << 16);Rn ← Register(op2);
PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
10Pipelining
The SH-4 CPU core is a dual-issue superscalar pipelining microprocessor. Thissection gives a high-level description of the way in which this particularimplementation of the SH4 architecture executes instructions. Definitions in thissection may not be applicable to SH-4 Series models other than the SH-4 CPU core.
10.1 PipelinesFigure 33 shows the basic pipelines. Normally, a pipeline consists of five or sixstages: instruction fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA), and write-back (S/FS). An instruction is executed as acombination of basic pipelines. Figure 34 to Figure 38 show the instructionexecution patterns.
484PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Figure 33: Basic pipelines
1. General Pipeline
• Instruction fetch • Instruction decode
• Issue• Register read• Destination address calculation
for PC-relative branch
• Non-memory data access
• Write-back
I D EX
• Operation
NA S
2. General Load/Store Pipeline
• Instruction fetch • Instruction decode
• Issue• Register read
• Memory data access
• Write-back
I D EX
• Address calculation
MA S
3. Special Pipeline
• Instruction fetch • Instruction decode
• Issue• Register read
• Non-memory data access
• Write-back
I D SX
• Operation
NA S
4. Special Load/Store Pipeline
• Instruction fetch • Instruction decode
• Issue• Register read
• Memory data access
• Write-back
I D SX
• Address calculation
MA S
5. Floating-Point Pipeline
• Instruction fetch • Instruction decode
• Issue• Register read
• Computation 2 • Computation 3• Write-back
I D F1
• Computation 1
F2 FS
6. Floating-Point Extended Pipeline
• Instruction fetch • Instruction decode
• Issue• Register read
• Computation 1 • Computation 3• Write-back
I D F0
• Computation 0
F1 F2 FS
• Computation 2
F3
Computation: Takes several cycles
7. FDIV/FSQRT Pipeline
485PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Figure 34: Instruction execution patterns
1. 1-step operation: 1 issue cycleEXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG
I D EX NA S
2. Load/store: 1 issue cycleMOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR
I D EX MA S
3. GBR-based load/store: 1 issue cycleMOV.[BWL]@(d,GBR)
I D SX MA S
4. JMP, RTS, BRAF: 2 issue cyclesI D EX NA S
D EX NA S
5. TST.B: 3 issue cycles
I D SX MA SD SX NA S
D SX NA S
6. AND.B, OR.B, XOR.B: 4 issue cyclesI D SX MA S
D SX NA SD SX NA S
D SX MA S
7. TAS.B: 5 issue cycles
I D EX MA SD EX MA S
D EX NA SD EX NA S
D EX MA S
8. RTE: 5 issue cyclesI D EX NA S
D EX NA SD EX NA S
D EX NA SD EX NA S
9. SLEEP: 4 issue cycles
I D EX NA SD EX NA S
D EX NA SD EX NA S
486PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Figure 35: Instruction execution patterns (continued)
10. OCBI: 1 issue cycleI D EX MA S
MA
11. OCBP, OCBWB: 1 issue cycleI D EX MA S
MAMA
MAMA
12. MOVCA.L: 1 issue cycleI D EX MA S
MAMA
MAMA
MAMA
13. TRAPA: 7 issue cyclesI D EX NA S
D EX NA SD EX NA S
D EX NA SD EX NA S
D EX NA SD EX NA S
14. CR definition: 1 issue cycleLDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR
I D EX NA SSX
SX
15. LDC to GBR: 3 issue cyclesI D EX NA S
DDSX
SX
16. LDC to SR: 4 issue cyclesI D EX NA S
DD
D
SXSX
SX
I D EX MA S
17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle
SXSX
18. LDC.L to GBR: 3 issue cycles
I D EX MA SD
DSX
SX
487PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Figure 36: Instruction execution patterns (continued)
19. LDC.L to SR: 4 issue cyclesI D EX MA S
DD
D
SXSX
SX
20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cyclesI D SX NA S
D SX NA S
21. STC.L from SGR: 3 issue cyclesI D SX NA S
D SX NA SD SX NA S
22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
I D SX NA SD SX MA S
23. STC.L from SGR: 3 issue cyclesI D SX NA S
D SX NA SD SX MA S
24. LDS to PR, JSR, BSRF: 2 issue cyclesI D EX NA S
D SXSX
25. LDS.L to PR: 2 issue cyclesI D EX MA S
D SXSX
26. STS from PR: 2 issue cyclesI D SX NA S
D SX NA S
27. STS.L from PR: 2 issue cycles
I D SX NA SD SX MA S
28. MACH/L definition: 1 issue cycleCLRMAC, LDS to MACH/L
I D EX NA SF1
F1 F2 FS
29. LDS.L to MACH/L: 1 issue cycleI D EX MA S
F1F1 F2 FS
30. STS from MACH/L: 1 issue cycle
I D EX NA S
488PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Figure 37: Instruction execution patterns (continued)
31. STS.L from MACH/L: 1 issue cycleI D EX MA S
32. LDS to FPSCR: 1 issue cycle
I D EX NA SF1
F1F1
F1F1
F1
33. LDS.L to FPSCR: 1 issue cycleI D EX MA S
34. Fixed-point multiplication: 2 issue cyclesDMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W
I D EX NA S (CPU)D EX NA S
f1 (FPU)f1
f1f1 F2 FS
35. MAC.W, MAC.L: 2 issue cyclesI D EX MA S (CPU)
D EX MA S
f1 (FPU)f1
f1f1 F2 FS
36. Single-precision floating-point computation: 1 issue cycleFCMP/EQ,FCMP/GT, FADD,FLOAT,FMAC,FMUL,FSUB,FTRC,FRCHG,FSCHG
I D F1 F2 FS
37. Single-precision FDIV/SQRT: 1 issue cycle
I D F1 F2 FSF3
F1 F2 FS
38. Double-precision floating-point computation 1: 1 issue cycle FCNVDS, FCNVSD, FLOAT, FTRC
I D F1 F2 FSd F1 F2 FS
39. Double-precision floating-point computation 2: 1 issue cycle FADD, FMUL, FSUB
I D F1 F2 FSd F1 F2 FS
d F1 F2 FSd F1 F2 FS
d F1 F2 FS
F1 F2 FS
489PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Figure 38: Instruction execution patterns (continued)
I D F1 F2 FSD F1 F2 FS
40. Double-precision FCMP: 2 issue cyclesFCMP/EQ,FCMP/GT
I D F1 F2 FS
F3F1 F2 F3
41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT
F1 F2d
F1 F2 F3F1 F2 F3
42. FIPR: 1 issue cycleI D F0 F1 F2 FS
43. FTRV: 1 issue cycleF1 F2 FSD F0I
F1 F2 FSd F0F1 F2 FSd F0
F1 F2 FSd F0
Notes: ??
: Locks D-stage
: Register read only
: Locks, but no operation is executed.
: Can overlap another f1, but not another F1.
d
D
??
f1
: Cannot overlap a stage of the same kind, except when two instructions are executed in parallel.
490PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
10.2 Parallel executablesInstructions are categorized into six groups according to the internal function blocksused, as shown in table 8.1. Table 8.2 shows the parallel executable pairs ofinstructions in terms of groups. For example, ADD in the EX group and BRA in theBR group can be executed in parallel.
1. MT Group
CLRT CMP/HI Rm,Rn MOV Rm,Rn
CMP/EQ #imm,R0 CMP/HS Rm,Rn NOP
CMP/EQ Rm,Rn CMP/PL Rn SETT
CMP/GE Rm,Rn CMP/PZ Rn TST #imm,R0
CMP/GT Rm,Rn CMP/STR Rm,Rn TST Rm,Rn
2. EX Group
ADD #imm,Rn MOVT Rn SHLL2 Rn
ADD Rm,Rn NEG Rm,Rn SHLL8 Rn
ADDC Rm,Rn NEGC Rm,Rn SHLR Rn
ADDV Rm,Rn NOT Rm,Rn SHLR16 Rn
AND #imm,R0 OR #imm,R0 SHLR2 Rn
AND Rm,Rn OR Rm,Rn SHLR8 Rn
DIV0S Rm,Rn ROTCL Rn SUB Rm,Rn
DIV0U ROTCR Rn SUBC Rm,Rn
DIV1 Rm,Rn ROTL Rn SUBV Rm,Rn
DT Rn ROTR Rn SWAP.B Rm,Rn
EXTS.B Rm,Rn SHAD Rm,Rn SWAP.W Rm,Rn
EXTS.W Rm,Rn SHAL Rn XOR #imm,R0
EXTU.B Rm,Rn SHAR Rn XOR Rm,Rn
EXTU.W Rm,Rn SHLD Rm,Rn XTRCT Rm,Rn
Table 74: Instruction groups
491PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
MOV #imm,Rn SHLL Rn
MOVA @(disp,PC),R0 SHLL16 Rn
3. BR Group
BF disp BRA disp BT disp
BF/S disp BSR disp BT/S disp
4. LS Group
FABS DRn FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR)
FABS FRn FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn)
FLDI0 FRn FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn)
FLDI1 FRn FMOV.S FRm,@Rn MOV.L Rm,@-Rn
FLDS FRm,FPUL FNEG DRn MOV.L Rm,@Rn
FMOV @(R0,Rm),DRn FNEG FRn MOV.W @(disp,GBR),R0
FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W @(disp,PC),Rn
FMOV @Rm,DRn LDS Rm,FPUL MOV.W @(disp,Rm),R0
FMOV @Rm,XDn MOV.B @(disp,GBR),R0 MOV.W @(R0,Rm),Rn
FMOV @Rm+,DRn MOV.B @(disp,Rm),R0 MOV.W @Rm,Rn
FMOV @Rm+,XDn MOV.B @(R0,Rm),Rn MOV.W @Rm+,Rn
FMOV DRm,@(R0,Rn) MOV.B @Rm,Rn MOV.W R0,@(disp,GBR)
FMOV DRm,@-Rn MOV.B @Rm+,Rn MOV.W R0,@(disp,Rn)
FMOV DRm,@Rn MOV.B R0,@(disp,GBR) MOV.W Rm,@(R0,Rn)
FMOV DRm,DRn MOV.B R0,@(disp,Rn) MOV.W Rm,@-Rn
FMOV DRm,XDn MOV.B Rm,@(R0,Rn) MOV.W Rm,@Rn
FMOV FRm,FRn MOV.B Rm,@-Rn MOVCA.L R0,@Rn
FMOV XDm,@(R0,Rn) MOV.B Rm,@Rn OCBI @Rn
FMOV XDm,@-Rn MOV.L @(disp,GBR),R0 OCBP @Rn
Table 74: Instruction groups
492PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FMOV XDm,@Rn MOV.L @(disp,PC),Rn OCBWB @Rn
FMOV XDm,DRn MOV.L @(disp,Rm),Rn PREF @Rn
FMOV XDm,XDn MOV.L @(R0,Rm),Rn STS FPUL,Rn
FMOV.S @(R0,Rm),FRn MOV.L @Rm,Rn
FMOV.S @Rm,FRn MOV.L @Rm+,Rn
5. FE Group
FADD DRm,DRn FIPR FVm,FVn FSQRT DRn
FADD FRm,FRn FLOAT FPUL,DRn FSQRT FRn
FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn
FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn
FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL
FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL
FDIV DRm,DRn FRCHG FTRV XMTRX,FVn
FDIV FRm,FRn FSCHG
6. CO Group
AND.B #imm,@(R0,GBR) LDS Rm,FPSCR STC SR,Rn
BRAF Rm LDS Rm,MACH STC SSR,Rn
BSRF Rm LDS Rm,MACL STC VBR,Rn
CLRMAC LDS Rm,PR STC.L DBR,@-Rn
CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn
DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn
DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn
FCMP/EQ DRm,DRn LDS.L @Rm+,MACL STC.L SPC,@-Rn
FCMP/GT DRm,DRn LDS.L @Rm+,PR STC.L SR,@-Rn
JMP @Rn LDTLB STC.L SSR,@-Rn
Table 74: Instruction groups
493PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
JSR @Rn MAC.L @Rm+,@Rn+ STC.L VBR,@-Rn
LDC Rm,DBR MAC.W @Rm+,@Rn+ STS FPSCR,Rn
LDC Rm,GBR MUL.L Rm,Rn STS MACH,Rn
LDC Rm,Rp_BANK MULS.W Rm,Rn STS MACL,Rn
LDC Rm,SPC MULU.W Rm,Rn STS PR,Rn
LDC Rm,SR OR.B #imm,@(R0,GBR) STS.L FPSCR,@-Rn
LDC Rm,SSR RTE STS.L FPUL,@-Rn
LDC Rm,VBR RTS STS.L MACH,@-Rn
LDC.L @Rm+,DBR SETS STS.L MACL,@-Rn
LDC.L @Rm+,GBR SLEEP STS.L PR,@-Rn
LDC.L @Rm+,Rp_BANK STC DBR,Rn TAS.B @Rn
LDC.L @Rm+,SPC STC GBR,Rn TRAPA #imm
LDC.L @Rm+,SR STC Rp_BANK,Rn TST.B #imm,@(R0,GBR)
LDC.L @Rm+,SSR STC SGR,Rn XOR.B #imm,@(R0,GBR)
LDC.L @Rm+,VBR STC SPC,Rn
Table 74: Instruction groups
494PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
O: Can be executed in parallel
X: Cannot be executed in parallel
10.3 Execution cycles and pipeline stallingInstruction execution cycles are summarized in Table 76: Execution cycles onpage 501. Penalty cycles due to a pipeline stall or freeze are not considered in thistable.
• Issue rate: Interval between the issue of an instruction and that of the nextinstruction
• Latency: Interval between the issue of an instruction and the generation of itsresult (completion)
• Instruction execution pattern (see Figure 34 to Figure 38)
• Locked pipeline stages
• Interval between the issue of an instruction and the start of locking
• Lock time: Period of locking in machine cycle units
2nd Instruction
MT EX BR LS FE CO
1st Instruction MT O O O O O X
EX O X O O O X
BR O O X O O X
LS O O O X O X
FE O O O O X X
CO X X X X X X
Table 75: Parallel executables
495PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
The instruction execution sequence is expressed as a combination of the executionpatterns shown in Figure 34 to Figure 38. One instruction is separated from thenext by the number of machine cycles for its issue rate. Normally, execution, dataaccess, and write-back stages cannot be overlapped onto the same stages of anotherinstruction; the only exception is when two instructions are executed in parallelunder parallel executables conditions. Refer to (a) through (d) in Figure 39 for somesimple examples.
Latency is the interval between issue and completion of an instruction, and is alsothe interval between the execution of two instructions with an interdependentrelationship. When there is interdependency between two instructions fetchedsimultaneously, the latter of the two is stalled for the following number of cycles:
• (Latency) cycles when there is flow dependency (read-after-write)
• (Latency - 1) or (latency - 2) cycles when there is output dependency(write-after-write)
- Single/double-precision FDIV, FSQRT is the preceding instruction (latency -1) cycles
- The other FE group except above is the preceding instruction (latency - 2)cycles
• 5 or 2 cycles when there is anti-flow dependency (write-after-read), as in thefollowing cases:
- FTRV is the preceding instruction (5 cycle)
- A double-precision FADD, FSUB, or FMUL is the preceding instruction (2cycles)
In the case of flow dependency, latency may be exceptionally increased or decreased,depending on the combination of sequential instructions (Figure 40 (e)).
• When a floating-point (FP) computation is followed by an FP register store, thelatency of the FP computation may be decreased by 1 cycle.
• If there is a load of the shift amount immediately before an SHAD/SHLDinstruction, the latency of the load is increased by 1 cycle.
• If an instruction with a latency of less than 2 cycles, including write-back to anFP register, is followed by a double-precision FP instruction, FIPR, or FTRV, thelatency of the first instruction is increased to 2 cycles.
The number of cycles in a pipeline stall due to flow dependency will vary dependingon the combination of interdependent instructions or the fetch timing (see Figure 40(e)).
496PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Output dependency occurs when the destination operands are the same in apreceding FE group instruction and a following LS group instruction.
For the stall cycles of an instruction with output dependency, the longest latency tothe last write-back among all the destination operands must be applied instead oflatency-2 (see Figure 41 (f)). A stall due to output dependency with respect toFPSCR, which reflects the result of an FP operation, never occurs. For example,when FADD follows FDIV with no dependency between FP registers, FADD is notstalled even if both instructions update the cause field of FPSCR.
Anti-flow dependency can occur only between a preceding double-precision FADD,FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, orFSTS. See Figure 41 (g).
If an executing instruction locks any resource, i.e. a function block that performs abasic operation, a following instruction that happens to attempt to use the lockedresource must be stalled (Figure 42 (h)). This kind of stall can be compensated byinserting one or more instructions independent of the locked resource to separatethe interfering instructions. For example, when a load instruction and an ADDinstruction that references the loaded value are consecutive, the 2-cycle stall of theADD is eliminated by inserting three instructions without dependency. Softwareperformance can be improved by such instruction scheduling.
Other penalties arise in the event of exceptions or external data accesses, as follows.
• Instruction TLB miss: a penalty of 7 CPU clocks
• Instruction access to external memory (instruction cache miss, etc.)
• Data access to external memory (operand cache miss, etc.)
• Data access to a memory-mapped control register. The penalty differs fromregister to register, and depends on the kind of operation (read or write), theclock mode, and the bus use conditions when the access is made.
During the penalty cycles of an instruction TLB miss or external instruction access,no instruction is issued, but execution of instructions that have already been issuedcontinues. The penalty for a data access is a pipeline freeze: that is, the execution ofuncompleted instructions is interrupted until the arrival of the requested data. Thenumber of penalty cycles for instruction and data accesses is largely dependent onthe user’s memory subsystems.
497PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Figure 39: Examples of pipelined execution
(a) Serial execution: non-parallel-executable instructions
ADD R2,R1MOV.L @R4,R5
MOV R1,R2next
SHAD R0,R1ADD R2,R3next
I D EX NA SI D EX NA S
I D ...
1 stall cycle
(b) Parallel execution: parallel-executable and no dependency
I D EX NA SI D EX MA S
(c) Issue rate: multi-step instruction
AND.B#1,@(R0,GBR) I D SX MA S
D SX MA SD SX NA S
D SX NA S
II
(d) Branch
1 issue cycle
1 issue cycle
4 issue cycles
...
I D EX NA SI D EX NA S
2-cycle latency for I-stage of branch destination
1 stall cycleI D
I D EX NA SI D EX NA S
I D EX NA S
BT/S L_farADD R0,R1SUB R2,R3
BT/S L_farADD R0,R1
L_far
I D EX NA SI D
I D
— — —...
No stall
BT L_skipADD #1,R0L_skip:
...
i D E A S
4 stall cycles
EX-group SHAD and EX-group ADD cannot be executed in parallel. Therefore, SHAD is issued first, and the following ADD is recombined with the next instruction.
EX-group ADD and LS-group MOV.L can be executed in parallel. Overlapping of stages in the 2nd instruction is possible.
AND.B and MOV are fetched simultaneously, but MOV is stalled due to resource locking. After the lock is released, MOV is refetched together with the next instruction.
No stall occurs if the branch is not taken.
If the branch is taken, the I-stage of the branch destination is stalled for the period of latency. This stall can be covered with a delay slot instruction which is not parallel-executable with the branch instruction.
Even if the BT/BF branch is taken, the I-stage of the branch destination is not stalled if the displacement is zero.
498PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Figure 40: Examples of pipelined execution (continued)
(e) Flow dependency
I D EX NA SI D EX NA S
MOV R0,R1ADD R2,R1
ADD R2,R1MOV.L @R1,R1next
I D EX NA SI D EX MA Si
I ...
...
...
Zero-cycle latency
1-cycle latency
1 stall cycle
MOV.L @R1,R1ADD R0,R1next
I D EX MA SI DI
EX NA SD
EX NA S
2-cycle latency
1 stall cycle
MOV.L @R1,R1SHAD R1,R2next
FADD FR1,FR2STS FPUL,R1STS FPSCR,R2
I D EX NA SI
4-cycle latency for FPSCR
2 stall cycles
I D F1 F2 FS
I D EX MA SI DI
2-cycle latency
2 stall cycles
EX NA Sd
1-cycle increase
II
I D F1 F2 FSd F1 F2 FS
d F1 F2 FSd F1 F2 FS
F1 F2 FSd F1 F2 FS
EX NA SDEX NA SD
FADD DR0,DR2
7-cycle latency for lower FR8-cycle latency for upper FR
FMOV FR3,FR5FMOV FR2,FR4
FLOAT FPUL,DR0FMOV.S FR1,@-R15
FR3 writeFR2 write
I D F1 F2 FSd F1 F2 FS
I D EX MA S
3-cycle latency for lower FR4-cycle latency for upper FR
FR1 writeFR0 write
FLDI1 FR3FIPR FV0,FV4
FMOV @R1,XD14FTRV XMTRX,FV0
I D EX NA SI D d F0 F1 F2 FS
Zero-cycle latency3-cycle increase
3 stall cycles
I D EX MA SI D d F0 F1 F2 FS
d F0 F1 FSF2d F0 F2F1 FS
d F1F0 F2 FS
2-cycle latency1-cycle increase
3 stall cycles
The following instruction, ADD, is not stalled when executed after an instruction with zero-cycle latency, even if there is dependency.
ADD and MOV.L are not executed in parallel, since MOV.L references the result of ADD as its destination address.
Because MOV.L and ADD are not fetched simultaneously in this example, ADD is stalled for only 1 cycle even though the latency of MOV.L is 2 cycles.
Due to the flow dependency between the load and the SHAD/SHLD shift amount, the latency of the load is increased to 3 cycles.
The latency of FLOAT is decreased by 1 cycle, only if followed by a lower FR store. This decrease does not apply to an upper FR store.
499PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Figure 41: Examples of pipelined execution (continued)
I D EX NA S
I D EX NA SD F1 F2 FS
D F1 F2 FS
(e) Flow dependency (cont)
I
I
LDS R0,FPULFLOAT FPUL,FR0LDS R1,FPULFLOAT FPUL,R1
Effectively 1-cycle latency for consecutive LDS/FLOAT instructions
I D EX NA SD F1 F2 FSI
D F1 F2 FSII D EX NA S
Effectively 1-cycle latency for consecutive FTRC/STS instructions
FTRC FR0,FPULSTS FPUL,R0FTRC FR1,FPULSTS FPUL,R1
(f) Output dependency
D F1 F2 FSI
I DF1 F2 FS
F1 F2 FS
11-cycle latency
9 stall cycles = latency (11) - 2The registers are written-back in program order.
D F1 F2 FSId F1 F2 FS
d F1 F2 FSd F1 F2 FS
d F1 F2 FS
F1 F2 FSEX NA SI D
7-cycle latency for lower FR8-cycle latency for upper FR
6 stall cycles = longest latency (8) - 2
FR2 writeFR3 write
D F1 F2 FSId F1 F2 FS
d F1 F2 FSd F1
F0F0
F0F0 F2 FS
(g) Anti-flow dependency
EX MA SI D1 stall cycle
D F1 F2 FSId F1 F2 FS
d F1 F2 FSd F1 F2 FS
EX NA SI D2 stall cycles
d F1 F2 FSF1 F2 FS
FSQRT FR4
FMOV FR0,FR4
FADD DR0,DR2
FMOV FR0,FR3
FTRV XMTRX,FV0
FMOV @R1,XD0
FADD DR0,DR2
FMOV FR4,FR1
F3
500PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Figure 42: Examples of pipelined execution (continued)
(h) Resource conflict
I D F1 F2 FSF3
F1 F2 FS
D F1 F2 FSID F1 F2 FSI
D F1 F2 FSI
I D F1 F2 FS
F1 stage locked for 1 cycle
Latency1 cycle/issue
1 stall cycle (F1 stage resource conflict)
FDIV FR7
FMAC FR0,FR8,FR9FMAC FR0,FR10,FR11FMAC FR0,FR12,FR13FMAC FR0,FR14,FR15
FIPR FV8,FV0FADD FR15,FR4
I D F1F0 F2 FSI D F1 F2 FS
1 stall cycle
LDS.L @R15+,PR I D EX MA FSD SX
SXSX NA S
SX NA SDI
3 stall cycles
STC GBR,R2
FADD DR0,DR2 I D F1 F2 FSd F1 F2 FS
d F1 F2 FSd F1 F2 FS
d F1 F2 FS
F1 F2 FSEX MA Sf1
EX MA SDf1
f1 F2 FSf1 F2 FS
I D5 stall cycles
MAC.W @R1+,@R2+
I D EX MA Sf1
f1f1 F2 FS
f1 F2 FSI
f1D EX MA Sf1
D EX MA S
f1 F2 FSf1 F2 FS
F1 F2 FSd F1 F2 FS
d F1 F2 FSd F1 F2 FS
d F1 F2 FS
F1 ...
I D3 stall cycles
1 stall cycle
2 stall cycles
MAC.W @R1+,@R2+
MAC.W @R1+,@R2+
FADD DR4,DR6
f1 stage can overlap preceding f1, but F1 cannot overlap f1.
D EX MA S
#1 #2 #3 ... #10 #11 #12
D
501PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Data transferinstructions
1 EXTS.B Rm,Rn EX 1 1 #1 - - -
2 EXTS.W Rm,Rn EX 1 1 #1 - - -
3 EXTU.B Rm,Rn EX 1 1 #1 - - -
4 EXTU.W Rm,Rn EX 1 1 #1 - - -
5 MOV Rm,Rn MT 1 0 #1 - - -
6 MOV #imm,Rn EX 1 1 #1 - - -
7 MOVA @(disp,PC),R0 EX 1 1 #1 - - -
8 MOV.W @(disp,PC),Rn LS 1 2 #2 - - -
9 MOV.L @(disp,PC),Rn LS 1 2 #2 - - -
10 MOV.B @Rm,Rn LS 1 2 #2 - - -
11 MOV.W @Rm,Rn LS 1 2 #2 - - -
12 MOV.L @Rm,Rn LS 1 2 #2 - - -
13 MOV.B @Rm+,Rn LS 1 1/2 #2 - - -
14 MOV.W @Rm+,Rn LS 1 1/2 #2 - - -
15 MOV.L @Rm+,Rn LS 1 1/2 #2 - - -
16 MOV.B @(disp,Rm),R0 LS 1 2 #2 - - -
17 MOV.W @(disp,Rm),R0 LS 1 2 #2 - - -
18 MOV.L @(disp,Rm),Rn LS 1 2 #2 - - -
19 MOV.B @(R0,Rm),Rn LS 1 2 #2 - - -
20 MOV.W @(R0,Rm),Rn LS 1 2 #2 - - -
21 MOV.L @(R0,Rm),Rn LS 1 2 #2 - - -
22 MOV.B @(disp,GBR),R0 LS 1 2 #3 - - -
23 MOV.W @(disp,GBR),R0 LS 1 2 #3 - - -
Table 76: Execution cycles
502PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Data transferinstructions
24 MOV.L @(disp,GBR),R0 LS 1 2 #3 - - -
25 MOV.B Rm,@Rn LS 1 1 #2 - - -
26 MOV.W Rm,@Rn LS 1 1 #2 - - -
27 MOV.L Rm,@Rn LS 1 1 #2 - - -
28 MOV.B Rm,@-Rn LS 1 1/1 #2 - - -
29 MOV.W Rm,@-Rn LS 1 1/1 #2 - - -
30 MOV.L Rm,@-Rn LS 1 1/1 #2 - - -
31 MOV.B R0,@(disp,Rn) LS 1 1 #2 - - -
32 MOV.W R0,@(disp,Rn) LS 1 1 #2 - - -
33 MOV.L Rm,@(disp,Rn) LS 1 1 #2 - - -
34 MOV.B Rm,@(R0,Rn) LS 1 1 #2 - - -
35 MOV.W Rm,@(R0,Rn) LS 1 1 #2 - - -
36 MOV.L Rm,@(R0,Rn) LS 1 1 #2 - - -
37 MOV.B R0,@(disp,GBR) LS 1 1 #3 - - -
38 MOV.W R0,@(disp,GBR) LS 1 1 #3 - - -
39 MOV.L R0,@(disp,GBR) LS 1 1 #3 - - -
40 MOVCA.L R0,@Rn LS 1 3-7 #12 MA 4 3-7
41 MOVT Rn EX 1 1 #1 - - -
42 OCBI @Rn LS 1 1-2 #10 MA 4 1-2
43 OCBP @Rn LS 1 1-5 #11 MA 4 1-5
44 OCBWB @Rn LS 1 1-5 #11 MA 4 1-5
45 PREF @Rn LS 1 1 #2 - - -
46 SWAP.B Rm,Rn EX 1 1 #1 - - -
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
503PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Data transferinstructions
47 SWAP.W Rm,Rn EX 1 1 #1 - - -
48 XTRCT Rm,Rn EX 1 1 #1 - - -
Fixed-pointarithmeticinstructions
49 ADD Rm,Rn EX 1 1 #1 - - -
50 ADD #imm,Rn EX 1 1 #1 - - -
51 ADDC Rm,Rn EX 1 1 #1 - - -
52 ADDV Rm,Rn EX 1 1 #1 - - -
53 CMP/EQ #imm,R0 MT 1 1 #1 - - -
54 CMP/EQ Rm,Rn MT 1 1 #1 - - -
55 CMP/GE Rm,Rn MT 1 1 #1 - - -
56 CMP/GT Rm,Rn MT 1 1 #1 - - -
57 CMP/HI Rm,Rn MT 1 1 #1 - - -
58 CMP/HS Rm,Rn MT 1 1 #1 - - -
59 CMP/PL Rn MT 1 1 #1 - - -
60 CMP/PZ Rn MT 1 1 #1 - - -
61 CMP/STR Rm,Rn MT 1 1 #1 - - -
62 DIV0S Rm,Rn EX 1 1 #1 - - -
63 DIV0U EX 1 1 #1 - - -
64 DIV1 Rm,Rn EX 1 1 #1 - - -
65 DMULS.L Rm,Rn CO 2 4/4 #34 F1 4 2
66 DMULU.L Rm,Rn CO 2 4/4 #34 F1 4 2
67 DT Rn EX 1 1 #1 - - -
68 MAC.L @Rm+,@Rn+ CO 2 2/2/4/4 #35 F1 4 2
69 MAC.W @Rm+,@Rn+ CO 2 2/2/4/4 #35 F1 4 2
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
504PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Fixed-pointarithmeticinstructions
70 MUL.L Rm,Rn CO 2 4/4 #34 F1 4 2
71 MULS.W Rm,Rn CO 2 4/4 #34 F1 4 2
72 MULU.W Rm,Rn CO 2 4/4 #34 F1 4 2
73 NEG Rm,Rn EX 1 1 #1 - - -
74 NEGC Rm,Rn EX 1 1 #1 - - -
75 SUB Rm,Rn EX 1 1 #1 - - -
76 SUBC Rm,Rn EX 1 1 #1 - - -
77 SUBV Rm,Rn EX 1 1 #1 - - -
Logicalinstructions
78 AND Rm,Rn EX 1 1 #1 - - -
79 AND #imm,R0 EX 1 1 #1 - - -
80 AND.B #imm,@(R0,GBR) CO 4 4 #6 - - -
81 NOT Rm,Rn EX 1 1 #1 - - -
82 OR Rm,Rn EX 1 1 #1 - - -
83 OR #imm,R0 EX 1 1 #1 - - -
84 OR.B #imm,@(R0,GBR) CO 4 4 #6 - - -
85 TAS.B @Rn CO 5 5 #7 - - -
86 TST Rm,Rn MT 1 1 #1 - - -
87 TST #imm,R0 MT 1 1 #1 - - -
88 TST.B #imm,@(R0,GBR) CO 3 3 #5 - - -
89 XOR Rm,Rn EX 1 1 #1 - - -
90 XOR #imm,R0 EX 1 1 #1 - - -
91 XOR.B #imm,@(R0,GBR) CO 4 4 #6 - - -
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
505PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Shiftinstructions
92 ROTL Rn EX 1 1 #1 - - -
93 ROTR Rn EX 1 1 #1 - - -
94 ROTCL Rn EX 1 1 #1 - - -
95 ROTCR Rn EX 1 1 #1 - - -
96 SHAD Rm,Rn EX 1 1 #1 - - -
97 SHAL Rn EX 1 1 #1 - - -
98 SHAR Rn EX 1 1 #1 - - -
99 SHLD Rm,Rn EX 1 1 #1 - - -
100 SHLL Rn EX 1 1 #1 - - -
101 SHLL2 Rn EX 1 1 #1 - - -
102 SHLL8 Rn EX 1 1 #1 - - -
103 SHLL16 Rn EX 1 1 #1 - - -
104 SHLR Rn EX 1 1 #1 - - -
105 SHLR2 Rn EX 1 1 #1 - - -
106 SHLR8 Rn EX 1 1 #1 - - -
107 SHLR16 Rn EX 1 1 #1 - - -
Branchinstructions
108 BF disp BR 1 2 (or 1) #1 - - -
109 BF/S disp BR 1 2 (or 1) #1 - - -
110 BT disp BR 1 2 (or 1) #1 - - -
111 BT/S disp BR 1 2 (or 1) #1 - - -
112 BRA disp BR 1 2 #1 - - -
113 BRAF Rn CO 2 3 #4 - - -
114 BSR disp BR 1 2 #14 SX 3 2
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
506PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Branchinstructions
115 BSRF Rn CO 2 3 #24 SX 3 2
116 JMP @Rn CO 2 3 #4 - - -
117 JSR @Rn CO 2 3 #24 SX 3 2
118 RTS CO 2 3 #4 - - -
Systemcontrolinstructions
119 NOP MT 1 0 #1 - - -
120 CLRMAC CO 1 3 #28 F1 3 2
121 CLRS CO 1 1 #1 - - -
122 CLRT MT 1 1 #1 - - -
123 SETS CO 1 1 #1 - - -
124 SETT MT 1 1 #1 - - -
125 TRAPA #imm CO 7 7 #13 - - -
126 RTE CO 5 5 #8 - - -
127 SLEEP CO 4 4 #9 - - -
128 LDTLB CO 1 1 #2 - - -
129 LDC Rm,DBR CO 1 3 #14 SX 3 2
130 LDC Rm,GBR CO 3 3 #15 SX 3 2
131 LDC Rm,Rp_BANK CO 1 3 #14 SX 3 2
132 LDC Rm,SR CO 4 4 #16 SX 3 2
133 LDC Rm,SSR CO 1 3 #14 SX 3 2
134 LDC Rm,SPC CO 1 3 #14 SX 3 2
135 LDC Rm,VBR CO 1 3 #14 SX 3 2
136 LDC.L @Rm+,DBR CO 1 1/3 #17 SX 3 2
137 LDC.L @Rm+,GBR CO 3 3/3 #18 SX 3 2
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
507PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
138 LDC.L @Rm+,Rp_BANK CO 1 1/3 #17 SX 3 2
139 LDC.L @Rm+,SR CO 4 4/4 #19 SX 3 2
140 LDC.L @Rm+,SSR CO 1 1/3 #17 SX 3 2
141 LDC.L @Rm+,SPC CO 1 1/3 #17 SX 3 2
142 LDC.L @Rm+,VBR CO 1 1/3 #17 SX 3 2
143 LDS Rm,MACH CO 1 3 #28 F1 3 2
144 LDS Rm,MACL CO 1 3 #28 F1 3 2
145 LDS Rm,PR CO 2 3 #24 SX 3 2
146 LDS.L @Rm+,MACH CO 1 1/3 #29 F1 3 2
147 LDS.L @Rm+,MACL CO 1 1/3 #29 F1 3 2
148 LDS.L @Rm+,PR CO 2 2/3 #25 SX 3 2
149 STC DBR,Rn CO 2 2 #20 - - -
150 STC SGR,Rn CO 3 3 #21 - - -
151 STC GBR,Rn CO 2 2 #20 - - -
152 STC Rp_BANK,Rn CO 2 2 #20 - - -
153 STC SR,Rn CO 2 2 #20 - - -
154 STC SSR,Rn CO 2 2 #20 - - -
155 STC SPC,Rn CO 2 2 #20 - - -
156 STC VBR,Rn CO 2 2 #20 - - -
157 STC.L DBR,@-Rn CO 2 2/2 #22 - - -
158 STC.L SGR,@-Rn CO 3 3/3 #23 - - -
159 STC.L GBR,@-Rn CO 2 2/2 #22 - - -
160 STC.L Rp_BANK,@-Rn CO 2 2/2 #22 - - -
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
508PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
161 STC.L SR,@-Rn CO 2 2/2 #22 - - -
162 STC.L SSR,@-Rn CO 2 2/2 #22 - - -
163 STC.L SPC,@-Rn CO 2 2/2 #22 - - -
164 STC.L VBR,@-Rn CO 2 2/2 #22 - - -
165 STS MACH,Rn CO 1 3 #30 - - -
166 STS MACL,Rn CO 1 3 #30 - - -
167 STS PR,Rn CO 2 2 #26 - - -
168 STS.L MACH,@-Rn CO 1 1/1 #31 - - -
169 STS.L MACL,@-Rn CO 1 1/1 #31 - - -
170 STS.L PR,@-Rn CO 2 2/2 #27 - - -
Single-precisionfloating-pointinstructions
171 FLDI0 FRn LS 1 0 #1 - - -
172 FLDI1 FRn LS 1 0 #1 - - -
173 FMOV FRm,FRn LS 1 0 #1 - - -
174 FMOV.S @Rm,FRn LS 1 2 #2 - - -
175 FMOV.S @Rm+,FRn LS 1 1/2 #2 - - -
176 FMOV.S @(R0,Rm),FRn LS 1 2 #2 - - -
177 FMOV.S FRm,@Rn LS 1 1 #2 - - -
178 FMOV.S FRm,@-Rn LS 1 1/1 #2 - - -
179 FMOV.S FRm,@(R0,Rn) LS 1 1 #2 - - -
180 FLDS FRm,FPUL LS 1 0 #1 - - -
181 FSTS FPUL,FRn LS 1 0 #1 - - -
182 FABS FRn LS 1 0 #1 - - -
183 FADD FRm,FRn FE 1 3/4 #36 - - -
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
509PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
184 FCMP/EQ FRm,FRn FE 1 2/4 #36 - - -
185 FCMP/GT FRm,FRn FE 1 2/4 #36 - - -
186 FDIV FRm,FRn FE 1 12/13 #37 F3 2 10
F1 11 1
187 FLOAT FPUL,FRn FE 1 3/4 #36 F1 2 2
188 FMAC FR0,FRm,FRn FE 1 3/4 #36 - - -
189 FMUL FRm,FRn FE 1 3/4 #36 - - -
190 FNEG FRn LS 1 0 #1 - - -
191 FSQRT FRn FE 1 11/12 #37 F3 2 9
F1 10 1
192 FSUB FRm,FRn FE 1 3/4 #36 - - -
193 FTRC FRm,FPUL FE 1 3/4 #36 - - -
194 FMOV DRm,DRn LS 1 0 #1 - - -
195 FMOV @Rm,DRn LS 1 2 #2 - - -
196 FMOV @Rm+,DRn LS 1 1/2 #2 - - -
197 FMOV @(R0,Rm),DRn LS 1 2 #2 - - -
198 FMOV DRm,@Rn LS 1 1 #2 - - -
199 FMOV DRm,@-Rn LS 1 1/1 #2 - - -
200 FMOV DRm,@(R0,Rn) LS 1 1 #2 - - -
Double-precisionfloating-pointinstructions
201 FABS DRn LS 1 0 #1 - - -
202 FADD DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6
203 FCMP/EQ DRm,DRn CO 2 3/5 #40 F1 2 2
204 FCMP/GT DRm,DRn CO 2 3/5 #40 F1 2 2
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
510PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
205 FCNVDS DRm,FPUL FE 1 4/5 #38 F1 2 2
206 FCNVSD FPUL,DRn FE 1 (3, 4)/5 #38 F1 2 2
207 FDIV DRm,DRn FE 1 (24, 25)/26
#41 F3 2 21
F1 20 3
208 FLOAT FPUL,DRn FE 1 (3, 4)/5 #38 F1 2 2
209 FMUL DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6
210 FNEG DRn LS 1 0 #1 - - -
211 FSQRT DRn FE 1 (23, 24)/25
#41 F3 2 20
F1 19 3
212 FSUB DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6
213 FTRC DRm,FPUL FE 1 4/5 #38 F1 2 2
FPU systemcontrolinstructions
214 LDS Rm,FPUL LS 1 1 #1 - - -
215 LDS Rm,FPSCR CO 1 4 #32 F1 3 3
216 LDS.L @Rm+,FPUL CO 1 1/2 #2 - - -
217 LDS.L @Rm+,FPSCR CO 1 1/4 #33 F1 3 3
218 STS FPUL,Rn LS 1 3 #1 - - -
219 STS FPSCR,Rn CO 1 3 #1 - - -
220 STS.L FPUL,@-Rn CO 1 1/1 #2 - - -
221 STS.L FPSCR,@-Rn CO 1 1/1 #2 - - -
Graphicsaccelerationinstructions
222 FMOV DRm,XDn LS 1 0 #1 - - -
223 FMOV XDm,DRn LS 1 0 #1 - - -
224 FMOV XDm,XDn LS 1 0 #1 - - -
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
511PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Note: 1 See Table 74 for the instruction groups.
2 Latency “L1/L2...”: Latency corresponding to a write to each register, includingMACH/MACL/FPSCR.Example:MOV.B @Rm+, Rn “1/2”: The latency for Rm is 1 cycle, and the latency forRn is 2 cycles.
3 Branch latency: Interval until the branch destination instruction is fetched
4 Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement,and 1 for a zero displacement.
5 Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latencyfor FR [n+1], L2 that for FR [n], and L3 that for FPSCR.
6 FTRV latency “(L1, L2, L3, L4)/L5”: L1 is the latency for FR [n], L2 that for FR[n+1], L3 that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.
7 Latency “L1/L2/L3/L4” of MAC.L and MAC.W instructions: L1 is the latency forRm, L2 that for Rn, L3 that for MACH, and L4 that for MACL.
225 FMOV @Rm,XDn LS 1 2 #2 - - -
226 FMOV @Rm+,XDn LS 1 1/2 #2 - - -
227 FMOV @(R0,Rm),XDn LS 1 2 #2 - - -
228 FMOV XDm,@Rn LS 1 1 #2 - - -
229 FMOV XDm,@-Rm LS 1 1/1 #2 - - -
230 FMOV XDm,@(R0,Rn) LS 1 1 #2 - - -
231 FIPR FVm,FVn FE 1 4/5 #42 F1 3 1
232 FRCHG FE 1 1/4 #36 - - -
233 FSCHG FE 1 1/4 #36 - - -
234 FTRV XMTRX,FVn FE 1 (5, 5, 6,7)/8
#43 F0 2 4
F1 3 4
Functionalcategory
No InstructionInstruction
groupIssuerate
LatencyExecution
pattern
Lock
Sta
ge
Sta
rt
Cyc
les
Table 76: Execution cycles
512PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
8 Latency “L1/L2” of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.Linstructions: L1 is the latency for MACH, and L2 that for MACL.
9 Execution pattern: The instruction execution pattern number (see figure 8.2)
10 Lock/stage: Stage locked by the instruction
11 Lock/start: Locking start cycle; 1 is the first D-stage of the instruction.
12 Lock/cycles: Number of cycles locked.
Exceptions:
1 When a floating-point computation instruction is followed by an FMOV store, anSTS FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency ofthe floating-point computation is decreased by 1 cycle.
2 When the preceding instruction loads the shift amount of the following SHAD/SHLD, the latency of the load is increased by 1 cycle.
3 When an LS group instruction with a latency of less than 3 cycles is followed bya double-precision floating-point instruction, FIPR, or FTRV, the latency of thefirst instruction is increased to 3 cycles.
Example:In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2cycles.
4 When MAC*/MUL*/DMUL* is followed by an STS.L MAC*, @-Rn instruction,the latency of MAC*/MUL*/DMUL* is 5 cycles.
5 In the case of consecutive executions of MAC*/MUL*/DMUL*, the latency isdecreased to 2 cycles.
6 When an LDS to MAC* is followed by an STS.L MAC*, @-Rn instruction, thelatency of the LDS to MAC* is 4 cycles.
7 When an LDS to MAC* is followed by MAC*/MUL*/DMUL*, the latency of theLDS to MAC* is 1 cycle.
8 When an FSCHG or FRCHG instruction is followed by an LS group instructionthat reads or writes to a floating-point register, the aforementioned LS groupinstruction[s] cannot be executed in parallel.
9 When a single-precision FTRC instruction is followed by an STS FPUL, Rninstruction, the latency of the single-precision FTRC instruction is 1 cycle.
PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
AAddress list
Module Register P4 addressArea 7
addressa SizePower-on
resetManualreset
Sleep StandbySyncclock
CCN PTEH 0xFF00 0000 0x1F00 0000 32 0x0000 0000 0x0000 0000 Held Held Iclk
CCN PTEL 0xFF00 0004 0x1F00 0004 32 0x0000 0000 0x0000 0000 Held Held Iclk
CCN TTB 0xFF00 0008 0x1F00 0008 32 0x0000 0000 0x0000 0000 Held Held Iclk
CCN TEA 0xFF00 000C 0x1F00 000C 32 0x0000 0000 0x0000 0000 Held Held Iclk
CCN MMUCR 0xFF00 0010 0x1F00 0010 32 0x0000 0000 0x0000 0000 Held Held Iclk
CCN BASRA 0xFF00 0014 0x1F00 0014 8 Undefined Held Held Held Iclk
CCN BASRB 0xFF00 0018 0x1F00 0018 8 Undefined Held Held Held Iclk
CCN CCR 0xFF00 001C 0x1F00 001C 32 0x0000 0000 0x0000 0000 Held Held Iclk
CCN TRA 0xFF00 0020 0x1F00 0020 32 0x0000 0000 0x0000 0000 Held Held Iclk
CCN EXPEVT 0xFF00 0024 0x1F00 0024 32 0x0000 0000 0x0000 0020 Held Held Iclk
CCN INTEVT 0xFF00 0028 0x1F00 0028 32 0x0000 0000 Held Held Held Iclk
CCN QACR0 0xFF00 0038 0x1F00 0038 32 Undefined Undefined Held Held Iclk
CCN QACR1 0xFF00 003C 0x1F00 003C 32 Undefined Undefined Held Held Iclk
UBC BARA 0xFF20 0000 0x1F20 0000 32 Undefined Held Held Held Iclk
UBC BAMRA 0xFF20 0004 0x1F20 0004 8 Undefined Held Held Held Iclk
Table 77: Address list
514PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Note: The address map for peripheral devices is contained in the system manual for thepart.
a. With control registers, the above addresses in the physical page number field can beaccessed by means of a TLB setting. When these addresses are referenced directlywithout using the TLB, operations are limited.
PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
BInstructionprefetch sideeffects
The SH-4 is provided with an internal buffer for holding pre-read instructions, andalways performs pre-reading. Therefore, program code must not be located in thelast 20-byte area of any memory space. If program code is located in these areas, thememory area will be exceeded and a bus access for instruction pre-reading may beinitiated. A case in which this is a problem is shown below.
Table 78 illustrates a case in which the instruction (ADD) indicated by the programcounter (PC) and the address 0x0400002 instruction prefetch are executedsimultaneously. Note that the program branches to an area outside Area 1 afterexecuting the following JMP instruction and delay slot instruction.
In this case, the program flow is unpredictable, and a bus access (instructionprefetch) to Area 1 may be initiated.
Address
0x03FFFFF8 ADD R1,R4 PC (program counter)
0x03FFFFFA JMP @R2
Area 0 0x03FFFFFC NOP
0x03FFFFFE NOP
Area 1 0x040000000
0x40000002 Instruction prefetch address
Table 78: Example
516PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
Instruction prefetch side effects
1 It is possible that an external bus access caused by an instruction prefetch mayresult in misoperation of an external device, such as a FIFO, connected to thearea concerned.
2 If there is no device to reply to an external bus request caused by an instructionprefetch, hangup will occur.
Remedies
1 These illegal instruction fetches can be avoided by using the MMU.
2 The problem can be avoided by not locating program code in the last 20 bytes ofany area.
PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
Index
AADD 209, 214-215, 261ADDC 216ADDV 217AND 186, 199-201, 218-220AND.B 220
BBackus-Naur Form xiiiBF 221, 223BNF. See Backus-naur Form.BRA 225BRAF 226BREAK 227BRK 227BSR 209, 228BSRF 209, 230BT 231, 233
CCMPGT 267
DDIV0S 247DIV1 249
DMULS.L 250DMULU.L 251DT 252
EELSE 192EXTS.B 253EXTS.W 254EXTU.B 255EXTU.W 256
FFABS 257-258FABS.D 204FABS.S 204FADD 211, 259-261FADD.D 204FADD.S 204FCMPEQ.D 205FCMPEQ.S 205FCMPGT.D 205FCMPGT.S 205FCNV.DS 205FCNV.SD 205FCNVDS 268, 270
518PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
FCNVSD 269-270FDIV 271-273FDIV.D 204FDIV.S 204FIPR 275-276, 278FIPR.S 206, 276FLDI 280-281FLDS 279FLOAT 282-284FLOAT.LD 205FLOAT.LS 205FMAC 285FMAC.S 205, 286-287FMOV 290-293, 295-298, 300-304,
306-315FMOV.S 296-298, 300, 310-312FMUL 316-318FMUL.D 204FMUL.S 204FNEG 319-320FNEG.D 205FNEG.S 205FOR 184-185, 188, 192, 196, 199, 201FPU 194, 203, 261, 264, 267, 270, 273,
276-277, 284, 286, 318, 325, 329,331-332, 334-335
FPUDIS 257-260, 262-263, 265-266,268-269, 271-272, 276, 279-283, 285,290-292, 294-297, 299-303, 305-317,319-324, 326-328, 330-331, 334,353-356, 459-462
FPUEXC 212FPUL 194, 268-269, 279, 282-284, 326,
330-331, 355-356, 461-462FROM 192FSQRT 323-325FSQRT.D 205FSQRT.S 205
FSTS 326FSUB 327-329FSUB.D 204FSUB.S 204FTRC 330-331FTRC.DL 205FTRC.SL 205FTRV 333-334, 336FTRV.S 206, 334Function
Bit(i) 188DataAccessMiss(address) 197, 200ExecuteProhibited(address) 197FABS_D 204FABS_S 204FADD_D 204FADD_S 204, 212FCMPEQ_D 205FCMPEQ_S 205FCMPGT_D 205FCMPGT_S 205FCNV_DS 205FCNV_SD 205FDIV_D 204FDIV_S 204FIPR_S 206FLOAT_LD 205FLOAT_LS 205FloatRegister32(i) 189FloatRegister64(i) 189FloatRegisterMatrix32(a) 189FloatRegisterPair32(a) 189FloatRegisterVector32(a) 189FloatValue32(r) 189FloatValue64(r) 189FloatValueMatrix32(r) 189FloatValuePair32(r) 189FloatValueVector32(r) 189FMAC_S 205FMUL_D 204FMUL_S 204
519PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
FNEG_D 205FNEG_S 205FpuCauseE() 203FpuCauseI() 203FpuCauseO() 203FpuCauseU() 203FpuCauseV() 203FpuCauseZ() 203FpuEnableI() 203FpuEnableO() 203FpuEnableU() 203FpuEnableV() 203FpuEnableZ() 203FpuFlagI() 203FpuFlagO() 203FpuFlagU() 203FpuFlagV() 203FpuFlagZ() 203FpuIsDisabled() 203FSQRT_D 205FSQRT_S 205FSUB_D 204FSUB_S 204FTRC_DL 205FTRC_SL 205FTRV_S 206InstFetchMiss(address) 197InstInvalidateMiiss(address) 197IsLittleEndian() 198MalformedAddress(address) 197,
199-201MMU() 197, 199-201OCBI(address) 202OCBP(address) 202OCBWB(address) 202PrefetchMemory(address) 200PREFO(address) 200, 202ReadMemoryLown(address) 200ReadMemoryn(address) 198-199ReadMemoryPairn(address) 198-199ReadProhibited(address) 197, 199-200Register(i) 188
SignExtendn(i) 187WriteControlRegister(index, value) 201WriteMemoryLown(address, value) 201WriteMemoryn(address, value) 200-201WriteMemoryPairn(address, value)
200-201WriteProhibited(address) 197, 201ZeroExtendn(i) 187
IIADDERR 226, 230IF 192, 199-201, 212ILLSLOT 208-209, 221-223, 225-226,
228, 230-233, 337-338, 390, 401, 403,425, 427, 442, 475
INT 186ISA 207-208, 226, 230, 338
JJMP 337JSR 209, 338
LLDC 339-352, 443-449LDC.L 340, 346-352LDS 209, 348, 353-362LDS.L 354, 356, 358, 360, 362
MMAC.L 365MAC.W 367MACH 194, 235, 250-251, 357-358, 365,
367, 407-409, 463-464MACL 194, 235, 250-251, 359-360, 365,
367, 407-409, 465-466MD 194MEM 195-196, 199, 201MMU 197-201
520PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F
MOV 369-402MOV.B 371-380MOV.L 381-391MOV.W 392-402MOVA 403MOVCA.L 404MOVT 406MUL.L 407MULS.W 408MULU.W 409
NNEG 410NEGC 411NOT 186, 200, 413
OOCBI 202, 414OCBP 202, 415OCBWB 202, 416OR 186, 199, 201, 417-419OR.B 419
PP0 204-206PC 194-195, 207-209, 221, 223, 225-226,
228, 230-231, 233, 390, 401, 403PR 194, 207-209, 228, 230, 338,
361-362, 427, 467-468PREF 420PREFO 200, 202
RRADDERR 199READPROT 199Register
DR 195
FPSCR 194, 202-206, 212, 259-261,263, 266, 268-273, 276, 282-283,285-286, 316-318, 321-325,327-331, 334-335, 353-354,459-460
FPSCR.CAUSE.E 203FPSCR.CAUSE.I 203FPSCR.CAUSE.O 203FPSCR.CAUSE.U 203FPSCR.CAUSE.V 203FPSCR.CAUSE.Z 203FPSCR.DN 261, 263, 266, 270, 273,
276, 286, 318, 325, 329, 331,334-335
FPSCR.ENABLE.I 203FPSCR.ENABLE.O 203FPSCR.ENABLE.U 203FPSCR.ENABLE.V 203FPSCR.ENABLE.Z 203FPSCR.FLAG.I 203FPSCR.FLAG.O 203FPSCR.FLAG.U 203FPSCR.FLAG.V 203FPSCR.FLAG.Z 203FPSCR.FR 321FPSCR.RM 259-260, 268-269,
271-272, 282-283, 285, 316-317,323-324, 327-328, 330-331
FPSCR.SZ 322FR 285, 321GBR 194, 220, 339-352, 374, 379, 384,
389, 395, 400, 419, 443-458, 478,481
MTRX 195R 219-220, 239, 295, 300, 306, 309,
312, 315, 373-375, 378-380,383-384, 388-389, 394-396,399-400, 402-404, 418-419,477-478, 480-481
Rm 214, 216-218, 238, 240-243,246-247, 249-251, 253-256,307-315, 339-362, 365, 367, 369,
521PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.ADCS 7182230F SH-4 CPU Core Architecture
371-373, 376-378, 380-383,385-388, 391-394, 396-399, 402,407-411, 413, 417, 430, 433,443-449, 469-473, 476, 479, 482
SR 194, 202-203SR.FD 203
REPEAT 192ROTCL 421ROTCR 422ROTL 423ROTR 424RTLBMISS 199
SSHAD 430SHAL 431SHAR 432SHLD 433SHLL 434-437SHLR 438-442SLEEP 201-202SLOTFPUDIS 257-260, 262-263,
265-266, 268-269, 271-272, 276,279-283, 285, 290-292, 294-297,299-303, 305-317, 319-324, 326-328,330, 334, 353-356, 459-462
STC 450-458STC.L 450-456, 458STEP 192STS 209, 459-468STS.L 460, 462, 464, 466, 468
SUB 329, 469SUBC 470SUBV 471SuperH SH-Series
documentation suitenotation xiii
SWAP.B 472SWAP.W 473SZ 322
TTAS.B 474The appendix 515THROW 193, 199, 201, 212TRAPA 475TST 476-478TST.B 478
UUNDEFINED 190-191
WWRITEPROT 201WTLBMISS 201
XYZXMTRX 333-334XOR 186, 479-481XOR.B 481XTRCT 482
522PRELIMINARY DATA
STMicroelectronics and Hitachi, Ltd.SH-4 CPU Core Architecture ADCS 7182230F