[SiC-En-2013-17] Challenges Regarding Parallel Connection of SiC JFETs

8/22/2019 [SiC-En-2013-17] Challenges Regarding Parallel Connection of SiC JFETs

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013 1449

Challenges Regarding Parallel Connectionof SiC JFETs

Dimosthenis Peftitsis, Student Member, IEEE, Roman Baburske, Jacek Rabkowski, Member, IEEE, Josef Lutz,Georg Tolstoy, Student Member, IEEE, and Hans-Peter Nee, Senior Member, IEEE

AbstractState-of-the-art silicon carbide switches have currentratings that are not sufficiently high to be used in high-power con-verters. It is, therefore, necessary to connect several switches inparallel in order to reach sufficient current capabilities. An inves-tigation of parallel-connected normally ON silicon carbide JFETsis presented in this paper. The device parameters that play themost important role for the parallel connection are the pinch-offvoltage, the gatesource reverse breakdown voltage, the spread inthe on-state resistances, and the variations in static transfer char-acteristics of the devices. Moreover, it is experimentally shown thata fifth factor affecting the parallel connection of the devices is theparasitic inductances of the circuit layout. The temperature depen-dence of the gatesource reverse breakdown voltages is analyzedfor two different designs of silicon carbide JFETs. If the spreadin the pinch-off and gatesource reverse breakdown voltages issufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of thegate voltages to exceed the breakdown voltage. A solution to thisproblem using individual gate circuits for the JFETs is given. Theswitching performance of two pairs of parallel-connected deviceswith different combinations of parameters is compared employingtwo different gate-driver configurations. Three different circuitlayouts are considered and the effect of the parasitic inductancesis experimentally investigated. It is found that using a single gatecircuit for the two mismatched JFETs may improve the switchingperformance and therefore the distribution of the switching losses

significantly. Based on the measured switching losses, it is alsoclear that regardless of the design of the gate drivers, the lowesttotal switching losses for the devices are obtained when they aresymmetrically placed.

Index TermsJunction field-effect transistor (JFET), parallel-connected switches, pinch-off voltage, reverse breakdown voltageof the gate, silicon carbide (SiC).

Manuscript received November 8, 2011; revised March 26, 2012; acceptedJune 18, 2012. Date of current version October 12, 2012. This paper was pre-sented in part at the International Conference on Power Electronics-EnergyConversion Congress and Exposition Asia 2011, Jeju, Korea, MayJune 2011.Recommended for publication by Associate Editor E. Santi.

D. Peftitsis, J. Rabkowski, G. Tolstoy, and H.-P. Nee are with the Laboratoryof Electrical Energy Conversion Laboratory, School of Electrical Engineering,KTH Royal Institute of Technology, SE-10044 Stockholm, Sweden (e-mail:[email protected]; [email protected]; [email protected]; [email protected]).

R. Baburske and J. Lutz are with the Faculty of Electrical Engineering andInformation Technology, Chemnitz University of Technology, 09126 Chem-nitz, Germany (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2206611

I. INTRODUCTION

SILICON carbide (SiC) JFETs are highly promising for

future application in, for instance, hybrid electric vehi-

cles [1][3], converters for photovoltaic power generation [4],

power-factor correction circuits [5][7], and high-power ap-

plications such as static synchronous compensators, HVDC

transmission [8], and high-power or high-power-density mo-

tor drives [9][12]. The reasons to the wide area of applica-

tion are that the SiC JFET can exhibit low on-state losses, low

switching losses, and high-temperature capability simultane-ously [13][17]. In many applications, high current ratings are

required. The available chip sizes at present and in a foresee-

able future will, however, not be sufficient for single-chip high-

current switches. The reason to this is that this would result

in very low fabrication yields. Consequently, the only ways to

proceed are to build multichip modules [18][21] or to parallel-

connect several single-chip components. In both cases, it is

essential to keep track of both steady-state and transient current

sharing of the parallel-connected chips.

There are, basically, four device parameters affecting these

issues. The first one is the on-state resistance, which must have

a low spread and a positive temperature coefficient for stable

steady-state current sharing. Based on the experience from the

measurements presented in the following, however, this does

not seem to be a major problem even if the current sharing

is influenced to some extent. The second one is the pinch-off

voltage, which determines at what gate voltage the device enters

the forward conduction region [22]. Obviously, a spread in this

parameter among a set of parallel-connected chips will have a

considerable effect on the transient current sharing during the

turn-on and turn-off transitions. The third critical parameter is

the reverse breakdown voltage of the gate, Vbr,g [23], which is

the maximum allowable reverse-bias voltage that can be applied

to the gate. If the spread in the two latter parameters is too large,

there might be no possibility for a stable off-state operation, asone chip may be driven into gate breakdown before another chip

is turned OFF. This problem can be solved, to some extent, by

sorting the chips with respect to the relevant parameters, but as

will be explained in the following, the spread in the pinch-off

voltage may anyway cause significant variations in switching

losses among the parallel-connected chips unless the sorting is

very rigorous. Additionally, depending on the device design, the

temperature dependence of the breakdown voltage may affect

both the sorting criteria and the high-temperature characteristics

of the parallel-connected switch. Furthermore, the difference in

static transfer characteristics among the devices also counts as

an important parameter which affects the performance of the

0885-8993/$31.00 2012 IEEE


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1450 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 3, MARCH 2013

parallel connection. Even if the devices have exactly the same

pinch-off voltages, there might be differences in the transfer

characteristics, i.e., different transconductances [24].

A fifth factor, which is not a device parameter, that affects the

parallel connection is the placement of the devices in the circuit

layout. In particular, a symmetrical placement of the devices

might result in uniformly distributed parasitic inductances not

only between the JFETs themselves, but also between the JFETs

and other components of the circuit (e.g., diodes, etc.) [25][28].

An investigation on the parallel connection of normally OFF

SiC JFETs and SiC bipolar junction transistors is presented

in [29]. That study, which is the first of its kind and a first ap-

proach to shed light on problems with parallel connection of SiC

devices, basically focuses on the dependence of various static

and dynamic characteristics of the devices on the temperature.

In this paper, therefore, an extensive experimental analysis of

problems with parallel connection of normally ON SiC JFETs

is performed. Additionally, possible remedies to the observed

adverse phenomena are suggested. It is well known that gate

drivers for power semiconductor devices can profoundly influ-ence the switching performance of the devices. In this paper,

therefore, a recently suggested gate driver [30] is used in two

different configurations which potentially could influence the

effectiveness of the parallel connection. The temperature de-

pendence of the pinch-off and the reverse breakdown voltage

of the gate and the importance of keeping a safety margin be-

tween those two voltages are analyzed in Section II. This section

also presents the parameter spread and temperature dependence

of the on-state resistance and the IV characteristics of the

SiC JFETs. Section III shows the switching performance of

the parallel-connected SiC JFETs having the same and differ-

ent Vbr,g . This was performed using three different main-circuitlayouts in order to investigate the influence of parasitic elements

of the main circuit. The switching losses of parallel-connected

SiC JFETs are treated in Section IV. Finally, a discussion on

problems with parallel connection of normally ON SiC JFETs

is given in Section V. Section VI concludes this paper.

II. TEMPERATURE DEPENDENCE AND SPREAD

OF SiC JFET PARAMETERS

Before presenting the switching performance of parallel-

connected SiC JFETs, it makes sense to investigate the tempera-

ture dependence and spread of different parameters influencing

the parallel connection. First, the temperature dependences ofthe pinch-off voltage, Vbr,g , and the on-state resistance are in-

vestigated. Next, it is shown that there might also be variations

in the IVcharacteristics among different devices. From these

investigations, the potential problems regarding parallel con-

nection of SiC JFETs are also identified.

Forthe presentedinvestigation, twotypesof normally ON SiC

JFETs have been used, which both were available in engineering

samples at the time when the experiments were performed. The

first one (Supplier 1) is the so-called lateral channel JFET

(LCJFET) and a graphical schematic of its structure is shown

in Fig. 1. The range of the typical pinch-off voltages of this

JFET design is between 16 and 26 V, while Vbr,g equals

Fig. 1. Graphical illustration of the cross section of the LCJFET.

Fig.2. Graphical illustration of thecross sectionof thedepletion-mode verticaltrench JFET.

approximately

34 V. A nice feature of this structure, especiallywith respect to the clamping during the blanking time, is the

antiparallel body diode which is formed by the p+ source side,

the n drift region, and the n++ drain. Nevertheless, the forward

voltage drop of the body diode is higher than the on-state voltage

drop of the channel, which mainly conducts the current in the

reverse direction.

The second JFET design (Supplier 2) that has been taken into

account in this study is the depletion-mode vertical trench JFET

as shown in Fig. 2. This device can be either normally ON or

normally OFF depending on the thicknessof the vertical channel

and the doping levels of the structure. Typically, the pinch-

off voltage of this JFET equals 5 V, while Vbr,g is typically

between 19 and 29 V. This JFET design has no body diode,but the load current can flow in the reverse direction through the

channel [8], [31]. Table I summarizes the basic parameters of

the SiC JFETs which have been used for the measurements in

the section.

A. Temperature Dependence of the Pinch-Off and

the Reverse Breakdown Voltage of the Gate

It is not only the pinch-off voltage, but also Vbr,g that affect

reliable and stable operation of parallel-connected normally ON

JFETs. The margin between these two voltages must be large

enough in order to ensure that when the negative gatesource


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PEFTITSIS et al.: CHALLENGES REGARDING PARALLEL CONNECTION OF SiC JFETs 1451

TABLE IBASIC PARAMETERS OF THE SiC JFETS

Fig. 3. Static transfer characteristics of SiC JFET No. 126 for two differenttemperatures.

voltage is supplied, the device is properly turned OFF without

forcing the gate into reverse breakdown.

Since SiC devices potentially have excellent high-

temperature properties [20], it makes sense to investigate the

temperature dependences of the pinch-off voltage and Vbr,g .

From experiments, on the one hand, it is found that the pinch-

off voltage is almost temperature independent as shown from

the static transfer characteristics in Fig. 3. Vbr,g , on the other

hand, might have (depending on the type of the device) a nega-

tive temperature coefficient, which means that its absolute value

is decreasing when the temperature is increasing. In Fig. 4, ex-

perimental results showing the temperature dependence ofVbr,g

for two different LCJFETs are presented. It is obvious fromFig. 4 that the safe operating region (indicated with short ver-

tical lines in the graphs) is reduced when the temperature is

increased.

A serious problem is, therefore, faced when two or more

devices with different values ofVbr,g or even different pinch-off

voltages are connected in parallel. This problem is accentuated

at high temperatures, because the reverse breakdown voltage

of the gate is reduced at high temperatures for LCJFETs. As

shown in Fig. 4, the operating region in the off-state might be

very small or even negative if the parallel-connected devices

are unfavorably matched. A solution to this problem could be

to use a supply voltage to the gate driver that is more negative

Fig. 4. Pinch-off and breakdown voltage margin for two temperatures(a) 23 C and (b) 150 C for devices No. 126 and No. 154.

Fig. 5. Gate driver of the normally ON SiC JFET showing the solution to thebreakdown voltage variations with temperature.

than Vbr,g , and to limit the leakage current through the gate by

means of a resistor.

A circuit for normally ON SiC JFETs that realizes this method

has already been presented in [30]. The operating principle of

the circuit is mainly based on the choice of the negative voltage

supplyVs and the DRpCparallel network. The parallel network

consists of a high-value resistor Rp , a diode D, and a capacitor

C. During the on-state of the device, the buffer output voltage

Vg equals zero and the JFET is conducting a drain current. When

the turn-off process starts, the buffer output voltage Vg is equal

to the supply voltage Vs and a high negative gate current peak is

provided through the capacitor Cand the gate resistor Rg to the

gatesource junction of the device. This current is shown withthe dashed line in Fig. 5. As the supply voltage Vs is chosen to

a more negative voltage than Vbr,g , the parasitic capacitance of

the gatesource junction Cgs is charged to a voltage that equals

Vbr,g . Simultaneously, the gate capacitor C is also charged and

the voltage drop across it equals the difference between the

supply voltage Vs and Vbr,g .

During steady-state operation in the off-state, a low leakage

current is only required in order to keep the JFET OFF. This

current is supplied through the resistor Rp as shown with the

solid line in Fig. 5. If the value ofRp is chosen with care, it

is, therefore, impossible to cause a junction breakdown due to

a high continuous negative gate leakage current. Nevertheless,


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20 40 60 80 100 120 140 160-22.8

-22.7

-22.6

-22.5

-22.4

-22.3

-22.2

Temperature [oC]

Reversebreakdownvo

ltageofthegate,

Vbr,g

[V]

Fig. 6. Measurements of the temperature dependence of the reverse break-down voltage of the gate of a vertical trench JFET.

it is possible to adjust the switching speed to any desired speed

by selecting an adequate value ofRg .

For the depletion-mode vertical trench JFETs, Vbr,g is almost

unaffected by variations in temperature. In Fig. 6, results from

measurements on temperature dependence ofVbr,g for vertical

trench JFETs are shown. In this case, the temperature depen-

dence is almost negligible. This means that the margin between

the pinch-off voltage and Vbr,g is almost unaffected by vari-

ations in temperature. In the opinion of the authors, this is a

significant advantage of the vertical trench JFETs compared to

LCJFETs. Due to this fact, and to the unavailability of new ver-

sions of LCJFETs, only vertical trench JFETs are considered inthe following.

B. On-State Resistance Variation

It is not only the reverse breakdown voltage of the gate and the

pinch-off voltage of the SiC JFET which affect the effectiveness

of the parallel connection. Due to the slightly different doping

concentrations and the slightly different channel widths of the

devices, there may also be differences on the on-state resis-

tances. This kind of variations among various devices also plays

a crucial role when SiC JFETs are connected in parallel. Es-pecially, during steady-state operation, these variations might

cause mismatches in the current sharing through the devices

which results in different on-state losses and, consequently, dif-

ferent temperature rises among the JFETs. Fig. 7 shows the

on-state resistance variations with respect to the temperature for

four different SiC JFET devices. As can be seen, the spread of

the on-state resistances among the JFETs approximately (but

note entirely, see SiC JFETs Nos. 3 and 4) remains constant as

the temperature increases.

Not surprisingly, the sorting of the SiC JFETs with respect

to the on-state resistances seems to be the solution to overcome

the mismatches in the steady-state current sharing.

20 40 60 80 100 120 140 16080

100

120

140

160

180

200

Temperature [oC]

On-stateresistance[m

]

On-state resistance variation with temperature

SiC JFET No1

SiC JFET No2

SiC JFET No3

SiC JFET No4

Fig. 7. On-state resistance variation with temperature for four different SiCJFET devices.

C. Variation in Static Transfer Characteristics

The IV transfer characteristics of the normally ON SiC

JFETs might be different among different devices. Fig. 8(a)

and (b) shows the static transfer characteristics at various gate

source voltages for two different samples of the same type of

normally ON SiC JFET. Ideally, the IVwaveforms for these

devices should be identical when looking at the same gate

source voltage. However, comparing two traces in Fig. 8(a) and

(b), it is obvious that there is a spread in the IV curves. For

instance, for the gatesource voltage Vgs = 5 V, the device

shown in Fig. 8(a) is still conducting the current, while the

device in Fig. 8(b) has been turned OFF. Moreover, comparing

the traces for Vgs = 4 V [heavy-width line in Fig. 8(a) and

(b)], it is clear that the characteristics of the two devices are very

different, even if both are in the on-state. A certain spread can beobserved at every value ofVgs shown in the graphs resulting in

different values of transconductance for the SiC JFETs. These

dissimilarities affect the effectiveness of the parallel-connected

devices, especially during the switching transitions. At turn-on,

for instance, the device with the lowest transconductance turns

ON slightly slower than the other one.

III. EXPERIMENTAL RESULTS

Apart from the investigationof the steady-state characteristics

at elevated temperatures and generally the various parameters

of the devices which play an important role for the feasibil-

ity of the parallel connection, it is also important to study theswitching performance of the devices when they are parallel-

connected. Parallel connection of normally ON SiC JFETs has

been experimentally investigated by using the devices listed in

Table II.

In total, three SiC JFETs have been selected with respect to

their reverse breakdown voltages of their gates Vbr,g and they

were tested in pairs using a standard double-pulse experimental

setup. The reason for choosing Vbr,g as a sorting criterion is that

this quantity can be measured easily. In Fig. 9, experimental

results indicating that differences in Vbr,g are correlated to dif-

ferences in the pinch-off voltages of the SiC JFETs are shown.

Fig. 9 shows the static transfer characteristics of two devices


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0 1 2 3 4 5 6-2

0

2

4

6

8

10

12

14

16

18

20

Drain-source voltage, Vds [V]

Draincurrent,Id[A]

Vgs=0 V

Vgs=-1 V

Vgs=-2 V

Vgs=-3 V

Vgs=-4 V

Vgs=-5 V

0 1 2 3 4 5 6-2

0

2

4

6

8

10

12

14

16

18

20

Drain-source voltage, Vds [V]

Draincurrent,Id

[A]

Vgs=0 V

Vgs=-1 V

Vgs=-2 V

Vgs=-3 V

Vgs=-4 V

Vgs=-5 V

(a) (b)

Fig. 8. Static transfer characteristics at various gatesource voltages for two different SiC JFET devices: (a) device No 21 and (b) device No 50.

TABLE IIREVERSE BREAKDOWN VOLTAGES OF THE GATE OF THE DUT

-6 -5.5 -5 -4.5 -4 -3.50

50

100

150

200

Gate-source voltage [V]

Draincurrent[mA]

JFET No. 50, Vbr,g

= -28.0 V

JFET No. 45, Vbr,g

= -21.1 V

Fig. 9. Measured static transfer characteristicsshowingthe relevance betweenthe reverse breakdown voltage of the gate and the pinch-off voltage.

having a difference of approximately 7 V in Vbr,g . The corre-

sponding difference in the pinch-off voltages was found to be

0.5 V. The device with the less negative Vbr,g also has the less

negative pinch-off voltage. Even if this is not a solid statisti-

cal proof of the correlation between the Vbr,g and the pinch-off

voltage, it is a strong indication that the Vbr,g can be used as a

sorting criterion. Table II shows the reverse breakdown voltages

of the gates of the devices under test (DUT). As can be seen

from this table, two of the DUTs (Nos. 20 and 50) have approx-

imately the same reverse breakdown voltage of the gates. The

other JFET, No. 21, has a different reverse breakdown voltage

of the gate compared to the other two devices. Thus, two sets of

measurements have been performed, one using the devices withapproximately the same Vbr,g (Nos. 20 and 50), and the other

one using devices Nos. 50 and 21, which have different values

ofVbr,g .

Theschematic of the double-pulse setup is shown in Fig. 10. It

consists of a direct voltage source Vdc , a SiC Schottky diode, an

inductor L, and the two parallel-connected SiC JFETs. Fig. 11

shows a graphical schematic of the circuit layout. A gate driver

which was proposed in [30] is used and two different configura-

tions of this driver have been designed and used for the parallel-

connected SiC JFETs. The first configuration uses two separate

DRpCparallel networks (each one drives a single JFET), which

both are fed from the same power supply as shown in Fig. 10(a).

On the other hand, a single DRpC network is employed inthe second gate-driver design and it is fed from a single volt-

age supply as shown in Fig. 10(b). In the second configuration,

both parallel-connected JFETs are driven by the same network.

The stray capacitances of the two SiC JFETs, which affect their

switching performance, are also shown in Fig. 10. Photographs

of the double DRpC and the single DRpC gate-driver circuits

are shown in Fig. 12(a) and (b), respectively. Table III summa-

rizes the parameters of the experimental setup which are the

same for both gate-driver configurations.

The parameters of the gate drivers have been adapted in such

a way that the switching performance of the drivers themselves

will be identical for the double and the single DRpCnetworks.


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Rg1 Rg2

Rp1 Rp2

D1 D2C1 C2

J1 J2

Vdc

LSiC Schoky

Diode

-Vs

0

CL,parCD,par

Cdg,1 Cdg,2

Cgs,1 Cgs,2

Cds,1Cds,2

-Vs

0

IC driver IC driver

J1 J2

Vdc

LSiC Schoky

Diode

-Vs

0

CL,parCD,par

Cdg,1 Cdg,2

Cgs,1 Cgs,2

Cds,1Cds,2

Rg,s

Rp,s

Ds

Cs

IC driver

(a) (b)

Fig. 10. Schematic diagram of the double-pulse test setup (a) with double DRpC networks and (b) with a single DRpC network.

Fig. 11. Graphical schematic of the test-circuit layout. (a) Top-side view. (b) Front-side view.

This practically means that the gate capacitor for the single

DRpC networkCs equals two times the capacitor for the dou-

ble DRpC networkC1 (or C2), while the gate resistor for the

single one Rg, s has been adjusted taking into account the inter-

nal resistance of the integrated-circuit driver (IC driver) Rdrv ,

and the resistance of the SiC JFET package Rpac , as well (see

Fig. 13). It is therefore obvious thatRg, s will not be equal to half

ofRg1 (or Rg2). Instead, the total resistance from the IC driver

to the gatesource junction of the JFET for the single DRpC

equals half of the corresponding one for the double DRpCnet-

work. Fig. 13(a) and (b) shows the resistive paths during the

turn-on process for the two gate-driver configurations. From

these drawings, it is clear that the resistances which are shown

inside the dashed line boxes are fixed and thus they cannot be

adjusted. However, as already analyzed previously, the external

gate resistors Rg1 , Rg2 , and Rg, s can be properly adjusted in

order to reach a desirable switching performance of the drivers.

The parameters of the gate drivers are shown in Table IV.

From Fig. 11, it is clear that the physical dimensions of the

gate circuits are small because the terminals of the JFETs are


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Fig. 12. Gate-drive circuit prototypes (a) with a doubleDRpC network and (b) with a single DRpC network.

TABLE IIIPARAMETERS OF THE EXPERIMENTAL SETUP

-Vs

0

Rg1 RpacRdrv

-Vs

0

Rg2 RpacRdrv

IC driver

IC driver

-Vs

0

Rg,s

Rpac

RdrvRpac

IC driver

(b)(a)

Fig. 13. Resistive pathsfor thetwogate-driver configurations (a)witha doubleDRpC network and (b) with a single DRpC network.

TABLE IVPARAMETERS OF THE GATE-DRIVER CIRCUITS

soldered directly to the terminals of the gate-driver printed cir-

cuit boards. Moreover, it is clear from Fig. 12(a) and (b) that the

paths of the gate current in the two gate-driver designs are quite

similar. This leads to the conclusion that 1) the stray inductance

of the gate circuit is very low, and 2) no significant difference in

stray inductance for the two gate-driver designs is anticipated.

Various experimental results showing the switching perfor-

mance and the switching losses under the parallel connection

are presented in the following. Section III-A deals with the

Fig. 14. Graphical illustration of the first circuit layout, L1.

investigation of the DUT with the same Vbr,g and Section III-

B presents the experiments on the DUT with different Vbr,g .

Both the double and the single DRpC network gate drivers

have been tested in the two different cases of parallel-connected

SiC JFETs. Furthermore, the positions of the DUTs have been

changed in order to investigate the effect of the parasitic in-ductances of the circuit layout on the switching performance of

the parallel-connected SiC JFETs. In particular, three different

circuit layouts regarding the placement of the SiC JFETs and

Schottky diode have been used. A graphical illustration of the

first layout, L1, is shown in Fig. 14. The SiC JFET No. 50 is

placed closer to the Schottky diode, while the SiC JFET No. 20

(or No. 21 in the case where the JFETs havedifferent breakdown

voltages of the gates) is mounted on the right side of No. 50.

The second circuit layout L2 is depicted in Fig. 15 where the

device No. 20 (or No. 21) is placed closer to the Schottky diode

and No. 50 on the right side of the circuit. A symmetrical place-

ment of the devices is shown in Fig. 16 with the third circuit


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Fig. 15. Graphical illustration of the second circuit layout, L2.

Fig. 16. Graphical illustration of the third circuit layout, L3, showing a sym-metrical placement of the devices.

layout L3. The SiC Schottky diode is mounted in the middle of

the circuit with the two JFETs placed aside. In this case, it is

believed that the parasitic inductances of the circuit are equally

distributed among the JFETs, while for the first two cases the

parasitic inductance is lower between the diode and the JFET

which is placed closer to it. It must be noted that the inductor

L is connected in the middle of the distance between the two

DUTs for all three cases.

A. DUT With the Same Reverse Breakdown

Voltage of the Gate

In this section, the parallel connection of two SiC JFET de-

vices having the same Vbr,g is presented. The tests were subdi-

vided into two main sets, one for each gate-driver configuration

(single and doubleDRpCnetworks), whereas each of these sets

is also subdivided into three subcases based on the placement of

1.35 1.4 1.45 1.5 1.55

x 10-6

0

10

20

30

Currents[A]

Current transients for 50,20 with double DRC (layout L1)

(a)

4 4.05 4.1 4.15 4.2 4.25

x 10-6

0

10

20

30

Currents[A]

(b)

SiC JFET No.50

SiC JFET No.20

1.05 1.1 1.15 1.2 1.25

x 10-6

0

10

20

30

Currents[A]


(c)

3.7 3.75 3.8 3.85 3.9 3.95

x 10-6

0

10

20

30

Currents[A]

(d)

SiC JFET No.20

SiC JFET No.50

1 1.1 1.2

x 10-6

0

10

20

30

Currents[A]


(e) Time [s]

3.65 3.7 3.75 3.8 3.85

x 10-6

0

10

20

30

Currents[A]

(f) Time [s]

SiC JFET No.20

SiC JFET No.50

Fig. 17. Switching transients for the SiC JFETs having the same reversebreakdown voltage of the gates when a double DRpC network is employedandvariouscircuit layouts are used. (a) Turn-on and(b) turn-off transients usingcircuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2.(e) Turn-on and (f) turn-off transients using circuit layout L3.

the DUTs anddiode as explainedpreviously. TheJFETs currents

have been measured using Rogowski coils (PEMUK CWT06)

which are connected on the drain pin of each device.

The current waveforms during turn-on and turn-off of the twoSiC JFETs having the same Vbr,g , when a double DRpC net-

work is employed and the DUTs are placed according to layout

L1, are shown in Fig. 17(a) and (b), respectively. As can be seen

from Fig. 17(a), the turn-on transition takes approximately 40 ns

for both devices. Even if the two JFETs have approximately the

same values of the Vbr,g , there is a significant difference in the

recorded waveforms. The turn-off transients are presented in

Fig. 17(b), where turn-off times of approximately 30 ns are ob-

served. Transient current mismatches are obtained both during

the turn-on and turn-off transitions. In particular, a current over-

shoot with higher magnitude is obtained for the JFET No. 50

compared to JFET No. 20 during the turn-on transient, while a

similar phenomenon appears during the turn-off process. It isbelieved that the main reason for this might be the lower on-

state resistance of DUT No. 50. Another possible contribution

to the difference may be a difference in the static transfer char-

acteristics of the two JFETs (transconductance). The layout of

the circuit might also affect the switching performance of the

parallel-connected devices due to the different parasitic induc-

tances not only between the JFETs themselves, but also between

the JFETs and the SiC Schottky diode. A closer examination of

the circuit layout L1 shows that the inductive path (parasitic

inductance) from JFET No. 50 to the SiC Schottky diode is

shorter than the one from JFET No. 20. Moreover, the para-

sitic inductances between the JFETs and the connection point


9/15


of the inductor L also affect the switching performance of the

JFETs. It is, therefore, necessary to design the circuit layout in

such a way that the various parasitic inductances will be equally

distributed among the devices.

The second subset of measurements was performed by in-

terchanging the positions of the two parallel-connected SiC

JFETs, whereas the diode was kept in the same position as

in the first circuit layout, L1. The double DRpCgate driver was

also employed in this case. Fig. 17(c) and (d) shows the turn-

on and turn-off switching transients, respectively. The turn-on

time equals approximately 35 ns for both DUTs and the corre-

sponding turn-off time is approximately 30 ns. As can be seen

from Fig. 17(c), the switching speed of the two JFETs is ap-

proximately the same, while the spread in the current overshoot

during the turn-on process has been reduced compared to the

case of layout L1. However, the spread in the steady-state cur-

rent is still large due to the spread in the on-state resistances of

the DUTs. Moreover, it is the hypothesis of the authors that the

differences in the resistances of the current paths in the circuit

layout might also contribute to the differences in current.Even though the turn-off transient looks the same as in the

previous layout case [see Fig. 17(b)], the delay between the two

currents is smaller in the present case L2. Nevertheless, the cur-

rent overshoot of No. 50 is still higher than for the JFET No. 20.

There is a difference in the currents just before the turn-off pro-

cess starts. Again, this is believed to be caused by differences in

on-state resistances. A closer examination of the current traces

of the two JFETs during the turn-off transition reveals a phe-

nomenon which is specific to the parallel connection. One of the

JFETs conducts a negative current during approximately 10 ns

and the other one has an additional positive component in an-

tiphase with the negative current. The explanation to this is aseries resonance between the series connection of the two drain

source capacitances of the two JFETs and the series connection

of the two stray inductances representing the connections to the

JFETs. This phenomenon is observed in several of the figures

in the following.

The turn-on and turn-off processes of the DUTs when they are

symmetrically placed in the circuit (circuit layout L3) are shown

in Fig. 17(e) and (f), respectively. The switching speed during

the turn-on transient is approximately the same for both JFETs.

As in the previous two cases, current mismatches are observed.

In particular, a slightly higher current is flowing through device

No. 50 than No. 20 during the transient period. Moreover, the

steady-state current of JFET No. 50 is also higher than JFET No.20 due to a difference in on-state resistance. It must be noted

that in the case of symmetrical placement of the devices, the

current overshoot during the turn-on process has beeneliminated

because the inductive paths between the JFETs and the diode

are almost identical. On the contrary, the switching speeds of the

two DUTs during the turn-off process are not equal, while there

is a time delay between the two currents. Moreover, a resonance

is obtained due to the same reason as explained previously.

Fig. 18(a)(f) shows the switching transients for the devices

having the same reverse breakdown voltages of the gates using

three different circuit layouts, when a gate driver with a single

DRpCnetwork is employed. The switching transients for both

1 1.1 1.2

x 10-6

0

10

20

30

Currents[A]

Current transients for 50,20 with single DRC (layout L1)

(a)

3.7 3.75 3.8 3.85 3.9 3.95

x 10-6

0

10

20

30

Currents[A]

(b)

SiC JFET No.50

SiC JFET No.20

1.1 1.2 1.3

x 10-6

0

10

20

30

Currents[A]


(c)3.75 3.8 3.85 3.9 3.95

x 10-6

0

10

20

30

Currents[A]

(d)

SiC JFET No.20

SiC JFET No.50

1.15 1.2 1.25 1.3 1.35

x 10-6

0

10

20

30

Currents[A]


(e) Time [s]3.8 3.85 3.9 3.95 4

x 10-6

0

10

20

30

Currents[A]

(f) Time [s]

SiC JFET No.20

SiC JFET No.50

Fig. 18. Switching transients for the SiC JFETs having the same reversebreakdown voltage of the gates when a single DRpCnetwork is employed andvarious circuit layouts are used. (a) Turn-on and (b) turn-off transients usingcircuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2.(e) Turn-on and (f) turn-off transients using circuit layout L3.

DUTs using the first circuit layout L1 are depicted in Fig. 18(a)

and (b). Even though the transient current sharing during the

turn-on process is not good, the turn-off process seems to be

improved with respect to current sharing between the JFETs

comparing to the corresponding case with the double DRpCgate driver [see Fig. 17(b)].

An improved switching performance of the parallel-

connected SiC JFETs comparing to Fig. 18(a) and(b) is obtained

when they are placed according to the second circuit layout L2.

Fig. 18(c) and (d) illustrates the turn-on and turn-off processes,

respectively. In this case, the difference in the currents during

the turn-on transient has been reduced. Additionally, the turn-

off process is also improved, characterized by fewer oscillations

after turn-off.

Finally, Fig. 18(e) and (f) shows the switching transients for

the parallel-connected JFETs when they are placed in a sym-

metrical circuit layout (L3). As in the previous case with sym-metrical positioning of the DUTs, the current overshoot during

turn-on has been eliminated. On the contrary, a difference in

the steady-state currents still exists due to the difference in the

on-state resistances of the two devices. During the turn-off pro-

cess, a current overshoot of the currents and a resonance after

the turn-off process are obtained, while a delay in the turn-off

processes of the two DUTs is also observed in Fig. 18(f).

B. DUT With Different Reverse Breakdown

Voltages of the Gates

The second set of measurements deals with the investiga-

tion of parallel-connected normally ON SiC JFETs having a


10/15


3.9 4 4.1 4.2 4.3

x 10

-6

0

10

20

30

Currents[A]


(a)

6.6 6.65 6.7 6.75 6.8

x 10

-6

0

10

20

30

Currents[A]

(b)

SiC JFET No.50

SiC JFET No.21

3.5 3.6 3.7 3.8

x 10-6

0

10

20

30

Currents[A]


(c)

6.2 6.3 6.4

x 10-6

0

10

20

30

Currents[A]

(d)

SiC JFET No.21

SiC JFET No.50

3.6 3.8 4x 10

-6

0

10

20

30

Currents[A]


(e) Time [s]6.3 6.35 6.4 6.45 6.5

x 10-6

0

10

20

30

Currents[A]

(f) Time [s]

SiC JFET No.21

SiC JFET No.50

Fig. 19. Switchingtransientsfor theSiC JFETs having differentreverse break-down voltages of the gates when a double DRpC network is employed andvarious circuit layouts are used. (a) Turn-on and (b) turn-off transients usingcircuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2.(e) Turn-on and (f) turn-off transients using circuit layout L3.

difference in Vbr,g of approximately 9 V. Such a high difference

in Vbr,g (and consequently in the pinch-off voltages, see Fig. 9)

might cause mismatches in the transient currents, and therefore

unequal distribution of the switching losses. As in the previous

section, the parallel connection of SiC JFETs Nos. 50 and 21 hasbeen investigated using both configurations of the gate drivers

and by interchanging the positions of the DUTs according to the

graphical illustrations shown in Figs. 1416.

Figs. 19 and 20 illustrate the turn-on and turn-off switching

transients when a gate driver with a double and a single DRpC

network is used, respectively. Similarly to the previous section,

where DUTs having the same Vbr,g were employed, the switch-

ing performance of devices Nos. 50 and 21 was investigated

using the three different circuit layouts. The turn-on and turn-

off processes for each circuit-layout case are depicted in a single

row in Figs. 19 and 20.

Substantial current mismatches are obtained during the turn-

on transient [see Fig. 19(a)] where the DUTs are placed accord-ing to circuit layout L1 and when a double DRpC gate driver

is employed. In the opinion of the authors, the main reason for

the large current difference are differences in Vbr,g and differ-

ences in parasitic inductances. Device No. 21 has a less negative

Vbr,g than device No. 50, and therefore, the gatesource parasitic

capacitance of JFET No. 21 is charged at a lower (in absolute

value) voltage than No. 50. Thus, during the turn-on process, the

gatesource capacitance of device No. 21 is discharged faster

than of device No. 50. It is obvious that the switching losses

dominate for the device which conducts the highest current and

a destructive temperature rise might result if the switching fre-

quency is sufficiently high.

3.45 3.5 3.55 3.6 3.65

x 10-6

0

10

20

30

Currents[A]


(a)

6.2 6.25 6.3

x 10-6

0

10

20

30

Currents[A]

(b)

SiC JFET No.50

SiC JFET No.21

3.5 3.6 3.7

x 10-6

0

10

20

30

Currents[A]


(c)

6.2 6.25 6.3 6.35

x 10-6

0

10

20

30

Currents[A]

(d)

SiC JFET No.21

SiC JFET No.50

3.9 4 4.1

x 10-6

0

10

20

30

Currents[A]


(e) Time [s]

6.6 6.65 6.7 6.75

x 10-6

0

10

20

30

Currents[A]

(f) Time [s]

SiC JFET No.21

SiC JFET No.50

Fig. 20. Switchingtransientsfor theSiC JFETs having differentreverse break-down voltages of the gates when a single DRpC network is employed andvarious circuit layouts are used. (a) Turn-on and (b) turn-off transients usingcircuit layout L1. (c) Turn-on and (d) turn-off transients using circuit layout L2.(e) Turn-on and (f) turn-off transients using circuit layout L3.

Even when a symmetrical placement of the DUTs was used,

current mismatches were obtained when a double DRpC net-

work was employed as can be seen in Fig. 19(e) and (f).

However, an improved switching performance of the parallel-

connected devices Nos. 50 and 21 can be observed in Fig. 19(c)and (d) even if the circuit was not symmetrical. It is the hypothe-

sis of the authors that in this case the combination of differences

in parasitic inductance and differences in pinch-off voltage was

very fortunate.

The switching performance of the devices with different re-

verse breakdown voltages of the gates when they are driven

by a single DRpC network is shown in Fig. 20. It is obvious

that the turn-on processes in all three circuit-layout cases have

been improved compared to the case where a double DRpC

network was employed. There is still a small difference in the

currents, which might not affect the distribution of the switch-

ing losses among the parallel-connected devices. An astonishing

improvement in the turn-off processes compared to Fig. 19 isalso observed in Fig. 20. The overshoot in the current during

the turn-off process has been significantly decreased, but on the

other hand, the oscillations after the turn-off still exist.

Considering the gate-driver schematic shown in Fig. 6, the

improved performance of the parallel-connected JFETs with

different reverse breakdown voltages of the gates when a single

DRpC network is used can be analyzed. The gate driver is

supplied by a voltage which is more negative than the most

negative reverse breakdown voltage of the gates, and at the same

time,a high-value resistanceRp limitsthe gate current in order to

avoid avalanche of the gatesource junction. While the parallel-

connected devices are kept in the OFF state, the voltage drop


11/15


TABLE VSWITCHING LOSSES FOR THE DUTS WITH THE SAME REVERSE BREAKDOWN VOLTAGE OF THE GATES WHEN A DOUBLE DRpC NETWORK IS USED

TABLE VISWITCHING LOSSES FOR THE DUTS WITH THE SAME REVERSE BREAKDOWN VOLTAGE OF THE GATES WHEN A SINGLE DRpCNETWORK IS USED

TABLE VIISWITCHING LOSSES FOR THE DUTS WITH DIFFERENT REVERSE BREAKDOWN VOLTAGES OF THE GATES WHEN A DOUBLE DRpCNETWORK IS USED

across the single DRpCnetwork equals the difference between

the supply voltage and the least negative reverse breakdown

voltage of the gates.Before theturn-on process, the gate voltages

of the two parallel-connected devices are identical (as explained

previously). As a consequence, the gate voltage will also follow

each other during the turn-on process. Similarly to the turn-on

process, during the turn-off process, the gate voltages of the two

devices will be identical, which enables approximately equal

switching times and quite good transient current sharing (see

Fig. 20).

IV. SWITCHING LOSSES

Apart from the switching transients of the parallel-connected

SiC JFETs as such, it is also important to investigate the asso-

ciated switching losses. The switching losses have been deter-

mined using measured data for the current and the voltage of the

devices. Both gate-driver configurations and the two alternative

combinations of the DUTs have been considered. Furthermore,

the switching losses have been measured for all three circuit

layouts in order to investigate the effect of the positioning of

the DUTs on them. Section IV-A presents the switching losses

of the parallel-connected SiC JFETs which have the same Vbr,g

when both double and single DRpC networks are employed

(see Tables V and VI, respectively). The switching losses for

the DUTs having the same Vbr,g are shown in Section IV-B

where both double and single DRpC networks are considered

(Tables VII and VIII, respectively).

It must be noted that the energy that is stored and released

from the stray capacitances of the devices also contributes to

the measured turn-on and turn-off switching losses shown in the

third and the fourth columns of Tables VVIII. Thus, the real

switching losses equal the losses shown in these two columns

excluding the power transfer of the stray capacitances of the two

JFETs. The relation of the power transfer involving the stray

capacitances to the actual switching losses is directly related tothe switching speed. The stored energy in the stray capacitances

depends mainly on the voltage, while the switching loss energy

is proportional to the duration of the switching transient. In other

words, if the switching speed would be significantly reduced,

Tables VVIII (third and fourth columns) would show the real

values of the device switching losses at turn-on and turn-off,

respectively. It is, therefore, obvious that a correct estimation of

the real switching losses of the devices can only be done if the

sum of the switching losses at turn-on and turn-off is studied,

and not on the turn-on and turn-off contributions separately.

Thus, the actual switching losses per parallel-connected device

are shown in the fifth column of Table VVIII, while the last


12/15


TABLE VIIISWITCHING LOSSES FOR THE DUTS WITH DIFFERENT REVERSE BREAKDOWN VOLTAGES OF THE GATES WHEN A SINGLE DRpC NETWORK IS USED

column shows the total switching losses caused in the pair of

parallel-connected JFETs.

A. DUT With the Same Reverse Breakdown

Voltage of the Gate

The switching losses when two SiC JFETs having the same

Vbr,g and they are driven by a gate driver using a double DRpC

network are shown in Table V for the three various circuit lay-

outs. As it has already been mentioned previously, studying theturn-on and turn-off losses separately might not be the most

accurate way in order to draw any conclusions about the tem-

perature rise in the DUTs. Nevertheless, by looking in the fifth

column of Table V, where the total switching losses per device

are presented, a more clear indication about the loss distribution

among the devices can be seen.

Even though the total losses of both JFETs are approximately

thesame when they areplaced accordingto thecircuit layouts L1

and L2, the loss distribution among the JFETs differs for these

two layouts. When L1 is used, the losses caused in device No.

20 equals half the corresponding losses in device No. 50, which

will be hotter especially at higher switching frequencies. On theother hand, an almost uniform loss distribution is obtained in L2.

Finally, in the case of L3, the total losses caused in JFET No. 50

are approximately 60% higher than the losses in the device No.

20. However, it is worth to look in the final column of Table V,

where it can be seen that the sum of the losses for both DUTs is

lower when the circuit layout L3 is used. This is basically due

to the different switching performance of these two devices as

shown in Fig. 17.

Table VI summarizes the switching losses of the parallel-

connected SiC JFET when a singleDRpCnetwork is employed

and the DUTs have the same Vbr,g . Similar to the previous case,

an uneven distribution of the switching losses per device is also

obtained when either layout L1 or L3 is used. On the other hand,

the total losses for both devices (last column of Table VI) have

been reduced at approximately 5%. The reason for this is the

improved switching performance that has been obtained when a

single DRpCnetwork is used instead of a double one, as shown

in Fig. 18 in Section III.

B. DUT With Different Reverse Breakdown

Voltages of the Gate

Tables VII and VIII show the switching losses caused in the

parallel-connected SiC JFETs for various circuit layouts when a

doubleand a singleDRpCnetworks are employed, respectively.

Due to the transient current mismatches between the two DUTs

which are shown in Fig. 19(a) and (e), a significantly uneven

distribution of the switching losses is also expected for L1 and

L3. This can be seen in the fifth column of Table VII for the

circuit layouts L1 and L3. On the contrary, when the DUTs are

placed according to L2, a uniform loss distribution is obtained,

but the total losses for both devices are the highest among all

the layout cases.

In Fig. 20, it was shown that by employing a single DRpC

network for the devices with different Vbr,g , the switching per-

formance was improved significantly. It is, therefore, anticipated

that a more even distribution of the switching losses caused in

devices Nos. 50 and 21 should be found. This was also found

experimentally and the results are shown in Table VIII. The

most uniform loss distribution among the parallel-connected

SiC JFETs regardless of the circuit layout can be observed in

the fifth column of this table. Moreover, the total switching

losses for both DUTs, which are shown in the last column of

the table, have not only been significantly reduced, but they are

also approximately equal for all three circuit-layout cases.

From the presented results so far, it can be concluded that

for each individual case presented in Tables VVIII, the totalswitching losses caused in both parallel-connected SiC JFETs

are minimized when the DUTs are placed in a symmetrical way

(L3). It is believed that the main reason for this is the approxi-

mately equal parasitic inductances between the SiC JFETs and

the SiC Schottky diode, which leads to an improved switching

performance of the DUTs as shown in Figs. 17(e), (f), 12(e),

(f), 15(e), (f), and 16(e), (f). The numerical value of the total

switching losses when the DUTs are placed according to L3 can

be seen in the fourth line in the last column of the tables.

On the contrary, the distribution of the switching losses per

device is uniform only in the case of devices with different

Vbr,g , and when they are driven by a single DRpC gate driver.In such case, the temperature distribution among the parallel-

connected DUTs will be more uniform compared to the other

three gate-driver cases. It seems that employing a gate driver

with a single DRpCnetwork is a solution not only to the larger

spread between the Vbr,g and the pinch-off voltage, but also

to achieve a more uniform distribution of the switching losses

among the DUTs. For instance, in a module which is populated

with several SiC JFET chips and where the chips are not sorted

with respect to their Vbr,g , using a single DRpC network can

drive the JFETs in a more efficient way compared to a double

DRpCgate driver. It must be also noted that very low switching

losses and a uniform loss distribution are obtained in the case


13/15


of DUTs having different Vbr,g and driven by a single DRpC

network regardless of the placement of the JFETs in the circuit

layout.

V. DISCUSSION

Considering the present state of development of SiC JFETs,

parallel connection is the only way to reach high current ratings.

For the highest current ratings, this might be true in two or three

decades. From the previous sections, however, it is clear that

several issues must be dealt with in order to be successful.

First of all, the spread in on-state resistance might affect the

steady-state current sharing among the parallel-connected de-

vices, and hence, an uneven temperature distribution might re-

sult. In Fig. 7, it was shown that the spread in on-state resistance

among four different devices can be significant (e.g., device

Nos. 1 and 4). Regardless of the spread in on-state resistance, it

was found that the temperature coefficient of the on-state resis-

tance is approximately the same (but not identical) for all four

devices. Sorting the devices with respect to the on-state resis-tance is a simple, yet effective, way to overcome the spread in

on-state losses. Small differences in on-state resistance are not

problematic because of the positive temperature coefficient.

The variations in static transfer characteristics of the SiC

JFETs might also affect the effectiveness of the parallel con-

nection. In Section II, significant differences in static transfer

characteristics in the active region were observed. The reason

to these differences is differences in the transconductance. This

basically affects the switching transients, since the device hav-

ing the highest transconductance will take a higher current than

the other ones. Moreover, a slight difference in the pinch-off

voltages can be also obtained. Even though the first device con-ducts a low current at a gatesource voltage of5 V, the second

one is still kept in the off state.

The experimental investigation has shown that even if the two

JFETs have the same Vbr,g , their switching performance is not

exactly the same. Regardless of the type of the gate driver that is

employed, transient current mismatches are obtained due to the

parasitic inductances in the circuit layout (see Figs. 17 and 18).

On the other hand, any difference in Vbr,g (and consequently in

the pinch-off voltage) has a significant impact on the switch-

ing performance and on the distribution of the switching losses

among the devices. In particular, in a case when Vbr,g differed

approximately 9 V and a doubleDRpCnetwork was employed,

the spread in the transient current is significant even if the de-vices are symmetrically placed (see Fig. 19). Even though the

difference in the currents is large when the DUTs are turned ON,

after a certain time, the steady state is reached [i.e., Fig. 19(a)

and (b)]. If very high switching frequencies are used, it might

have destructive results for the device carrying the higher cur-

rent. In the case of the single DRpC network, the switching

performance of devices with different Vbr,g was improved re-

gardless of the circuit layout (see Fig. 20). It seems that, by

employing a gate driver with a single DRpC network, very

substantial mismatches in the transient current can be reduced,

while at the same time an approximately uniform switching

loss distribution among the devices is obtained (see Table VIII).

This might also be the solution to efficiently drive a module

populated with several normally ON SiC JFETs in the future.

In this case, the sorting of the chips with respect to their Vbr,gmight not be necessary since a satisfactory switching perfor-

mance can be obtained even if substantial device mismatches are

present.

From Tables VVIII, it is clear that the total switching losses

for the devices are the lowest when they are symmetrically

placed in the circuit layout. Nevertheless, a closer investigation

reveals that the loss distribution among the devices is uniform

only in Table VIII, which corresponds to the case of devices

having different Vbr,g and driven by a single DRpCgate driver.

Considering the other three cases (see Tables VVII) at a first

sight, it may seem that the nonuniformly distributed switching

losses may not be a considerable problem, because the sum

of the losses for the corresponding cases is not influenced. A

closer investigation, however, reveals that if the loss distribution

among the devices is excessively nonuniform, the device that

is exposed to the highest losses might get destroyed. Moreover,

with the switching speeds considered in this paper, it shouldbe mentioned that it only makes sense to look on either the

switching losses per device or the total switching losses and not

on the switching losses during the turn-on and turn-off transients

separately.

Elevated temperatures also contribute in a negative way as

shown in Section II. Even though the pinch-off voltage is al-

most independent on the temperature, Vbr,g is increasing (or

decreasing in the absolute value) when the temperature is in-

creasing for the LCJFET design, and thus, the operating gate-

voltage region is reduced. To solve this, a special gate-driver

design which supplies a narrow voltage range is again required.

This problem might become more serious when both Vbr,g andits variations with the temperature differ between the parallel-

connected devices. However, in the case of the vertical trench

JFET design,Vbr,g is almost temperature independent, and thus,

the safety margin between Vbr,g and the pinch-off voltage is also

maintained at higher temperatures.

Theidealsolutionwouldbe a sorting of theparallel-connected

devices with respect to Vbr,g and the pinch-off voltages. How-

ever, as it has been shown from the experimental results, even

this will not provide a perfect solution. When it comes to the

experiments, even if the devices have exactly the same Vbr,g ,

they might either have different on-state resistances or different

static transfer characteristics. Furthermore, the circuit layout

might also affect the switching performance of the perfectlymatched devices as it has been already shown in Section III.

Hence, the current sharing is not equal among the devices, and

consequently, the distribution of switching lossesis not uniform.

This has been experimentally shown in Sections III and IV.

VI. CONCLUSION

This paper deals with the challenges regarding parallel con-

nection of normally ON SiC JFETs. The pinch-off voltage and

the reverse breakdown voltage of the gate both count as the most

crucial parameters affecting the performance of the parallel-

connected JFETs. The margin between these two parameters


14/15


might vary among the different devices and if the parameter

spread is sufficiently large, it may, therefore, be impossible to

keep one of the components in the off-state without forcing the

other component into reverse breakdown of the gate. However,

if individual gate circuits are used, this problem can be solved.

A spread in the on-state resistances of the SiC JFETs has

been observed, but it does not appear to have any significant

adverse effects on the effectiveness of the parallel connection.

Variations, in the static transfer characteristics of the devices,

have also been observed together with the associated differences

in the switching transients.

It was found experimentally that there are substantial mis-

matches in the switching transients when the parallel-connected

devices have a significant difference in the reverse breakdown

voltage of the gates and a gate driver with a double DRpC

network is employed (see Fig. 19). This results in an uneven

distribution of the switching losses among the devices as shown

in Table VII. On the contrary, it has been shown that when a gate

driver with a single DRpCnetwork is employed, the switching

performance of the devices having different reverse breakdownvoltages of the gates has been improved and an adequately uni-

form distribution of the switching losses among the DUTs is

obtained (see Table VIII) regardless of the placement of the

JFETs.

Slightly different switching performance has also been ob-

served for the SiC JFETs having the same reverse breakdown

voltage of the gates. The spread in the switching losses distri-

bution among the parallel-connected devices may be significant

even if the DUTs are symmetrically placed in the circuit layout

(see Tables V and VI). Nevertheless, the total losses for both

DUTs are the lowest for the symmetrical placement.

Finally, it is shown that in order to achieve a similar switchingperformance of the parallel-connected SiC JFETs is not a trivial

issue, but there are four device parameters and the circuit layout

itself which are involved.

REFERENCES

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[31] J. Rabkowski, D. Peftitsis, andH.-P. Nee, Design steps towardsa 40-kVASiC inverter with an efficiency exceeding 99.5%, in Proc. 27th Annu.IEEE Appl. Power Electron. Conf. Expo., Feb. 59, 2012, pp. 15361543.

Dimosthenis Peftitsis (S03) was born in Kavala,Greece, in 1985. He received the Diploma in electri-cal and computer engineering from the DemocritusUniversity of Thrace, Xanthi, Greece, in 2008. Since2008, he has been working toward the Ph.D. degreein the Electrical Energy Conversion Laboratory, KTHRoyal Institute of Technology, Stockholm, Sweden.

In 2008, he was involved in research on hisdiploma thesis at ABB CorporateResearch, Vasteras,

Sweden, for six months. His research interests in-clude gate- and base-driver design for SiC JFETs andbipolar junction transistors, as well as protection circuits for normally ON SiCJFETs.

Roman Baburske was born in Werdau, Germany,in 1980. He received the Dipl.-Ing. degree in elec-trical engineering and the Ph.D. degree in electricalengineering and information technology from Chem-nitz University of Technology, Chemnitz, Germany,in 2006 and 2011, respectively.

From 2006 to 2011, he was with the Chair of

Power Electronics and Electromagnetic Compatibil-ity, Chemnitz University of Technology, where heworked on ruggedness analyses of high-power semi-conductor devices. The main focus of his research

was on the reverse-recovery process of bipolar power diodes. Since 2011, heis with Infineon Technologies AG, Neubiberg, Germany, where he is currentlyworking on new technologies for high-voltage diodes and IGBTs.

Jacek Rabkowski (M10) received the M.Sc. andPh.D. degrees in electrical engineering from the War-saw University of Technology, Warsaw, Poland, in2000 and 2005, respectively.

In 2005, he joined the Institute of Control andIndustrial Electronics, Warsaw University of Tech-nology, as an Assistant Professor. Since 2010, he hasbeen with Electrical Machines and Power Electron-ics Laboratory, KTH Royal Institute of Technology,Stockholm, Sweden, as a Guest Researcher. His re-search interests include novel topologies of power

converters, pulsewidth modulation techniques, drive units, and converters withSiC devices.

Josef Lutz was born in 1954. He received theDipl.-Phys. degree from the University of Stuttgart,Stuttgart, Germany, in 1983, and the Dr.-Ing. degreein electrical engineering from the Technical Univer-sity of Ilmenau, Ilmenau, Germany, in 1999.

In 1983, he was with the SEMIKRON Elek-tronikGmbH, Nuremberg, Germany, where he wasinvolved in the development of gate turn-off thyris-tors and fast-recovery diodes. He introduced the con-trolled axial lifetime diode andis theholder of severalpatents in the field of fast-recovery diodes. Since Au-

gust 2001, he has been a Professor of power electronics and electromagneticcompatibilitywith the ChemnitzUniversityof Technology, Chemnitz,Germany.

Dr. Lutz is a Member of the Board of Directors of the ZfM, a consultatorymember of the Board of Directors of the Power Conversion Intelligent Mo-tion, and a Member of the International Steering Committee of the EuropeanPower Electronics and Drives Association, the technical program committee ofthe International Conference on Integrated Power Electronics Systems, and theprogram committee of the International Seminar on Power Semiconductors. Hewas awarded the degree of Honorable Professor by the North Caucasus StateTechnical University, Stavropol, Russia, in 2005.

Georg Tolstoy (S09) was born 1981 in Gavle,Sweden. He received the M.Sc. degree in engineeringphysics from Uppsala University, Uppsala, Sweden,in 2008. Since 2008, he has been working toward thePh.D. degree in power electronics at the KTH RoyalInstitute of Technology, Stockholm, Sweden.

He was previously a Project Worker at ABBCorporate Research Center, Vasteras, Sweden, anda Software Engineer at SAAB Avitronics, Kista,Sweden.

Hans-Peter Nee (S91M96SM04) was born inVasteras, Sweden, in 1963. He received the M.Sc.,Licentiate, and Ph.D. degrees in electrical engineer-ing from the KTH Royal Institute of Technology(KTH), Stockholm, Sweden, in 1987, 1992, and1996,respectively.

In 1999, he joined as a Professor of power elec-tronics at KTH, where hecurrentlyserves as theHeadof the Electrical Energy Conversion Laboratory. Hiscurrent research interests include power electronic

converters, semiconductor components, and controlaspects of utility applications, such as flexible ac transmission systems andHVDC transmission, and variable-speed drives.

Dr. Nee has received several awards for his research. He is currently an As-sociate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS, and wason the board of the IEEE Sweden Section for several years, serving as its Chair-man during 20022003. He is a Member of European Power Electronics andDrives Association, involved with the Executive Council and the InternationalScientific Committee.

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