Silpha (Mjt Ram)

8/7/2019 Silpha (Mjt Ram)

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- 1 - Seminar Report 2004

1. INTRODUCTION

Impediments to main memory performance have traditionally been

due to the divergence in processor versus memory speed and the pin

bandwidth limitations of modern packaging technologies. End-user

demands are forcing drastic changes in the applications, which use

semiconductor memory products, and new applications are emerging with

even more unique requirements. Some of these demands include a

reduction in power, board space and cost, as well as increased density

and performance. Flash memory has been the answer to most such

demands because of the maturity of its technology, scalability, highdensity and good compatibility with the CMOS technology. But its ability

to scale with technology, because of either its tunneling oxide thickness

or cell size is limited. It is struggling to keep up with the current demands

of low voltage, high speed, high retention and high endurance operation.

As technology moves rapidly towards compact, low power, wireless and

mobile applications, a universal memory, which possesses all the good

traits of different memories like the speed of SRAM, the density of a

DRAM and most importantly, an eternal non-volatility in data storage is

sought. Non-volatility, the property by which a memory retains its data for

years even with the power is turned off, is crucial for almost all electronic

devices these days. It tells a computer how to boot up and what to do, it

tells a cell phone how to send and receive calls and store phone numbers.

Different technologies are emerging to meet these demands, some of

which are ferroelectrics memory, magnetoresistive memory, Ovonic

Unified Memory (OUM), Programmable Metallization Cell memory (PMCm)

etc. Different as these technologies are, they share three main

advantages over flash. First, they can write data in a few tens of

nanoseconds, like the DRAMs in a computers main memory. Flash, on the

other hand, takes at least a microsecond. Second, the new memories can

withstand re-writing for years whereas flash begins to lose data after

Dept Of Electronics&Commn Engg GEC,Thrissur


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fewer than a million write cycles and thirdly, the newer memories

consume far less power than flash during its operation.

Magneto resistive Random Access Memory (MRAM), is an emerging

memory technology that exploits a property of some atoms,

ferromagnetism. Atoms in a ferromagnetic material act like tiny magnets

and respond to an external magnetic field by trying to align themselves in

its direction. As in ferroelectric materials, they arrange themselves into

domains in which all the atomic magnets point in the same direction,

creating a larger magnet. Apply an external magnetic field and all of the

domains line up to point in its direction; remove the field and they remain

locked in that direction. If a field is next applied in the opposite direction,

the domains flip over. This propertythat the magnetic domains of

ferromagnetic materials change direction only when they are influenced

by a magnetic fieldmakes them ideal memory devices. Thus an MRAM

stores information using the magnetic polarity of a thin ferromagnetic

layer. This information is read by measuring the current across an MRAM

cell, determined by the rate of electron quantum tunneling, which is in

turn affected by the magnetic polarity of the cell.

A BRIEF HISTORY

Historically, volatile memories such as DRAM (Dynamic Random

Access Memory) and SRAM (Static Random Access Memory) were the

most important types of memory in terms of market size, despite the

disadvantage of their non-volatility. This was due to their rapid writing

capability, which is mandatory for their use as "working" memory. In the

case of DRAM, the small size of the memory cell allows very high storagecapacities to be achieved: in 2003, 1-Gbit DRAMs are commercially

available, each chip with a capacity of over one billion data bits of

storage. The absence of refresh circuitry and its high reading speed are

advantages for the SRAM. Both DRAM and SRAM are essential

components of PCs.



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Flash memory belongs to the class of semiconductor memories

called non-volatile memories, of which it is the most dynamic driving

force. These memories are based on the EEPROM technology. The Flash

memory is similar to the EPROM cell in structure except with a high

quality thinner gate oxide layer. Flash memories are useful in applications

which require more memory capacity than the EEPROM can provide and

also for applications which do not need fast and frequent programming

like memory cards for digital cameras and MP3 players. The pressures on

Flash manufacturers are twofold: to increase performance (in terms of

speed, density and power consumption) and to decrease costs.

Since 1971, anisotropic magnetoresistive (AMR) Ni-Fe alloy thin

films have been explored for use in magnetic field sensing. These types of

ferromagnetic thin films change resistance depending on the relative

direction between film magnetization and in-plane current direction. Its

field sensitivity is much larger than that obtained through coil winding.

Unlike inductive magnetic field sensors, the AMR sensor is speed

independent. Devices using this type of material include read heads in

high-density hard disk drives, magnetic field sensors for a variety of

applications, and magnetoresistive random access memory (MRAM).

In 1988, a new type of magnetoresistive material, termed giant magneto

rsistance (GMR) material, was discovered. The material is made of at

least two magnetic layers separated by a conducting interlayer. Its

resistance depends on the relative orientation between the neighboring

magnetic layers. It is a maximum when the directions are antiparallel and

a minimum when they are parallel. Due to its improved signal compared

to AMR material, GMR films result in enhanced device performance in

most applications. GMR films have already been incorporated intocommercial read heads, and development for other device applications,

such as sensors and MRAM, is underway. The GMR films are most often

used with current flowing in the film plane. The discovery of the GMR

effect was a boost to MRAM technology. Not only is the signal strength

larger, but the characteristics of the physical phenomenon itself are well



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suited for MRAM, which uses magnetic-moment direction as information

storage and the resultant MR difference for sensing.

The development of MRAM began approximately ten years ago in

response to the need for a durable, radiation-hard, nonvolatile RAM. In

the early 1990s, high magneto resistance (MR) ratio, (expressed as the

change in resistance divided by the minimum resistance) was discovered

for magnetic tunnel junction (MTJ) material. Tunneling MR values reported

are in the 20-50% range, much higher than typical GMR films. MTJ

material is quickly finding applications in MRAM and magnetic field

sensing.

MRAM CELL

Figure 1 shows the different components of an MRAM cell. The cell is

composed of a diode and an MTJ stack, which actually stores the data.

The diode acts as a current rectifier and is required for reliable readout

operation.

Figure 1. MRAM CELL



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The MTJ has three functional layers as shown in figure 2. From top to

bottom, there is a free ferromagnetic (FM) layer, a tunnel barrier, and a

pinned ferromagnetic (FM) layer. In the top FM layer, the orientation of

the free magnet (within the free FM layer) in the absence of applied fields

will be along either the positive or negative X axis, depending on the

state of the stored datum. In the bottom FM layer, material anisotropy

freezes the pinned magnet, to point in a fixed direction, by providing an

extremely high magnetic barrier relative to the range of fields required to

switch the free magnet. The alignment between the free magnet and the

pinned magnet governs the conductance of the MTJ. The free FM layer

provides a means for storing a bit of information, corresponding to a "1"

or "0" state of a binary memory element.

Figure 2. The MTJ stack

To operate MTJ as a memory cell depicted as in figure 2 requires

that the MTJ provide a physical means for state storage, one for state



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detection, and another to change its state. The MTJ memory cell stores

state in one of two possible relative orientations of its free magnet to its

pinned magnet, either a parallel orientation or an antiparallel orientation.

Since the relative orientation regulates the read current through the MTJ,

a "read" circuit can detect the state of the memory cell by assessing the

MTJ resistance. The MTJ behaves as a variable resistor with two discrete

resistance values, Rparalleland Rantiparallel, where Rantiparallel is larger than the

Rparallel.These resistance values depend on the before mentioned relative

orientation of the free magnet to the pinned magnet. In other words, the

relative orientation regulates the "read current" flow through the MTJ.

When the polarization is anti-parallel, the electrons experience an

increased resistance to tunneling through the MTJ stack. Thus, the

information stored in a selected memory cell can be read by comparing

its resistance with the resistance of a reference memory cell located

along the same word line. The resistance of the reference memory cell

always remains at the minimum level.

An applied field can switch the free layer between the two states, ie.

to change the state of the memory cell, magnetic fields generated by

pulsed currents flowing above and below the MTJ orient the free magnet

to one of the two states. In an MRAM array, orthogonal lines pass under

and over the bit, carrying current that produces the switching field. The

bit is designed so that it will not switch when current is applied to just one

line, but will always switch when current is flowing through both lines that

cross at the selected bit.

The diode in this architecture must have a large on-to-off

conductance ratio to provide isolation of the sense path from the sneak

paths. This isolation is achievable using thin film diodes. Schottky barrierdiodes have also been shown to be promising candidates for current

rectification in MRAM cells.

2. HOW MTJ MRAM WORKS?



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In two-dimensional (2-D) arrays of MTJs, a single bit of information

may be selectively written by applying orthogonal magnetic fields

directed within the XY-plane of the MTJ. The combination of an easy axis

field, directed along the length of the MTJ (i.e., the X-axis), and a hard

axis field, directed along the width of the MTJ (i.e., the Y-axis), writes the

MTJ to a new state. A switching astroid curve delineates the boundary

between switching the orientation of the free magnet and not switching it.

Figure 3 (a) shows an ideal switching astroid, which assumes single

domain switching. A model for the ideal switching astroid can be derived

that satisfies the relation Heasy^ 2/3 + Hhard^ 2/3 = Hk^ 2/3, where Heasy

is the easy axis field, Hhard is the hard axis field, and Hk is the anisotropy

field.

Figure. 3(a) ideal switching astroid3(b) actual switching astroid

The switching astroid differs from the ideal. In general, actual

switching astroids of MTJs within a memory array are not identical.

Fluctuations among them may arise from differences in each MTJs shape,

edge roughness, surface smoothness, material composition, thickness of

the free FM layer, pinning mechanism of the pinned FM layer, and aspect

ratio. It should be emphasized, however, that all MTJs must have a certain



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consistency, as expressed by the uniformity of their switching astroids, to

serve as viable memory elements for an MRAM chip.

Hhard and Heasy write the MTJ. Inside the switching astroids of Figure

3(a) and (b), fields are small enough that they cannot change the

orientation of the free magnet. Outside the switching astroids, fields are

large enough that they can reverse the orientation of the free magnet,

and hence through this means, the free magnet can be set in either a

parallel or antiparallel state, having a characteristically low resistance

Rparallel or high resistance Rantiparallel.

Referring to Figure 3(a), it has been explained that the MTJ may be

written by the combination of two orthogonal fields, which individually are

too small to write the MTJ: Heasy directed along the easy axis (X-axis) and

represented by field point 1a and Hhard directed along the hard axis

(Y-axis) and represented by field point 2a. An Heasy of the size of field point

1a cannot write the MTJ alone. Only a combination of Heasy and Hhard,

represented by field point 3a, exceeds the switching astroid boundary

and writes the MTJ to a state, its free magnet aligning with Heasy. Had Heasy

been negative rather than positive, resulting in the field combination

represented by field point 4a, the orientation of the free magnet would

have been reversed.

It is important to understand Hhard does not define the orientation of

the free magnet of an MTJ; instead, it only helps to destabilize the free

magnet so that a lower Heasy can be applied to switch the free magnet.

This property is exploited in two-dimensional (2-D) memory arrays where

the coincident application of Heasy and Hhard writes only the MTJ of a

selected memory cell. Other memory cells that incidentally receive one or

the other field alone are not written.The shape anisotropy (aspect ratio of the thin-film magnet) acts to

confine the free magnet such that, in the absence of a field, it will point in

one of two directions; the free magnet orients itself along the longer of

the two dimensions of the thin-film magnet which, in this example, is

along the X-axis. In other words, after a switching operation, once all



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external fields have been removed and the magnet has had a chance to

reach a quiescent state, the free magnet always settles in such a way

that its north and south poles align along the X-axis.

A bit of information is retrieved from the MTJ of Figure 2 by

measuring its resistance via a read current directed along the Z-axis,

transverse to the XY-plane. The logic state is extracted from the read

current by determining whether the magnitude of the read current is

larger than or less than a reference current. The reference current is

halfway between a current extracted from a MTJ in a parallel state (having

Rparallel) and a current extracted from a MTJ in an antiparallel state

(having Rantiparallel).

The read current can be divided into a carrier component,

henceforth referred to as a base read current, and a signal component,

henceforth referred to as a signal current. The base current is

proportional to the average of the inverse of Rparallel and the inverse of

Rantiparallel. The signal current is proportional to the difference between the

inverse of Rparallel and the inverse of Rantiparallel. The MTJ stack includes a

tunnel barrier that determines the magnitude of the base read current.

The tunneling barrier thickness and composition control the resistance of

the MTJ, as measured by the read current flowing from the free FM layer

across the tunnel barrier, and to the pinned FM layer. The base read

current has an inverse exponential dependence on the barrier thickness.

The base resistance of an MTJ should be identical across a 2-D array of

such elements, with the measured resistance reflecting only a binary

difference in state among the MTJs . An MTJ's magnetoresistance provides

the signal current. The quantity of magnetoresistance is defined as the

difference between Rantiparallel and Rparallel divided by Rparallel, and it has beenreported to be greater than 40%.

The quantum mechanical mechanism responsible for the

magnetoresistance of the MTJ is electron spin. The electron transport

across a tunnel barrier of the MTJ is governed by the orientation of the

magnetic moment in the free layer with respect to that in the pinned



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- 10 - Seminar Report

2004layer. "Parallel" orientation indicates, on a microscopic level, that the

spins of the conduction band electrons in each of the ferromagnetic

layers are the same, whereas "antiparallel" orientation indicates that such

electron spins are opposite. For free and pinned FM layers having the

same electron spins in their conduction bands, a high density of filled

electron states furnishes a significant number of electrons for tunneling to

a high density of empty electron states, resulting in a low tunnel barrier

resistance. In contrast, for free and pinned FM layers having opposite

electron spins in their conduction bands, a lower density of filled electron

states furnishes fewer electrons for tunneling to a high density of empty

electron states, resulting in a high tunnel barrier resistance. Hence, an

MTJ having a "parallel" orientation between moments has a lowerresistance than one having an "antiparallel" orientation.

1T1MTJ MRAM

One flavor of MRAM is the one-transistor-one-MTJ (1T1MTJ) memory

cell, offering very high performance. Figure 4 depicts a 1T1MTJ MRAM

circuit comprising an array of 1T1MTJ memory cells, row drivers, bit line

(BL) connect circuits, a sense amplifier, and write circuits. Each 1T1MTJ

memory cell consists of one n-type transistor, which is used to isolate

selectively the read current of one memory cell from that of another

(sharing the same bit line), and one MTJ, which provides nonvolatile

coverage.



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2004

Figure 4. 1T1MTJ MRAM circuit

It should be emphasized that the bit line connects directly to each

MTJ along a column of memory cells, while the write word line (WL)

passes under the MTJs along a row of memory cells. The write word line is

electrically isolated from the memory cells.

Write Operation of 1T1MTJ MRAM

A selected MTJ within the array of 1T1MTJ memory cells is written by

the coincident application of orthogonal magnetic fields, a hard axis field

that emanates from a selected write word line (WL) and an easy axis fieldthat emanates from a selected bit line. Write currents Iword and Ibit

generate circumferential magnetic fields Hhardand Heasyin the range of 20

to 80 Orstead. The magnitude of the write current required to switch the

MTJ depends upon the switching astroid (threshold) of the free magnet.



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2004From elementary physics, it is known that the magnitude of the

magnetic field applied to an MTJ is directly proportional to the current

flowing through the source conductor, the bit line, or word line, but it is

inversely proportional to the radial distance from a source conductor to

the MTJ itself. Therefore, the distance from the center of the write word

line to the MTJ, deltaZ, should be minimized to maximize the magnetic

coupling.

Traversing a selected write word line and a selected bit line within

the 1T1MTJ MRAM Circuit of Figure 4, Iwordand Ibit induce magnetic fields

Hhard and Heasy, respectively, that together write a memory cell. A word

address directs a row driver to steer Iwordfrom a word write circuit through

a selected row driver, through the selected write word line, and finally- tothe ground return line. Likewise, a bit address directs bit line connect

circuits to steer Ibit from a write circuit designated to operate as a source,

through a bit-line connect circuit, through the selected bit line, through

another bit-line connect circuit, to another write circuit designated to

operate as a sink. A datum input signal determines which write circuit

operates as a current source and which operates as a current sink. The

sign of Ibit determines the state of the datum to be stored in a selected

memory cell. Inverting the data input reverses the direction of Ibit and Heasy

thereby writing a complement state (instead of a true state) in the

selected memory cell. A coincidence Of Hhard and Heasy fields drives the

free magnet of the MTJ of the selected memory cell to either a parallel or

an anti parallel orientation with respect to its pinned magnet. In Figure 3,

the composite field applied to the MTJ corresponds to field point 3a. In the

process of writing the selected cell with Hhard and Heasy fields, other

memory cells are subjected to one or the other of the two fields.

An unfortunate by-product of the coincident application of fields on

the selected memory cell is the partial stimulation of the remaining

memory cells, which are not intended to be written, by Hhard and Heasy .

These half-selected cells occupy the row of cells along the selected word

line or the column of memory cells connected to the selected bit line.



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2004Referring to Hhard and Heasy, field points 2a and 1a of the switching astroids

of Figure 3, since the half-select fields applied to the half-selected cells

reside within the switching astroid curve, they should not disturb the

state of the half-selected cells. However, additional stray magnetic fields

could combine with the half-select fields in such away that the cumulative

fields could exceed the astroid curves causing the half-selected cells to

switch inadvertently. It is therefore necessary for the designer to consider

all significant factors that impact the absolute margins between selected

and half-selected cells including stray field coupling, misalignment of the

write WLs and Us with respect to the MTJs, non-idealities of the write

circuit, and the non-idealities of MTJ itself.

For example, the impact of stray field coupling can be quantified interms of Hhard and Heasy fields applied to the half selected cells and the

selected cell. Hhard and Heasy fields extend beyond the dimensions of the

selected MRAM cell, spilling over into neighboring, unselected cells.

According to the equation that expresses the field strength emanating

from an ideal conductor, the strength of Hhard or Heasy decays as the

inverse of the radial distance outward from the center of the

corresponding source conductor, either the write word line or write bit

line, to the free FM layer of the MTJ. In addition , only the in-plane field

component of the total magnetic field switches the MTJ. It can be deduced

from these relationships that a fraction of the in-plane Hhard field, applied

to the selected row of memory cells, couples to memory cells in

neighboring rows according to

Hcouple~ Hhard / [(I + deltaY / deltaZ)] 2 (1)

In this equation, Hcoupleis the fraction of the Hhard field that is coupled to

the nearest neighbor cell, deltaY is the horizontal spacing between MTJs

along the Y axis, and deltaZ is the vertical distance between the free FM

layer of the MTJs and the center of the write word line conductor. The

equation for Hcouple would be more complex if misalignment between the

MTJ and the write word line was considered, or if the finite width and

height of the write word line were included, but, nonetheless, it can be



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2004revised to include such non-idealities. For some memory cell geometries,

the Hcouplecan be even higher than 10% of the Hhard Thus, it is should be

emphasized, once again, that only precise control of the magnetic circuit

and the MTJ will yield a memory array with enough write-margin to write

the selected memory cell only and not disturb the state of neighboring

memory cells or other half-selected memory cells.

Read Operation of 1T1MTJ MRAM

During a read operation, a selected read word line enables n-type

transistors along a row of memory cells in the 1T1MTJ MRAM circuit of

Figure 4. Consequently, only the MTJ of each selected memory cell isconnected from a bit line to ground. A read current (not shown)

originating in a sense amplifier traverses a path including a bit line

connect circuit (to read port) and the selected 1T1MTJ cell and ending at

ground. The n-type transistor directs the read current supplied by the

sense amplifier to flow exclusively through the selected MTJ, thereby

shielding it from the influence of other MTJs attached to the same bit line.

The sense amplifier detects the logic state stored within a selected

memory cell. Its positive terminal (or negative terminal) connects through

a bit line connect circuit to the selected memory cell, via the bit line, and

its negative terminal (or positive terminal) connects through another bit

line connect circuit to a reference cell, via a reference line. Referred to as

a voltage-clamped-current sense amplifier, this sense amplifier ideally

forces its positive and negative terminals to the same voltage by

supplying two different currents, one having a variable value and the

other having a fixed value. A read current and a reference current flow

from the sense amplifier to the memory cell and the reference cell,

respectively. These currents are compared within the sense amplifier to

determine the logic state of the memory cell, having been modulated by

the resistances of the memory cell and of the reference cell. If the read

current is greater than the reference current, then the sense amplifier



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2004would detect a "1" state stored within the memory cell, for example (the

"1" and "0" logic state assignment is arbitrary for the sense amplifier as

long as it is consistently defined with respect to the write circuit);

whereas, if the read current is less than the reference current of the

reference cell, then the same sense amplifier would detect a "0" state

within the memory cell.

Although it is possible to design a reference cell that provides a

current halfway between the read current of a memory cell storing a "I"

state and the read current of one storing a "0" state.In large-scale

manufacturing, the reference cell is likely to produce inconsistent current

levels, due to variations in its shape or size with respect to a memory

cell's shape or size. It is therefore advisable to develop accurate andconsistent reference currents through a network of preprogrammed

memory cells. The current averaging reference circuit of Figure 5

accomplishes such a function.



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2004Figure 5. Current averaging reference circuit

For simplicity, sense amplifiers 1 and 2 are shown connected to

selected BLs 1 and 2 and reference lines I and 2, the exact connections to

the selected BLs and reference lines having been formed within the bit

line connect circuits (to read port) of Figure 4 in response to an applied

bit address. Similarly, in response to an applied word address (shown in

Figure 4), an enabled read word line closes all switches of Figure 5 (the

n-type transistors of Figure 4) along the selected row, thereby connecting

the variable resistors of Figure 5 (representing the MTJs of Figure 4) to

ground. Selected 1T1MTJ memory cells have closed switches. Unselected

1T1MTJ memory cells have open ones. The reference cells in the circuit

are formed out of preprogrammed memory cells in a "1" state or a "0"state having resistances Rparallel or Rantiparallel, respectively.

A voltage bias, is applied across both the selected memory cells

and the reference cells. A reference current for each sense amplifier is

established by averaging the "1" and "0" currents of reference cells. The

connection between reference line 1 and reference line 2 combines "1"

and "0" currents from two reference cells to form the 2X reference

current that then divides into two equal reference currents, one for sense

amplifier 1 and the other for sense amplifier 2. This reference scheme

insures the reference current tracks halfway between the "0" and "1"

current of the memory cells since the same voltage Vbias is applied

across both the MTJs of the selected memory cells and the MTJs of the

reference cells. Having a common voltage Vbias applied across all MTJs is

important because the magnetoresistance of an MTJ has a nonlinear

dependence on voltage.

3. CROSS - POINT CELL (XPC) MRAM

Figure 6 depicts an XPC MRAM circuit proposed as a dense

alternative to the 1T1MTJ MRAMcircuit of Figure 4.



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2004

Figure 6. XPC MRAM circuit

In this alternative, MTJs are used exclusively to form the memory

cells and are sandwiched between, and electrically connected to,

orthogonal WLs and BLs as depicted in Figure 7. Advantageously, the XPC

memory cell requires one MTJ only, as opposed to a MTJ plus a switching

device in the IT1MTJ memory cell. Moreover, a single WL in XPC MRAM

serves both write and read functions for a row of memory cells. In

contrast, the 1T1MTJ MRAM circuit of Figure 4 requires two WLs for each

row of memory cells, a dedicated read WL and a dedicated write WL.

Unfortunately, though, for XPC MRAM, duplicate WL, circuits are required

to control the hybrid read-write functionality required by the single WL

approach.



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2004Figure 7. Array of MTJs for XPC MRAM

With a simpler cell and one WL, the XPC memory cell offers a

minimum cell area of 4F2. Both WLs, laid out in metal-2 (M2), and BLs, laid

out in metal - 3 (M3), have a metal width and spacing off, resulting in an

MTJ area to 1F2. F refers to the minimum feature size, where currently F is

less than 0.18m for leading-edge technologies. Actually, the memory

cells size and the MTJ area are larger than 4F2and 1F2,respectively, since

the MTJ needs to be elongated along the X-axis in order to fix the easy

axis orientation of the free magnet along the X-axis. Without shape,

anisotropy, the magnetic moment in the free FM layer would orient itself

in an arbitrary direction, destroying the intended binary storage

capability.Only back-end metal levels (e.g., M2 and M3) are needed for

accessing the MTJ, thereby leaving the silicon area underneath the

storage layer unoccupied. This active area can be used for peripheral

circuits, such as decoders or logic blocks, in order to reduce overall chip

size. By modifying only the back-end layers, an XPC MRAM can be added

above existing circuits, making the XPC MRAM a promising candidate for

embedded and high-density applications. Moreover, 3-D stacking of MTJs

is -possible, leading to cell areas close to 4F2/n where n refers to the

number of stacked storage layers. A 3-D XPC array uses two stacked

MTJs, which leads to a cell size close to 4/2F2. While Flash memories store

multiple bits in the device threshold of one transistor, XPC MRAM stacks

multiple bits one on top of the other.

In Figure 6, a schematic block diagram of the XPC MRAM is shown.

The write operation of the XPC MRAM employs the same coincident field

selection mechanism (Heasy and Hhard) as that used in 1T1MTJ MRAM.

However, to generate the same Hhard 011 the free magnet of the MTJ, the

XPC MRAM requires less write current 1word, than the 1T1MTJ MRAM, due

to improved magnetic coupling gained from the reduction of the vertical

distance (along the Z-axis) of the XPC memory cell (as depicted in Figure

7) in reference to the vertical distance, deltaZ, of the 1T1MTJ memory



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2004cell, the vertical distance being measured from the center of the WL to

the free ferromagnetic layer. In addition to the WL height and the MTJ

height of the XPC memory cell, the 1T1MTJ memory cell of Figure 5 has

the intervening heights of insulating layer and MX layer totally.

XPC writing is illustrated in Figure 8. Currents are forced through

WLi and BLk to write the selected cell S at the cross section of WLi and BLk

Since a cross-point cell array is a resistive network, the voltage drop

along the selected lines WLi and BLk caused by the wire resistance and the

MTJ resistance induces parasitic currents

that flow into unselected WLs and BLs tied to the equipotential voltage,

Veq, supply.

Figure 8. XPC writing

The variation of the programming current along the WL or BL

depends on the resistance of the MTJs, the number of MTJs connected to

the WL or BL, and the resistance of the WL or BL. In order to reduce the

variation of the programming current along WLi/BLk caused by the

parasitic currents, the resistance of the MTJ cells has to be significantly



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2004higher than in a 1T1MTJ design. An increased MTJ resistance, however,

leads to decreased read signal levels, and the XPC MRAM, therefore,

requires more sophisticated sensing circuitry than the 1T1MTJ MRAM

required.

The read operation of the XPC MRAM differs from the read operation

of the 1T1MTJ MRAM in that the unselected WLs and unselected BLs are

held at the equipotential voltage Veq by a keeper device within the

peripheral circuits while the selected word line is grounded. This behavior

is explained with reference to Figure 9.



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2004

Figure 9.XPC Reading

Ideally, the sense amplifier forces Veq across the selected memory

cell (or cells) and zero voltage drop across the unselected memory cells;

the read current would then depend only on the state of the selected

memory cell (or cells), labeled Rc. Unfortunately, mismatches in the

threshold of the transistors clamping the BLs, WLs, and sense amplifier to

Veq cause small voltage drops (Vos) to develop across unselected memory

cells, reducing the signal-to-noise ratio of the XPC MRAM. The auto-zero



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2004sense amplifier of Figure 9, however, can correct such mismatches with

its Vos compensation scheme (An auto-zero sense amplifier removes offset

in an amplifier by first measuring offset voltage at the input of the

amplifier, next storing the measured offset on a capacitor, and finally

summing the measured offset with the input to cancel the offset in the

amplifier).

ADVANTAGES OF MRAM

MRAM cells are non-volatile, and they can be both faster, and

potentially as dense, as DRAM cells. They can be implemented in wiring

layers above an active silicon substrate as part of a single chip. MultipleMRAM layers can thus be placed on top of a single die, permitting highly

integrated capacities, MRAM has the potential to be fabricated on top of a

conventional microprocessor, thus providing very high bandwidth. The

access time and cell size of MRAM memory has been shown to be

comparable to DRAM memory.

As the data stored in an MRAM cell are non-volatile, MRAMs do not

consume any static power. Also, MRAM cells do not have to be refreshedperiodically like DRAM cells. Thus, MRAM memory has attributes which

make it competitive with semiconductor memory.

The memory technology comparison table 1 compares the

attributes of MTJ MRAM (both IT1MTJ and XPC MRAM) to the attributes of

other RAMs, specifically SRAM, DRAM, NAND Flash, and NOR Flash. In the

nonvolatile category, MTJ MRAM offers practically infinite high write

endurance, expected to exceed 1015 cycles, and high-speed write

access, between 10 to 40 ns. Moreover, IT1MTJ MRAM offers a smaller cell

size than SRAM. This would be particularly attractive for the wireless

device arena where data endurance and nonvolatility have become the

"mantra." In comparison to 171MTJ MRAM, XPC MRAM offers higher

density at the expense of READ random access time.



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4. DRAWBACKS

Unsurprisingly, MRAM devices have several potential drawbacks.

They require high power to write, and layers of MRAM devices may

interfere with heat dissipation. Furthermore, while MRAM devices have

been prototyped, the latency and density of production MRAM cells in

contemporary conventional technologies remains unknown. To justify the

investment needed to make MRAMs commercially competitive will require

evidence of significant advantages over conventional technologies.

CHALLENGES

One of the challenges involved in the integration of MRAM

technology is temperature compatibility with the CMOS process. Several

standard CMOS process steps occur at or above 400C. As shown in figure

11, the MR of typical MTJ material begins to degrade at temperaturesabove 300C and drops sharply by 400C.



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Figure 10.

Thus, for a working memory either the MTJ material must be

improved to withstand these standard process temperatures, or low-

temperature processes must be developed for MRAM technology. For our

demonstration circuits, special low-temperature processes were used toprevent the MTJ material from being exposed to higher temperatures

during MRAM processing. Improvements in the thermal endurance that

would make the materials compatible with standard processes would

enhance the manufacturability of the technology.

Obtaining very uniform RA over large wafers is another challenge.

Techniques that have been explored include forming the aluminum-oxide

tunnel barrier with air; reactive sputtering; plasma oxidation with plasmasource; plasma oxidation with power introduced from the target side; and

plasma oxidation with power introduced from the substrate side. The

results show that all techniques can be made to work. Plasma oxidation is

favored due to its simplicity and manufacturing compatibility. It was also

discovered that different oxidation methods used in this study caused



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2004little difference in MTJ resistance uniformity. The latter is mainly

determined by the aluminum metal thickness uniformity. Modeling based

on Simmons' theory supports the experimental finding. This illustrates

that the key to better MTJ RA uniformity is to improve the aluminium

metal layer thickness uniformity.

A final challenge is producing MTJ material with very low RA.

As bit sizes are reduced, MRAM may require material with lower RA. In

addition, use in hard-disk read heads would require a much lower

resistance for the first generation of product. Obtaining a thinner tunnel

barrier without losing MR is one of the key factors to achieving low RA.

CONCLUSION

There is no doubt that there is a need for a new memory technology

for a successful market penetration and a better end user product. Lower

costs, lower power consumption, non-volatile techniques, and the new

technology should be easy to integrate into existing CMOS technology.

Comparing these requirements for future memories with current memory

devices, we see that each of them has certain limitations: DRAMs are

difficult to integrate, SRAMs are expensive and FLASH devices are too

slow and have a limited number of write/erase cycles. EEPROMs show

high power requirements and a poor flexibility. None of them combines

features like: The ability to retain stored charge for long periods with zero

applied or refreshed power, high speed of data writes, low power

consumption, large number of write cycles. Which in turn are met by MTJ

MRAM.



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2004In the race to commercialize MTJ MRAM, process engineers and

physicists are battling to increase MTJ bit yield, to improve the intrinsic

write-margin of the MTJ, and to incorporate magnetic materials (nickel

and iron) into the back-end process. Circuit designers are developing

clever approaches to increase memory density, to minimize power

consumption, and to reduce read access times. Considering the current

pace of development, MTJ MRAM technology could become a mainstream

memory technology of tomorrow.

REFERENCES

IEEE Circuits and Devices

domino.research.ibm.com

www.public.asu.edu

www.cordis.lu/esprit/src/28229.htm

www.tcd.ie/Physics/Magnetism/

Conferences/tfdom3/parkin.pdf



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Documents

Silpha (Mjt Ram)