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Introduction
Embedded systems are task specific systems often with real time computing constraints used to control devices. Made for versatile capabilities, are found within a larger system thus the name embedded, like in phones, automobiles, washing machines etc.
Integrated Circuits (IC) or chips are semiconductor wafer circuit packaging for deployed and implementation in electronics designs. A single chip could thousands or millions of transistors, resistors, capacitors or other electronics components and circuit designs. ICs could have digital or analogue functionalities on. Typical examples are amplifiers, logic gates (AND, OR, XOR etc), oscillators, timers, computers (microcontrollers and microprocessors) (CIO, 2012).
8051 microcontrollers are Harvard architecture based micro computer chips developed by Intel for embedded systems design (John, 1980). Has 8-bit CPU, I/O peripherals(32 bidirectional), program(64K) and data(64K) memories address spaces, [RAM(128 bytes), ROM (4 k-bytes)], counter/timers(two(2) 16 bit)], 6-source/5vector interrupt structure with two(2) priority levels and full duplex UART on a single chip (Intel, 1994). A design exercise with 8051 programming and hardware implementation is demonstrated in this assignment.
VHDL is VHSIC (Very High Speed Integrated Circuit) Hardware Description Language would be used to design digital circuits in Altera Quartus II software.
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Procedure and Results
Question 1
A program which writes the last two (2) digits of a student’s Stamford ID into the 8051 microcontroller’s internal RAM addresses from 40h to 6Fh with the same data. Assuming the last two (2) digits of ID as a decimal number and crystal oscillator is 11.0592MHz.
Stamford students ID = 1119930Last two(2) digits of my ID = 30 Program code:
#include<reg51.h> //special function declaration to include/add 8051 header file
unsigned int A; // initializing the variable A
unsigned char *ptr; // store a location in pointer, declare pointer
void main(void) // main has no return value
{
while(1) //Loop/Run continuously, until blocked
{
ptr = 0x40; // pointer address, RAM address 40h
A = 30; // Loads 30 into A
for (ptr = 0x40; ptr <= 0x6f; ptr++) // Loop to write 30 in the addresses 40h to 6Fh
*ptr = A; // loads data into pointer
}
}
The result
The memory window showing that address 40h has 30 written in it.
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The memory window showing that 30 has been written from address 40h to 6F
Flow chart: to illustrate writing the last two (2) digits of a student’s Stamford ID into the 8051
microcontroller’s internal RAM addresses from 40h to 6Fh with the same data. Last two (2)
digits = 30, student’s ID = 1119930
Flowchart of Loading ID =30 in 8051 RAM Addresses 40h to 6Fh.
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Question 2
A program that counts down from the last four (4) digits of a student’s Stamford ID until zero. Once completed, the function will reset and countdown again. Assume the last two (2) digits of Stamford students ID is a decimal number and crystal oscillator is 11.0592MHz.
Stamford students ID = 1119930Last four (4) digits of my ID = 30
Program code:
#include<reg51.h> // special function declaration to include/add 8051 header file
unsigned int A = 9930; // Initializing the variable A =9930void main(void) // main has no return value { while (1) // while=1, Loop/Run continuously, until blocked {
for (A = 0; A <= 9930; A--) // loop function to countdown from 9930 if (A == 0){ //check if countdown is complete A = 9930; //reset the variable to aid countdown, A=9930
}}
}
The result:
The watch window showing the last four (4) digits of ID (9930) in variable counting continuously
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Flow chart: to illustrate counting down from last four (4) digits of student’s Stamford ID in 8051 microcontroller. Last four (4) digits = 9930, student’s ID = 1119930
Program Flowchart for A = 9930 counting continuously.
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Question 3
VHDL Code for the function:
F(x1, x2, x3) = Ʃ m (0, 2, 4, 5, 6)
The truth Table
No. X3 X2 X1 F (output)
0 0 0 0 1
1 0 0 1 0
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0
Figure 3: Truth table of the function
Minimizing the function using Karnaugh Map:
X2X3
X100 01 11 10
1 1 1 0 1
0 1 1 0 1
Figure 4: Karnaugh Mapping for the function
F = X1X 2+ X 3
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Using Boolean algebra:
F = X 1 X 2 X 3 + X 1 X2 X 1 + X1 X 2 X 3 + X1 X 2 X3 + X1 X2 X 3
X 1 X 3 (X 2+ X2) + X1 X 2 ( X 3 +X3) + X1 X 3 (X 2+ X2)
X 1 X 3 (X 2+ X2) + X1 X 2 ( X 3 +X3) + X1 X 3 (X 2+ X2)
X 1 X 3 + X1 X 2 + X1 X 3
X 3 (X1+X 1)+ X1 X 2
X1 X 2 + X 3
Simulation Using Quartus II
AND2
inst
NOT
inst1
NOT
inst2
OR2
inst3
VCCX1 INPUT
VCCX2 INPUT
VCCX3 INPUT
FOUTPUT
Circuit schematic of the function X1 X 2 + X 3 created in Quartus II.
Waveform of the function in Quartus II
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The VHDL code for the function X1 X 2 + X 3 generated with Quartus II..
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY sss IS
PORT
(
x1 : IN STD_LOGIC;
x2 : IN STD_LOGIC;
x3 : IN STD_LOGIC;
f : OUT STD_LOGIC
);
END sss;
ARCHITECTURE bdf_type OF sss IS
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_2 <= x1 AND SYNTHESIZED_WIRE_0;
f <= SYNTHESIZED_WIRE_1 OR SYNTHESIZED_WIRE_2;
SYNTHESIZED_WIRE_0 <= NOT(x2);
SYNTHESIZED_WIRE_1 <= NOT(x3);
END bdf_type;
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Question 4
Write the VHDL Code for the 4-bit comparator
Logic symbol for a 4-bit comparator (Floyd, Digital Fundamentals)
Truth table for a 4-bit comparator
Comparing Inputs OutputsA3, B3 A2, B2 A1, B1 A0, BO A > B A < B A = B
A3 > B3 X X X H L LA3 < B3 X X X L H LA3 = B3 A2 > B2 X X H L LA3 = B3 A2 < B2 X X L H LA3 = B3 A2 = B2 A1 > B1 X H L LA3 = B3 A2 = B2 A1 < B1 X L H LA3 = B3 A2 = B2 A1 = B1 A0>B0 H L LA3 = B3 A2 = B2 A1 = B1 A0<B0 L H LA3 = B3 A2 = B2 A1 = B1 A0=B0 H L LA3 = B3 A2 = B2 A1 = B1 A0=B0 L H LA3 = B3 A2 = B2 A1 = B1 A0=B0 L L H
H = High, L = Low, X= Don’t care.
Truth table of a 4-bit Comparing by comparing inputs (Dr AL–Khalili, et al)
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VCCa3 INPUT
VCCb3 INPUT
VCCa2 INPUT
VCCb2 INPUT
VCCa1 INPUT
VCCb1 INPUT
VCCa0 INPUT
VCCb0 INPUT
AeqBOUTPUT
AltBOUTPUT
AgtBOUTPUT
XNOR
inst
XNOR
inst1
XNOR
inst2
XNOR
inst3
AND4
inst4
AND2
inst5
AND3
inst6
AND4
inst7
AND3
inst8
OR4
inst10
NOR2
inst11NOT
inst22
NOT
inst23
NOT
inst24
NOT
inst25
AND3
inst9
Block diagram schematic for a 4-bit comparator drawn with Quartus II software
Quartus II Simulator vector waveform for a 4-bit comparator
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Quartus II simulation vector waveform for a 4-bit comparator, with smaller period to capture more numbers.
VHDL Code for a 4-bit comparator:
LIBRARY ieee;USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Mysim4bitcomp IS PORT(
a3 : IN STD_LOGIC;b3 : IN STD_LOGIC;a2 : IN STD_LOGIC;b2 : IN STD_LOGIC;a1 : IN STD_LOGIC;b1 : IN STD_LOGIC;a0 : IN STD_LOGIC;b0 : IN STD_LOGIC;AeqB : OUT STD_LOGIC;AltB : OUT STD_LOGIC;AgtB : OUT STD_LOGIC
);END Mysim4bitcomp;
ARCHITECTURE bdf_type OF Mysim4bitcomp IS
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_23 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
BEGIN AeqB <= SYNTHESIZED_WIRE_5;AgtB <= SYNTHESIZED_WIRE_4;
SYNTHESIZED_WIRE_21 <= NOT(a3 XOR b3);
SYNTHESIZED_WIRE_22 <= NOT(a2 XOR b2);
SYNTHESIZED_WIRE_4 <= SYNTHESIZED_WIRE_0 OR SYNTHESIZED_WIRE_1 OR SYNTHESIZED_WIRE_2 OR SYNTHESIZED_WIRE_3;
AltB <= NOT(SYNTHESIZED_WIRE_4 OR SYNTHESIZED_WIRE_5);
SYNTHESIZED_WIRE_23 <= NOT(a1 XOR b1);
SYNTHESIZED_WIRE_10 <= NOT(b3);
SYNTHESIZED_WIRE_12 <= NOT(b2);
SYNTHESIZED_WIRE_15 <= NOT(b1);
SYNTHESIZED_WIRE_17 <= NOT(b0);
SYNTHESIZED_WIRE_9 <= NOT(a0 XOR b0);
SYNTHESIZED_WIRE_5 <= SYNTHESIZED_WIRE_21 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_23 AND SYNTHESIZED_WIRE_9;
SYNTHESIZED_WIRE_0 <= SYNTHESIZED_WIRE_10 AND a3;
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SYNTHESIZED_WIRE_3 <= SYNTHESIZED_WIRE_21 AND SYNTHESIZED_WIRE_12 AND a2;
SYNTHESIZED_WIRE_1 <= SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_21 AND SYNTHESIZED_WIRE_15 AND a1;
SYNTHESIZED_WIRE_20 <= SYNTHESIZED_WIRE_21 AND SYNTHESIZED_WIRE_17 AND a0;
SYNTHESIZED_WIRE_2 <= SYNTHESIZED_WIRE_23 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_20;
END bdf_type;
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Discussion
These questions are intended to make sense of the discussions relating to the basic principles and functions in defining specifications and providing solutions to engineering problems and innovations involving the use of embedded processors. It is pertinent that a basic understanding of the fundamentals of formalized hardware and software design process is established by way of analyzing and evaluating digital design using specialist software tools. This study is based on the 8051 microcontroller and Quartus II software.
Embedded systems require coded instructions to perform certain desired tasks. Questions 1 and 2 are to basically demonstrate how to program the 8051 microcontroller and have the coded (program) function run the computer chip. C programming was used in both of the questions. Question 1 is about writing the last two (2) digits of a student’s Stamford ID in the addresses 40h to 6Fh. The ID used is 1119930, which makes the last two (2) digits 30 in this case. the flowchart of Loading ID = 30 in 8051 RAM Addresses 40h to 6Fh above helps in creating a visual flow of how the coding was done. An initialization of variables and header files was done as well as loading the variable A with 30. This variable is used in the program to store and duplicate the value to be written in the addresses specified while pointers was used in a ‘for’ loop function to load the addresses. The code and a view of the memory window, showing 30 written at the addresses is as shown in question 1 part of the procedure and results above.
A counting operation was performed in question 2. The last digits four (4) in this case is 9930 and it was required that a code is written to count down from this number, reset and countdown again continuously. A similar flow is used here a ‘for’ loop is used to decrement the variable A which contains is originally loaded with 9930 and decrements until 0. A reset check is done by the line: if (A == 0){A = 9930; } after which the counting continues as long as the system is on. These two exercise can be downloaded into the UEL-51 Mk II kit for demonstration. A picture of UEL-51 Mk II is shown in the appendix.
Digital design and VHDL coding was explored in questions 3 and 4. A three variable function was question was given question 3 which is HIGH at 0,2,4,5 and 6. A truth was made for the function before minimizing the function to reduce the number of gates used to save power consumed by the circuit, cost and space. K-mapping and Boolean algebra were used to check the simplification. The function was found to be X1X 2+ X 3 after simplification. A circuit schematic was made in Quartus II from which the vector waveform and VHDL codes was generated and tallies with the truth table. The result is shown in the results for question 3.
Comparators are used to check the equality of numbers. Using giving equal to, less than or greater than relationship between numbers. A bit-bit comparator means 4 bits can be compared. The procedure used to achieve the VHDL code for the comparator is similar to that of the function design in question 3. Since the comparator circuit was already provided it was drawn in Quartus II to generate the vector waveform and VHDL code which tallies with the truth table as shown in the results for question 4 above.
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Summary
Question 1 = program to write 30 into 8051 addresses 40h to 6Fh, c program coding, flowchat and results shown in the results above.
Question 2 = program to continuously countdown from 9930 using c programming in 8051. Flowchart, coding and results shown.
Questions 3 and 4 is about simulations to generate VHDL codes.
Conclusion
That practice a very important component of learning makes this exercise has been very beneficial; it has enabled a demonstration of formalized process and tools used in developing digital design solutions. The 8051 microcontroller was programmed to perform addressing and counting, using specified digits of Stanford student ID numbers. Flowcharts, c program codes and well as the results obtained has been presented here.
Digital design was performed in questions 3 and 4. The function in question 3 was minimized using k-map and also by Boolean algebra to reduce space circuit occupies, cost and power that would be consumed if left otherwise. While in question four (4) a 4-bit comparator which a setup that can show the equality, greater than and less than relationship between two 4-bit numbers. These were drawn in Quartus II and simulated to generate the respective vector waveforms and VHDL codes.
With every task successfully completed, this experiment exercised has been studies and appreciated.
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References
CIO (2012) integrated circuit (IC) [online] available from: http://searchcio-midmarket.techtarget.com/definition/integrated-circuit [Accessed: April 2, 2012]
Dr. A.J.AL–Khalili, et al (2012) Design of a 4-bit comparator [online] Department of Electrical and Computer Engineering Concordia University Montreal, Quebec. Available from: http://users.encs.concordia.ca/~asim/COEN_6511/Projects/final6511report.pdf [Accessed: April 2, 2012]
Engineer’s World (January 15, 2011) VHDL Code for 4 Bit Comparator [online]. Available from: http://engineersworld.wordpress.com/2011/01/15/vhdl-code-for-4-bit-comparator/ [March 23, 2012].
Intel (1994) MCS-51 Microcontroller Family User’s Manual [online] Available from: http://eeweb1.poly.edu/networks/specs/27238302.pdf [Accessed April 1, 2012]
John Wharton (1980) An Introduction to the Intel MCS-51TM Single-Chip Microcomputer Family. Intel Coporation.
Lab Manual. (2012). Introduction to Quartus II, (EE3003) Embedded Systems and IC Design. Stamford College, PJ, Malaysia. Available in print [Accessed: April, 2012].
Thomas Floyd (2006). 9th edition. New Jersey: Person Education International.
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Appendix
The UEL-51 MK II
Block diagram of the Basic Structure of the 8051 Architecture Core.
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