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Simulator for PowerPC

TRACE32 Online Help

TRACE32 Directory

TRACE32 Index

TRACE32 Documents ......................................................................................................................

TRACE32 Instruction Set Simulators ..........................................................................................

Simulator for PowerPC .............................................................................................................. 1

TRACE32 Simulator License .................................................................................................. 4

Quick Start of the Simulator ................................................................................................... 5

Peripheral Simulation ............................................................................................................. 7

Troubleshooting ...................................................................................................................... 7

FAQ ........................................................................................................................................... 7

Memory Classes ...................................................................................................................... 8

General SYStem Commands .................................................................................................. 9

SYStem.CPU Select CPU type 9

SYStem.CpuAccess Run-time memory access (intrusive) 9

SYStem.MemAccess Real-time memory access (non-intrusive) 10

SYStem.Mode Establish the communication with the simulator 10

SYStem.Option DisMode Simulator operation mode 11

SYStem.Option DUALPORT Run-time memory access for all windows 11

SYStem.Option IMASKASM Disable interrupts while single stepping 12

SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 12

SYStem.Option MMUSPACES Enable space IDs 12

SYStem.Option.NOTRAP Use alternative software breakpoint instruction 13

SYStem.Option OVERLAY Enable overlay support 14

CPU specific MMU Commands .............................................................................................. 15

MMU.DUMP Page wise display of MMU translation table 15

MMU.List Compact display of MMU translation table 16

MMU.SCAN Load MMU table from CPU 17

Support ..................................................................................................................................... 19

Available Tools 19

Compilers 19

Target Operating Systems 21

3rd-Party Tool Integrations 22

Products ................................................................................................................................... 23

Product Information 23

Simulator for PowerPC 1 ©1989-2018 Lauterbach GmbH

Order Information 23


Simulator for PowerPC

Version 22-Mar-2018

All general commands are described in the “IDE Reference Guide” (ide_ref.pdf) and “General Commands Reference”.


TRACE32 Simulator License

[build 68859 - DVD 02/2016]

The extensive use of the TRACE32 Instruction Set Simulator requires a TRACE32 Simulator License.

For more information, see www.lauterbach.com/sim_license.html.


www.lauterbach.com/sim_license.html

Quick Start of the Simulator

To start the simulator, proceed as follows:

1. Select the device prompt for the ICD Debugger and reset the system.

The device prompt B:: is normally already selected in the command line. If this is not the case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start directly after booting TRACE32.

2. Specify the CPU specific settings.

The default values of all other options are set in such a way that it should be possible to work without modification. Please consider that this is probably not the best configuration for your target.

B::

RESet

SYStem.CPU <cpu_name>


3. Enter debug mode.

This command resets the CPU and enters debug mode. After this command is executed it is possible to access memory and registers.

4. Load the program.

The format of the Data.LOAD command depends on the file format generated by the compiler. Refer to Supported Compilers to find the command that is necessary for your compiler.

A detailed description of the Data.LOAD command and all available options is given in the reference guide.

5. Start-up example

A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII file format) and executed with the command DO <filename>.

*) These commands open windows on the screen. The window position can be specified with the WinPOS command.

SYStem.Up

Data.LOAD.format <filename> ; load program and symbols

B:: ; Select the ICD device prompt

WinCLEAR ; Clear all windows

SYStem.CPU <cpu_name> ; Select CPU type

SYStem.Up ; Reset the target and enter; debug mode

Data.LOAD.format <filename> ; Load the application

Register.Set pc main ; Set the PC to function main

PER.view ; Show clearly arranged peripherals ; in window *)

Data.List ; Open source code window *)

Register /SpotLight ; Open register window *)

Frame.view /Locals /Caller ; Open the stack frame with ; local variables *)

Var.Watch %Spotlight flags ast ; Open watch window for ; variables *)


Peripheral Simulation

For more information, see “API for TRACE32 Instruction Set Simulator” (simulator_api.pdf).

Troubleshooting

No information available

FAQ

No information available


Memory Classes

The following memory classes are available:

If the cache is disabled, memory accesses to the memory classes IC or DC are realized by TRACE32-ICD as reads and writes to physical memory.

Memory Class Description

P Program

D Data

SPR Special Purpose Register

DCR Device Control Register

PMR Performance Control Register

IC Instruction Cache

DC Data Cache

NC No Cache (only physically memory)


General SYStem Commands

SYStem.CPU Select CPU type

SYStem.CpuAccess Run-time memory access (intrusive)

Default: Denied.

Format: SYStem.CPU <cpu>

<cpu>: 505 | 509 | 555 | 821 | 860

Format: SYStem.CpuAccess Enable | Denied | Nonstop

Enable Allow intrusive run-time memory access.Since a non-intrusive run-time memory access (SYStem.MemoryAccess CPU) is available for all TRACE32 instruction set simulators, there is no need for an intrusive run-time memory access.

Denied Lock intrusive run-time memory access.

Nonstop Lock all features of the debugger that affect the run-time behavior.Nonstop reduces the functionality of the debugger to:• run-time access to memory and variables• trace displayThe debugger inhibits the following:• to stop the program execution• all features of the debugger that are intrusive (e.g. action Spot for

breakpoints, performance analysis via StopAndGo mode, condi-tional breakpoints etc.)


SYStem.MemAccess Real-time memory access (non-intrusive).

SYStem.Mode Establish the communication with the simulator

Default: Down.

Selects the target operating mode.

If the mode Go is selected, this mode will be entered, but the control button in the SYStem.state window jumps to the mode Up.

Format: SYStem.MemAccess CPU | Denied | <cpu_specific>SYStem.ACCESS (deprecated)

CPU Real-time memory access during program execution to target is enabled.

Denied (default) Real-time memory access during program execution to target is disabled.

Format: SYStem.Mode <mode>

<mode>: DownNoDebugGoUp

Down The CPU is in reset. Debug mode is not active. Default state and state after fatal errors.

NoDebug The CPU is running. Debug mode is not active. Debug port is tristate. In this mode the target should behave as if the debugger is not connected.

Go The CPU is running. Debug mode is active. After this command the CPU can be stopped with the break command or if any break condition occurs.

Up The CPU is not in reset but halted. Debug mode is active. In this mode the CPU can be started and stopped. This is the most typical way to activate debugging.


SYStem.Option DisMode Simulator operation mode

MPC5XXX/SPC5XX only.

This command sets the operation mode for the simulator.

SYStem.Option DUALPORT Run-time memory access for all windows

Default: OFF.

Dualport access of memory while simulation in running.

Format: SYStem.Option DisMode <mode>

<mode>: ACCESSAUTOFLEVLE

AUTO (default) Behavior depending on CPU selection. VLE/FLE operation for VLE/FLE-only processors, others: see ACCESS

ACCESS Default: Standard PowerPC (FLE) instruction set. Simulator supports mixed FLE/VLE code execution if MMU simulation is enabled.

FLE Simulator is configured to execute code compiled for the standard PowerPC instruction set (fixed length encoding).

VLE Simulator is configured to execute code compiled for VLE (variable length encoding).

Format: SYStem.Option DUALPORT [ON | OFF]


SYStem.Option IMASKASM Disable interrupts while single stepping

Default: OFF.

If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step.

SYStem.Option IMASKHLL Disable interrupts while HLL single stepping

Default: OFF.

If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step.

SYStem.Option MMUSPACES Enable space IDs

Default: OFF.

Format: SYStem.Option IMASKASM [ON | OFF]

Format: SYStem.Option IMASKHLL [ON | OFF]

NOTE: Do not enable this option for code that disables MSR_EE. The debugger will disable MSR_EE while the CPU is running and restore it after the CPU stopped. If a part of the application is executed that disables MSE_EE, the debugger cannot detect this change and will restore MSE_EE.

Format: SYStem.Option MMUSPACES [ON | OFF]SYStem.Option MMUspaces [ON | OFF] (deprecated)SYStem.Option MMU [ON | OFF] (deprecated)


Enables the use of space IDs for logical addresses to support multiple address spaces.

Examples:

SYStem.Option.NOTRAP Use alternative software breakpoint instruction

Defines which instruction is used to implement software breakpoints.

NOTE: SYStem.Option MMUSPACES should not be used if only one translation table is used on the target.

If a debug session requires space IDs, you must observe the following sequence of steps:

1. Activate SYStem.Option MMUSPACES.

2. Load the symbols with Data.LOAD.

Otherwise, the internal symbol database of TRACE32 may become inconsistent.

;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x012A:Data.dump D:0x012A:0xC00208A

;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x0203:Data.dump D:0x0203:0xC00208A

Format: SYStem.Option NOTRAP <type>

<type>: ON | OFF | FPU | ILL

OFF Use TRAP instructions as software breakpoint (default setting).

ONILL

Using illegal opcode as breakpoint instruction, TRAP instruction available for use in application.

FPU Not supported in simulator. Same effect as ON.


SYStem.Option OVERLAY Enable overlay support

Default: OFF.

Format: SYStem.Option OVERLAY [ON | OFF | WithOVS]

ON Activates the overlay extension and extends the address scheme of the debugger with a 16 bit virtual overlay ID. Addresses therefore have the format <overlay_id>:<address>. This enables the debugger to handle overlaid program memory.

OFF Disables support for code overlays.

WithOVS Like option ON, but also enables support for software breakpoints. This means that TRACE32 writes software breakpoint opcodes both to the execution area (for active overlays) and to the storage area. In this way, it is possible to set breakpoints into inactive overlays. Upon activation of the overlay, the target’s runtime mechanisms copies the breakpoint opcodes to the execution area. For using this option, the storage area must be readable and writable for the debugger.

SYStem.Option OVERLAY ON Data.List 0x2:0x11c4 ; Data.List <overlay_id>:<address>


CPU specific MMU Commands

MMU.DUMP Page wise display of MMU translation table

Displays the contents of the CPU specific MMU translation table.

• If called without parameters, the complete table will be displayed.

• If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter.

The optional <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory.

CPU specific tables:

Format: MMU.DUMP <table> [<range> | <addr> | <range> <root> | <addr> <root>]MMU.<table>.dump (deprecated)

<table>: PageTableKernelPageTableTaskPageTable <magic_number> | <task_id> | <task_name><cpu_specific_tables>

PageTable Display the current MMU translation table entries of the CPU. This command reads all tables the CPU currently uses for MMU translation and displays the table entries.

KernelPageTable Display the MMU translation table of the kernel.If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and displays its table entries.

TaskPageTable <magic_number> | <task_id> | <task_name>

Display the MMU translation table entries of the given process. In MMU based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and displays its table entries.See also the appropriate OS awareness manuals: RTOS Debugger for <x>.For information about the parameters, see “What to know about Magic Numbers, Task IDs and Task Names” (general_ref_t.pdf).

ITLB Displays the contents of the Instruction Translation Lookaside Buffer.

DTLB Displays the contents of the Data Translation Lookaside Buffer.


MMU.List Compact display of MMU translation table

Lists the address translation of the CPU-specific MMU table. If called without address or range parameters, the complete table will be displayed.

If called without a table specifier, this command shows the debugger-internal translation table. See TRANSlation.List.

If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter.

TLB Displays the contents of the Translation Lookaside Buffer.

TLB0 Displays the contents of the Translation Lookaside Buffer 0.



BAT Displays the contents of the BAT table.

PTE Displays the contents of the PTE table.

Format: MMU.List <table> [<range> | <addr> | <range> <root> | <addr> <root>] MMU.<table>.List (deprecated)

<table>: PageTableKernelPageTableTaskPageTable <magic_number> | <task_id> | <task_name> | <space_id>:0x0

<root> The optional <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory.

PageTable List the current MMU translation of the CPU. This command reads all tables the CPU currently uses for MMU translation and lists the address translation.


MMU.SCAN Load MMU table from CPU

Loads the CPU-specific MMU translation table from the CPU to the debugger-internal translation table. If called without parameters, the complete page table will be loaded. The loaded address translation can be viewed with TRANSlation.List.

If the command is called with either an address range or an explicit address, page table entries will only be loaded if their logical address matches with the given parameter.

KernelPageTable List the MMU translation table of the kernel.If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and lists its address translation.


List the MMU translation of the given process. In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and lists its address translation.See also the appropriate OS awareness manuals: RTOS Debugger for <x>.For information about the parameters, see “What to know about Magic Numbers, Task IDs and Task Names” (general_ref_t.pdf).

Format: MMU.SCAN <table> [<range> <address>]MMU.<table>.SCAN (deprecated)

<table>: PageTableKernelPageTableTaskPageTable <magic_number> | <task_id> | <task_name>ALL<cpu_specific_tables>


CPU specific tables:

PageTable Load the current MMU address translation of the CPU. This command reads all tables the CPU currently uses for MMU translation, and copies the address translation into the debugger-internal translation table.

KernelPageTable Load the MMU translation table of the kernel.If specified with the MMU.FORMAT command, this command reads the table of the kernel and copies its address translation into the debugger-internal translation table.


Load the MMU address translation of the given process. In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and copies its address translation into the debugger-internal translation table.See also the appropriate OS awareness manual: RTOS Debugger for <x>.For information about the parameters, see “What to know about Magic Numbers, Task IDs and Task Names” (general_ref_t.pdf).

ALL Load all known MMU address translations. This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debugger-internal translation table. See also the appropriate OS awareness manual: RTOS Debugger for <x>.

TLB1 Loads the translation table 1from the CPU to the debugger internal translation table.


Support

Available Tools

Compilers

CP

U

ICE

FIR

E

ICD

DE

BU

G

ICD

MO

NIT

OR

ICD

TR

AC

E

PO

WE

RIN

TE

GR

ATO

R

INS

TR

UC

TIO

NS

IMU

LA

TOR

MPC5200 YES YES YESMPC5200B YES YES YES

Language Compiler Company Option Comment

ADA GNAT PRO AdaCore ELF/DWARF not all ADA constructs/DWARF

ADA GNAT Free Software Foundation, Inc.

ELF/DWARF

C CXPPC Cosmic Software ELF/DWARFC XCC-V GAIO Technology Co.,

Ltd.SAUF

C GREEN-HILLS-C Greenhills Software Inc. ELF/DWARFC MCCPPC Mentor Graphics

CorporationELF/DWARF

C CC NXP Semiconductors XCOFFC ULTRA-C Radisys Inc. ROFC HIGH-C Synopsys, Inc ELF/DWARFC DCPPC TASKING ELF/DWARFC D-CC Wind River Systems IEEEC D-CC Wind River Systems COFFC D-CC Wind River Systems ELF/DWARFC++ GCC Free Software

Foundation, Inc.ELF/DWARF

C++ GREEN-HILLS-C++

Greenhills Software Inc. ELF/DWARF

C++ CCCPPC Mentor Graphics Corporation

ELF/DWARF


C++ MSVC Microsoft Corporation EXE/CV5 WindowsCEC++ HIGH-C++ Synopsys, Inc ELF/DWARFC++ D-C++ Wind River Systems ELF/DWARFC++ GCCPPC Wind River Systems ELF/STABSC/C++ GNAT PRO AdaCore ELF/DWARFC/C++ GCC HighTec EDV-Systeme

GmbHELF/DWARF

C/C++ CODEWARRIOR NXP Semiconductors ELF/DWARFGCC GCC Free Software

Foundation, Inc.ELF/DWARF

JAVA FASTJ Wind River Systems ELF/DWARF

Language Compiler Company Option Comment


Target Operating Systems

Company Product Comment

KadakProducts Ltd. AMXOracle Corporation ChorusOSCMX Systems Inc. CMX-RTXDDC-I, Inc. DEOS implemented by DDC-IeCosCentric Limited ECOS 1.3, 2.0 and 3.0Elektrobit Automotive GmbH

Elektrobit tresos via ORTI

ETAS GmbH ERCOSEK via ORTIEvidence Erika via ORTIfreeRTOS FreeRTOS up to v9HIPPEROS S.A. HIPPEROS implemented by HIPPEROS- Linux Kernel Version 2.4 and 2.6, 3.x, 4.xMontaVista Software, LLC Linux 3.0, 3.1, 4.0, 5.0LynuxWorks Inc. LynxOS 3.1.0, 3.1.0a, 4.0NXP Semiconductors MQX 3.x and 4.xSynopsys, Inc MQX 2.40 and 2.50- NetBSDMISPO Co. Ltd. NORTiMentor Graphics Corporation

Nucleus PLUS

Radisys Inc. OS-9Enea OSE Systems OSE Delta 4.x and 5.x- OSEK via ORTINXP Semiconductors OSEKturbo via ORTI/former MetrowerksOSEKSysgo AG PikeOS up to 4.2.1Elektrobit Automotive GmbH

ProOSEK via ORTI

Wind River Systems pSOS+ 2.1 to 2.5, 3.0, with TRACE32QNX Software Systems QNX 6.0 to 7.0RTEMS RTEMS up to v5Quadros Systems Inc. RTXC 3.2Quadros Systems Inc. RTXC QuadrosSciopta ScioptaMicro Digital Inc. SMX 3.4 to 4.3Express Logic Inc. ThreadX 3.0, 4.0, 5.0Micrium Inc. uC/OS-II 2.0 to 2.92- uITRON HI7000, RX4000, NORTi,PrKernelMentor Graphics Corporation

VRTXsa

Wind River Systems VxWorks 5.x to 7.x


3rd-Party Tool Integrations

CPU Tool Company Host

WINDOWS CE PLATF. BUILDER

- Windows

CODE::BLOCKS - -C++TEST - WindowsADENEO -X-TOOLS / X32 blue river software GmbH WindowsCODEWRIGHT Borland Software

CorporationWindows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Windows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Linux

EASYCODE EASYCODE GmbH WindowsECLIPSE Eclipse Foundation, Inc WindowsCHRONVIEW Inchron GmbH WindowsLDRA TOOL SUITE LDRA Technology, Inc. WindowsUML DEBUGGER LieberLieber Software

GmbHWindows

SIMULINK The MathWorks Inc. WindowsATTOL TOOLS MicroMax Inc. WindowsVISUAL BASIC INTERFACE

Microsoft Corporation Windows

LABVIEW NATIONAL INSTRUMENTS Corporation

Windows

RAPITIME Rapita Systems Ltd. WindowsRHAPSODY IN MICROC IBM Corp. WindowsRHAPSODY IN C++ IBM Corp. WindowsDA-C RistanCASE WindowsTRACEANALYZER Symtavision GmbH WindowsECU-TEST TraceTronic GmbH WindowsUNDODB Undo Software LinuxTA INSPECTOR Vector WindowsVECTORCAST UNIT TESTING

Vector Software Windows

VECTORCAST CODE COVERAGE

Vector Software Windows

POWERPC OSE ILLUMINATOR Enea OSE Systems WindowsPOWERPC DIAB RTA SUITE Wind River Systems Windows


Products

Product Information

Order Information

OrderNo Code Text

LA-2801L SIMULATOR-PPC-FL

1 User Float. Lic. TRACE32 PPC SimulatorFloating license to use the TRACE32 Instruction SetSimulator for automated tests via script languagePRACTICE or via the TRACE32 Remote APIsupports PowerPCsfor Windows32, Windows64, Linux32, Linux64and Solaris, other platforms on requestfloating license via RLM (Reprise License Manager)Please add the RLM HostID of the license serverto your order (please see our FAQ)

Order No. Code Text

LA-2801L SIMULATOR-PPC-FL 1 User Float. Lic. TRACE32 PPC Simulator
