Single/Multiphase, Step-Down, DC-DC Converter Delivers Up to 25A Per Phase · 2010-10-20 · MAX8686 Single/Multiphase, Step-Down, DC-DC Converter Delivers Up to 25A Per Phase _____

General DescriptionThe MAX8686 current-mode, synchronous PWM step-down regulator with integrated MOSFETs operates froma 4.5V to 20V input supply and generates an adjustableoutput voltage from 0.7V to 5.5V while delivering up to25A per phase.

The MAX8686 employs a peak current-mode architec-ture that operates with an adjustable switching frequencyfrom 300kHz to 1MHz. An adjustable current-limit thresh-old allows for optimization for different applications withdifferent load currents. Inductor current sense isachieved either using an external sense resistor or usinga lossless inductor current-sense scheme. The foldbackand hiccup current limit reduces the power dissipationduring overload or short-circuit conditions and allows forautorecovery when the fault condition is removed.

The MAX8686 offers the ability to start up monotonicallyeven when there is a prebias output voltage. In addi-tion, an adjustable soft-start capability allows for a con-trolled turn-on. The MAX8686 features an accurate 1%reference and offers a reference input that allows for ahigher accuracy reference to be used for voltage track-ing applications such as DDR memory.

The MAX8686 can be paralleled (up to eight) togetherin a true multiphase mode to deliver up to 200A of out-put current. When operating in this mode, this deviceachieves better than 10% current balance betweenphases at full load. The MAX8686 supports program-mable phase shedding to improve system efficiencyduring light load conditions.

Other features include an enable input and a power-OK(POK) indicator used for power sequencing. TheMAX8686 also features latch overvoltage protectionthat turns on the low-side MOSFET when the outputvoltage exceeds 120% of the nominal voltage. TheMAX8686 is offered in a thermally enhanced 40-pin,6mm x 6mm TQFN package.

ApplicationsPOL Power Supplies

Module Replacements

Telecom Equipment

Networking Equipment

Servers

DDR Memory

Features Operating Range from 4.5V to 20V Input Supply

1% Reference Voltage Accuracy Over Temperature

Reference Input (REFIN) for Output Tracking orSystem Reference Voltage

Adjustable Switching Frequency from 300kHz to 1MHz

Single/Multiphase Operation Delivers Up to25A/200A with Integrated MOSFETs

Adjustable Current Limit

Monotonic Output Voltage at Startup (Prebias)

Output Sink and Source Current Capability

Adjustable Soft-Start

Thermal-Overload Protection

Output Overvoltage Protection

Thermally Enhanced 6mm x 6mm TQFN Package (4W)

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Single/Multiphase, Step-Down,DC-DC Converter Delivers Up to 25A Per Phase

________________________________________________________________ Maxim Integrated Products 1

IN

POKOUTPUT

ENABLEINPUT

BST

LX

VIN = 12V

VOUT = 1.2V/25APGND

PHASE/REFO

COMP

EN/SLOPE

FREQ SS GND ILIM

MAX8686REFINRS+

RS-

CS+

CS-

POK

Typical Application Circuit

Ordering Information

19-4113; Rev 1; 10/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX8686ETL+ -40°C to +85°C 40 TQFN-EP*

+Denotes a lead-free package.*EP = Exposed pad.

Pin Configuration appears at end of data sheet.

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,CAVL = 0.22μF, CFREQ = 270pF, TA = +25°C, unless otherwise noted.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

IN, INA to PGND.....................................................-0.3V to +22VBST, DH to LX...........................................................-0.3V to +6VBST to PGND..........................................................-0.3V to +28VLX to PGND...........................-0.3V to (VIN + 0.3V) (-2V for 50ns)BST to VL................................................................-0.3V to +22VAVL to GND.................................................-0.3V to (VVL + 0.3V)COMP, ILIM, FREQ, PHASE/REFO, RS+, RS-, POK, REFIN,

CS+, CS- to GND ..................................-0.3V to (VAVL + 0.3V)VL to PGND ..............................................................-0.3V to +6VEN/SLOPE to GND ...................................................-0.3V to +6VRTN to PGND to GND to GFREQ ..........................-0.3V to +0.3VIN Continuous Current.....................................................20ARMS

LX Continuous Current ....................................................25ARMSContinuous Power Dissipation (TA = +70°C) (Note 1)

40-Pin TQFN (derate 50mW/°C above +70°C) ..........4000mWθJC (thermal resistance from junction to exposed pad)

(Note 1) ......................................................................3.5°C/WθJT (thermal resistance from junction to top) (Note 1) ...3.9°C/WOperating Temperature Range ...........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-65°C to +150°CLead Temperature (soldering, 10s) .................................+300°CSoldering Temperature (reflow) .......................................+260°C

PARAMETER CONDITIONS MIN TYP MAX UNITS

GENERAL

Operating Input-Voltage Range VINA = VIN , TA = -40°C to +85°C 6 20 V

Operating Input-Voltage Range VIN = VINA = VVL = VAVL, TA = -40°C to +85°C 4.5 5.5 V

TA = +25°C 450IN/INA Shutdown Supply Current

VEN/SLOPE = 0V,VIN = VINA = 20V TA = +85°C 500

μA

IN/INA Quiescent Supply CurrentVRS+ = 1.1V, no switching; VIN = VINA = 20V,TA = -40°C to +85°C

5.5 6.6 mA

Rising, TA = -40°C to +85°C 4.2 4.35 4.45AVL Undervoltage Lockout TripLevel Falling 4.03

V

VL Output Voltage6V ≤ VIN = VINA ≤ 20V, 1mA ≤ IVL ≤ 30mA,TA = -40°C to +85°C

5.2 5.4 5.5 V

SOFT-START (SS)

SS Shutdown Resistance VEN/SLOPE = 0V (master mode) 20 100 ΩSS Soft-Start Current VSS = 0.4V and 1.1V, TA = -40°C to +85°C 19 25 31 μA

PHASE COMPARATOR AND REFERENCE (PHASE/REFO)

Reference Output VoltageMeasured at PHASE/REFO (master mode),TA = -40°C to +85°C

3.267 3.300 3.333 V

PHASE Comparator OffsetVRS- = VAVL (slave mode), VPHASE = 0.3V and 2.5V,TA = -40°C to +85°C

-20 +20 mV

REFIN INPUT

REFIN Input Bias Current VREFIN = 0.7V or 3.3V -500 +500 nA

REFIN Input Voltage Range 0 3.3 V

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layerboard. For detailed information on package thermal considerations see www.maxim-ic.com/thermal-tutorial.

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_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,CAVL = 0.22μF, CFREQ = 270pF, TA = +25°C, unless otherwise noted.) (Note 2)


ERROR AMPLIFIER

VREFIN = 3.3V 3.267 3.3 3.333Remote-Sense Accuracy(Including Error Amplifier Offset)

Measure as VRS+ - VRS-(TA = -40°C to +85°C) VREFIN = 0.7V 0.693 0.7 0.707

V

Transconductance TA = -40°C to +85°C 1.1 1.7 2.6 mS

COMP Source Current VRS+ - VRS- = 1.3V 220 300 μA

COMP Sink Current VRS+ - VRS- = 0.7V 220 300 μA

COMP Shutdown Resistance VEN/SLOPE = 0V 20 100 ΩRS+/RS- Input Leakage Current 0.2 1.5 μA

RS+ Input Common-Mode Range VIN = VINA = VVL = VAVL = 4.5V, VRS- = 100mV 0 3.4 V

RS- Input Common-Mode Range -100 +100 mV

CURRENT-SENSE AMPLIFIER

Input Offset VoltageMeasure at CS+ and CS-, VCS+ = VCS- = 0.7V and 5.5V(TA = -40°C to +85°C)

-1.5 +1.5 mV

Current-Sense Amplifier GainVCS- = 0 to 5V, VCS+ - VCS- = 30mV,TA = -40°C to +85°C

29.0 30.5 32.0 V/V

Input Bias Current VCS+ = VCS- = 5.5V and 0V -4 +4 μA

CURRENT LIMIT

ILIM Output Current VILIM = 2V, TA = -40°C to +85°C 9 10 11 μA

RILIM = 122kΩ 16 20 23Current-Limit Threshold

Measure as VCS+ - VCS-(TA = -40°C to +85°C) RILIM = 275kΩ 38 45 52

mV

COMP Clamp Voltage High RILIM = 275kΩ, VREFIN = 3.3V, VRS+ - VRS- = 2V 3.6 3.8 4.0 V

COMP Clamp Voltage Low VREFIN = 3.3V, VRS+ - VRS- = 3.35V 0.54 0.6 0.66 V

Maximum Peak Positive CurrentThreshold

RILIM = 275kΩ, no slope compensation 54 mV

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4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)(VIN = VINA = 12V, VL = AVL, VREFIN = 1V, VRS+ - VRS- = 1V, VRS- = 0V, VEN/SLOPE = 1.25V, VCS+ = VCS- = 1V, RILIM = 122kΩ, CVL = 1μF,CAVL = 0.22μF, CFREQ = 270pF, TA = +25°C, unless otherwise noted.) (Note 2)

Note 2: Specifications to TA = -40°C are guaranteed by design and not production tested.


OSCILLATOR (FREQ)

Source Current VFREQ = 2V, TA = -40°C to +85°C 480 500 520 μA

CFREQ = 180pF 0.8 1 1.2 MHzSwitching Frequency

CFREQ = 580pF 240 300 360 kHz

Minimum On-Time 100 ns

FREQ Discharge Resistance 10 50 ΩRamp Peak Voltage 2.60 VAVL/2 2.85 V

SLOPE COMPENSATION (EN/SLOPE)

VSLOPE Range 1.25 2.50 V

SLOPE Source Current 8 10 12 μA

THERMAL PROTECTION

Thermal Shutdown Rising temperature 160 °C

Thermal-Shutdown Hysteresis 30 °C

POWER-OK (POK)

VOUT rising 87 90 93POK Threshold

VOUT falling 87%VOUT

POK Output Voltage Low VRS+ - VRS- = 0.8V, IPOK = 2mA 25 200 mV

POK Leakage Current VPOK = 5.5V 0.001 1 μA

OVERVOLTAGE OUTPUT PROTECTION (OVP)

Overvoltage Fault Trip LevelVREFIN = 3.3V, VRS+ rising, percentage of VOUT inregulation

115 120 125 %

ENABLE (EN/SLOPE)

EN Logic-High 1.2 V

EN Logic-Low 0.7 V

BST

Internal PMOS On-Resistance 8 Ω

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SINGLE-PHASE EFFICIENCYvs. LOAD CURRENT

MAX

8686

toc0

1

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

20155 10

77.5

80.0

82.5

85.0

90.0

87.5

92.5

95.0

75.00 25

VOUT = 3.3V

VOUT = 1.8VVOUT = 2.5V

AIRFLOW = 300 LFM

SINGLE-PHASE EFFICIENCYvs. LOAD CURRENT (VIN = 5V)

MAX

8686

toc0

2

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

20155 10

77.5

80.0

82.5

85.0

90.0

87.5

92.5

95.0

75.00 25

VOUT = 1.2V

VOUT = 1.8V

VOUT = 2.5V

CIRCUIT OF FIGURE 3AIRFLOW = 300 LFM

EFFICIENCY vs. LOAD CURRENT

MAX

8686

toc0

3

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

17148 11

80

81

82

83

85

84

86

87

795 20

270kHz

379kHz

467kHz

564kHz

AIRFLOW = 300 LFM

SWITCHING FREQUENCYvs. CFREQ CAPACITANCE

MAX

8686

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4

CFREQ CAPACITANCE (pF)

SWIT

CHIN

G FR

EQUE

NCY

(kHz

)

650600500 550200 250 300 350 400 450150

300

400

500

600

700

800

900

1000

1100

1200

1300

200100 700

CLOSED-LOOP FREQUENCY RESPONSE(IOUT = 160A, 8 PHASES)

FREQUENCY (kHz)

GAIN

(dB)

10 100

-40

-30

-20

-10

0

10

20

30

40

50

-50

PHAS

E (D

EGRE

ES)

-144

-108

-72

-36

0

36

72

108

144

180

-1801 1k

MAX8686 toc05

PHASE

GAIN

OUTPUT VOLTAGE vs. OUTPUT CURRENT

MAX

8686

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6

OUTPUT CURRENT (A)

OUTP

UT V

OLTA

GE (V

)

20155 10

1.2005

1.2010

1.2015

1.2020

1.2030

1.2025

1.2035

1.2040

1.20000 25

AIRFLOW = 300 LFM

OUTPUT VOLTAGE vs. INPUT VOLTAGE

MAX

8686

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7

INPUT VOLTAGE (V)

OUTP

UT V

OLTA

GE (V

)

19181716151413121110987

1.20

1.25

1.30

1.156 20

IOUT = 10A

OUTPUT LOAD TRANSIENTMAX8686 toc08

100μs/div

VOUT200mV/div

AC-COUPLED

IOUT42A/div


SOFT-START WITH EN CONTROL(IOUT = 10A)

MAX8686 toc09

1ms/div

EN2V/div

SS2V/div

POK5V/div

VOUT500mV/div

CIRCUIT OF FIGURE 4

Typical Operating Characteristics(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)

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6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)

SOFT-START WITH EN CONTROL(IOUT = 10A)

MAX8686 toc10

1ms/div

EN2V/div

SS2V/div

POK5V/div

VOUT500mV/div

CIRCUIT OF FIGURE 4

SHUTDOWN WITH EN CONTROL(IOUT = 10A)

MAX8686 toc11

200μs/div

EN2V/div

SS5V/div

POK5V/div

VOUT500mV/div

CIRCUIT OF FIGURE 4

SHUTDOWN WITH EN CONTROL(IOUT = 100A)

MAX8686 toc12

200μs/div

EN2V/div

SS5V/div

POK5V/div

VOUT500mV/div

CIRCUIT OF FIGURE 4

SHORT-CIRCUIT PROTECTIONMAX8686 toc13a

400μs/div

IOUT42A/div

SS500mV/div

POK5V/div

VOUT500mV/div

SHORT-CIRCUIT RECOVERYMAX8686 toc13b

400μs/div

IOUT42A/div

SS500mV/div

POK5V/div

VOUT500mV/div

CURRENT-SHARING ACCURACY

MAX

8686

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4

LOAD CURRENT (A)

PHAS

E CU

RREN

T (A

)

13012010011030 40 50 60 70 80 9010 20

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

22.5

25.0

00 140


LX_ SWITCHING WAVEFORM FORPHASES 1, 2, 3, AND 4

MAX8686 toc15

200ns/div

LX15V/div

LX25V/div

LX35V/div

LX45V/div

CIRCUIT OF FIGURE 4

PHASE SHEDDING FROM 6 PHASESTO 2 PHASES (IOUT = 30A)

MAX8686 toc18

1μs/div

PS2V/div

LX110V/div

LX510V/div

LX210V/div

CIRCUIT OF FIGURE 4

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PHASE RECOVERY FROM 2 PHASESTO 6 PHASES (IOUT = 30A)

MAX8686 toc19

1μs/div

PS2V/div

LX110V/div

LX510V/div

LX210V/div

CIRCUIT OF FIGURE 4

SAFE OPERATING AREA

MAX

8686

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0

AMBIENT TEMPERATURE (°C)

I OUT

(A)

807565 7035 40 45 50 55 6030

11

13

15

17

19

21

23

25

925 85

400 LFM

300 LFM

200 LFM

100 LFM

0 LFM

TJ = +125°C, VOUT = 1.2V

SAFE OPERATING AREA

MAX

8686

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1

AMBIENT TEMPERATURE (°C)

I OUT

(A)

807565 7035 40 45 50 55 6030

11

13

15

17

19

21

23

25

925 85

400 LFM

300 LFM

200 LFM

100 LFM

0 LFM

TJ = +125°C, VOUT = 3.3V

LX_ SWITCHING WAVEFORM FORPHASES 4, 5, 6, AND 1

MAX8686 toc16

200ns/div

LX45V/div

LX55V/div

LX65V/div

LX15V/div

CIRCUIT OF FIGURE 4

REFO OUTPUT vs. TEMPERATURE

MAX

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7

TEMPERATURE (°C)RE

FO O

UTPU

T (V

)80706050403020100-10-20-30

3.28

3.29

3.30

3.31

3.32

3.33

3.27-40 90

Typical Operating Characteristics (continued)(VIN = 12V, fSW = 500kHz, single phase, circuit of Figure 2, unless otherwise noted.)

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8 _______________________________________________________________________________________

Pin DescriptionPIN NAME FUNCTION

1 CS-Negative Differential Current-Sense Input. Connect CS- to the output side of the inductor for losslesscurrent sense or to the load side of the current-sense resistor.

2 CS+Positive Differential Current-Sense Input. Connect CS+ to the inductor through an RC network forlossless current sense or to the inductor side of the current-sense resistor.

3 GFREQCFREQ Capacitor Return Terminal. Connect the frequency-setting capacitor CFREQ to GFREQ as closeas possible to the device.

4 EN/SLOPE

Enable and Slope Compensation Input. Connect a resistor from EN/SLOPE to GND to set the desiredslope compensation ramp voltage. An internal 10μA current source pulls up EN/SLOPE. The deviceshuts down when the voltage at EN/SLOPE is less than 0.7V. Connect EN/SLOPE to an open-drain oropen-collector output for system enable or phase-shedding function.

5, 16 LX Inductor Connection. LX is high impedance during shutdown.

6 RTNPower Ground for Low-Side Gate Driver. Connect RTN to PGND plane at the return terminal of the INbypass capacitor.

7–15 PGND Power Ground. Low-side MOSFET source connection.

17 N.C. No Connection. Not internally connected.

18–26 INPower Input. Connect IN to the input voltage source. Connect input bypass capacitor from IN to PGNDas close as possible to the device. Connect IN, INA, and VL together for 5V operation (see Figure 3).

27 INA Input of the Internal VL Linear Regulator. Bypass INA with a 0.1μF capacitor to PGND.

28 GND Analog Ground

29 AVL Input Voltage to the Device’s Internal Analog Circuitry. Connect AVL to VL through a lowpass RC filter.

30 VLInternal 5.4V Linear Regulator Output. Connect a ceramic capacitor of at least 1μF from VL to RTN. INAis the input to this linear regulator. Connect VL to INA when VINA is less than 5.5V. VL provides powerfor the MOSFET drivers.

31 BST Boost Capacitor Connection. Connect a 0.22μF ceramic capacitor from BST to LX.

32 POKPower-Good Output. POK is an open-drain output that is high impedance when the output voltage is atits nominal regulated voltage. The POK rising threshold is 90% of the reference voltage at REFIN. POKis internally pulled low during shutdown. Connect POK to GND for slave mode operation.

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_______________________________________________________________________________________ 9

Pin Description (continued)

PIN NAME FUNCTION

33 FREQFrequency-Setting Input. Connect a capacitor from FREQ to GFREQ to set the switching frequency.The triangle ramp runs between 0 and AVL/2. In multiphase applications, connect FREQ of the masterand all slave devices together. FREQ is internally pulled to GFREQ during shutdown.

34 SSSoft-Start Input. For master-mode or single-phase operation, connect a capacitor from SS to GND toset the soft-start time. A 25μA internal current source charges the capacitor. SS is pulled to GND inshutdown. Connect SS to GND for slave mode operation.

35 ILIMAnalog Programmable Current Limit. Connect a resistor from ILIM to GND to set the current limit. A10μA current source through this resistor sets the current-limit threshold. In multiphase applications,connect ILIM of the master and all slave devices together.

36 REFIN

Voltage Error-Amplifier Reference Input. For master-mode or single-phase operation, connect REFIN toPHASE/REFO through a resistor-divider to set the output voltage from 0 to 3.3V. To use an externalreference, connect REFIN to the system reference voltage, and use an RC network at REFIN toimplement soft-start if the external reference does not provide this function. Connect REFIN to GND forslave mode operation.

37 P H AS E /RE FO

Phase Selection Input/Reference Voltage Output. For single-phase or master-mode operation, the 3.3Voutput with 1% accuracy can be used as a reference voltage. For multiphase operation, connectPHASE/REFO of each slave device to the center tap of a resistor-divider from the master AVL to GND.The resistor values are selected to set phase delay between phases. The PWM cycle starts 60ns afterthe rising edge of VFREQ crosses VPHASE.

38 COMPCompensation and Output of the Voltage-Error Amplifier. Connect a Type II compensation network atCOMP. COMP is internally pulled to GND in shutdown. In multiphase applications, connect COMP ofthe master and all slave devices together.

39 RS+Positive Input of the Output-Voltage Remote Sense. For master-mode or single-phase operation,connect RS+ to the output-voltage sense point at the load. Connect RS+ to AVL (slave) for slave modeoperation.

40 RS-Negative Input of the Output-Voltage Remote Sense. For master-mode or single-phase operation,connect RS- to the remote ground at the load. Connect RS- to AVL (slave) for slave mode operation.

— GND_EP Ground Exposed Paddle. Connect GND_EP to GND.

— IN_EP Input Exposed Paddle. Connect IN_EP to IN.

— LX_EP LX Exposed Paddle. Connect LX_EP to LX.

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10 ______________________________________________________________________________________

VL

500μA

S2

TO S4

PGND

RTN

10μA

LX

IN

LEVELSHIFT

BSTINA

UVLO

THERMALSHDN

RAMPGENERATOR

5.4V LDOGENERATOR

PWMCONTROL

LOGIC

CURRENT-LIMITCONTROL LOGIC

VOLTAGEREFERENCE

SLAVE MODEDETECTION

SLAVE MODE = S1, S2, S3, S5, S6 OPENMASTER MODE = S1, S2, S5, S6 CLOSE

10μA

AVL

FREQ

UV

OV

PHASE/REFO

VREF

SOFT-STARTCIRCUITRY

EN/SLOPE

EN/SLOPE

VL

AVL

SS

S6

CLOCKGENERATOR

0.9

1.2

REFIN FB

POK

EN/SLOPE

gM

ERRORAMPLIFIER PWM

COMPARATOR

PEAK CURRENT-LIMIT COMPARATOR

S1

S3

S4

AVL

AVLS5

VSUM

REFIN

RS+

RS-

FB

COMP

CS+

CS-

SLOPECOMP

1/2

CURRENT-SENSE

AMPLIFIER30.5

30.5

ILIM

GNDMAX8686

GFREQ

Functional Diagram

Detailed DescriptionDC-DC Converter Control Architecture

The MAX8686 step-down regulator uses a PWM, cur-rent-mode control scheme. An internal transconduc-tance amplifier establishes an integrated error voltage.The heart of the PWM controller is a PWM comparatorthat compares the integrated voltage-feedback signalagainst the amplified current-sense signal plus anadjustable slope-compensation ramp, which issummed with the current signal to ensure stability. Ateach rising edge of the internal clock, the internal high-side MOSFET turns on until the PWM comparator tripsor the maximum duty cycle is reached. During this on-time, current ramps up through the inductor, storingenergy in the inductor while sourcing current to theoutput. The current-mode feedback system regulates thepeak inductor current as a function of the output-voltageerror signal. The circuit acts as a switch-mode transcon-ductance amplifier and pushes an output LC filter polenormally found in a voltage-mode PWM to a higher fre-quency. See the Functional Diagram.

During the second half of the cycle, the internal high-sideMOSFET turns off and the internal low-side MOSFETturns on. The inductor releases the stored energy as thecurrent ramps down, providing current to the load. Theoutput capacitor stores charge when the inductor cur-rent exceeds the required load current and dischargeswhen the inductor current is lower, smoothing the volt-age across the load. Under soft-overload conditions,when the peak inductor current exceeds the selectedcurrent limit (see the Current-Limit Circuit section), thehigh-side MOSFET is turned off immediately and thelow-side MOSFET is turned on and remains on to let theinductor current ramp down until the next clock cycle.Under severe-overload or short-circuit conditions, thefoldback/hiccup current limit is enabled to reducepower dissipation.

The MAX8686 operates in a forced-PWM mode. Theconverter maintains a constant switching frequency,regardless of load, to allow for easier filtering of theswitching noise.

Internal Linear Regulator (VL)The MAX8686 contains an internal LDO regulator thatprovides a 5.4V supply for the MOSFET gate drivers.Connect at least a 1μF ceramic capacitor from VL to

RTN. VL also provides power to the internal analog cir-cuit through AVL. Connect an RC lowpass filter (R =10Ω, C = 0.22μF) from VL to AVL.

Undervoltage LockoutWhen AVL drops below 4.03V, the MAX8686 assumesthat the supply voltage is too low to make valid deci-sions, so the undervoltage-lockout (UVLO) circuitryinhibits switching and turns off both power MOSFETs.When AVL rises above 4.35V, the regulator enters thestartup sequence and then resumes normal operation.

When operating in a multiphase configuration, the AVLof all the devices must exceed the UVLO thresholdbefore any switching begins. This is achieved throughthe shared ILIM pin, which is pulled low in UVLO.

Startup, Soft-Start, and Prebias OperationThe internal soft-start circuitry gradually ramps up thereference voltage in order to control the rate of rise ofthe output voltage and reduce input surge currents dur-ing startup. The soft-start time is determined by thevalue of the capacitor from SS to GND and is approxi-mately equal to 50ms per microfarad of the capacitor.

In addition, the MAX8686 features monotonic output-voltage rise (prebias); therefore, both power MOSFETsare kept off if the voltage between the remote senseinput (RS+, RS-) is higher than the voltage at REFIN.This allows the MAX8686 to start up into a prebiasedoutput without pulling the output voltage down.

Before the MAX8686 can begin the soft-start andpower-up sequence, the following conditions must bemet: AVL exceeds the 4.35V UVLO threshold, EN is atlogic-high, and the thermal limit is not exceeded.

Reference Output(PHASE/REFO)/Reference Input (REFIN)

The reference voltage REFO can be used to set the out-put voltage by scaling this voltage down with a resistivedivider and using it as the input voltage to the referenceinput, REFIN. The 3.3V reference voltage is 1% accurateover temperature and can source up to 20μA.

The reference input REFIN allows the reference value ofthe device to be set by an external reference. In mostapplications, the 3.3V voltage with 1% accuracy fromthe PHASE/REFO pin should be used as the reference.This can be achieved by dividing the 3.3V voltage tothe desired output voltage.

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______________________________________________________________________________________ 11

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The external reference should be able to sink at least31μA. Calculate RREFIN as follows:

where VEXT is the external reference voltage.

In a multiphase converter, only REFIN of the masterdevice is connected to a reference voltage, and theREFIN of all slave devices should be tied to GND.

The REFIN also allows for coincident voltage tracking ofmultiple converters during power-up/power-down byapplying the same voltage on REFIN of the masterdevice in each converter.

Enable, Phase Shedding, andSlope Compensation Input (EN/SLOPE)

An internal 10μA current source pulls the EN/SLOPEinput high. The device shuts down when the voltage atthe EN/SLOPE falls below 0.7V. By connecting anopen-drain or open-collector switch to the EN/SLOPE,this pin can be used to enable/disable a single-phaseor multiphase converter system.

A separate system signal can be used to shed somephases of the converter at light load to eliminate all thepower loss from these phases and thus improve the sys-tem efficiency. The phase shedding signal is connectedto the EN/SLOPE pins of the slave devices to be shed.

The right timing of the phase shedding signal from thesystem is critical for the safe operation of the multiphaseconverter. Only after the load current drops below a cer-tain level, should the phase shedding signal becomehigh. When the open-drain or open-collector switch islogic-low, it shuts down the slave phases connected tothe switch to reduce power loss. Before the load currentincreases to a certain level, the phase shedding signalshould become logic-high to release the EN/SLOPE ofthese slave devices, thus turning these phases back onagain to prepare for the higher load current. A minimumload of 2A per phase in the remaining phases isrequired for the shedded phase(s) to turn on.

The transfer function of the power stage is different with adifferent number of phases. As the number of phasesincreases, the power stage gain increases. The compen-sation network should be designed such that the convert-er is always stable with the maximum number of phases.

The EN/SLOPE input is also used to set the slope com-pensation ramp voltage by connecting a resistor from thisinput to GND. The slope compensation is used to stabi-lize the converters when the duty cycle is more than 40%.

High-Side Gate-Drive Supply (BST)A flying capacitor between BST and LX generates thegate-drive voltage for the internal high-side n-channelMOSFET. When the low-side MOSFET is turned on, thecapacitor is charged by VL to 5.4V minus the dropacross the internal boost switch. When the low-sideMOSFET is turned off, the stored voltage of the capaci-tor is stacked above LX to provide the necessary turn-on voltage (VGS) for the high-side MOSFET. An internalswitch between BST and the internal high-side MOSFET’sgate closes to turn the MOSFET on.

Current-Sense AmplifierThe current-sense circuit amplifies the differential current-sense voltage (VCS+ - VCS-). This amplified current-sensesignal and the internal-slope-compensation signal aresummed (VSUM) together and fed into the PWM com-parator’s inverting input. The high-side MOSFET is turnedon by the clock in the device and is shut off when VSUMexceeds the error-amplifier output voltage (VCOMP) atthe noninverting input of the PWM comparator. The dif-ferential current sense is also used to provide peakinductor current limiting. The limit can be set by adjust-ing the analog current-limit input (ILIM).

The current-sense amplifier is used to measure the cur-rent across the inductor by connecting to the inductorthrough an RC network for lossless current sensing orconnecting to a current-sense resistor for higher accu-racy. The input common-mode voltage range of thecurrent-sense amplifier is from 0 to 5.5V.

RV

μAREFIN

EXT.=

−1 2519


12 ______________________________________________________________________________________

MAX8686

REFIN

RREFIN

VEXT

SS

Figure 1a. Using an External Reference

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______________________________________________________________________________________ 13

Current-Limit CircuitThe current-limit threshold is set by a resistor betweenILIM and GND. Under soft-overload conditions, whenthe peak inductor current exceeds the selected currentlimit, the high-side MOSFET is turned off immediatelyand the low-side MOSFET is turned on and remains onto let the inductor current ramp down until the nextclock cycle. The converter does not stop switching andthe output voltage regulation is not guaranteed. Undersevere-overload or short-circuit conditions, the foldbackand hiccup current limit is simultaneously activated toreduce power dissipation in the inductor, internal powerMOSFETs, and the upstream power source. Thus, thecircuit can withstand short-circuit conditions continu-ously without causing overheating of any component. Ifthe device experiences a persistent overload condition,the device will autoretry with a soft-start. The converterwill resume normal operation after the overload condi-tion is removed.

The current-limit input is also used to communicate faultsbetween the devices in a multiphase configuration. Withany fault on the slave or master device (such as UVLO orovertemperature), the ILIM input is pulled low, whichcauses the other devices to turn off both MOSFETs.

Current SharingAccurate current sharing is required in a multiphase con-verter to prevent some phases from overheating duringsoft-start, steady-state, and load transient. For a convert-er with current-mode control, the current is proportionalto the error-amplifier output in the voltage feedback loop.The error-amplifier output (COMP) of the master is con-nected to the current comparator input of all slavedevices. The current-sharing accuracy is determined bythe tolerances of the inductance and inductor DCR, theinput offset voltage, the gain of the current-sense ampli-fiers, and the slope compensation circuits.

The peak current-mode control is an open-loop current-sharing scheme, and therefore no compensation forcurrent sharing is needed and no stability issue exists.

Switching Frequency andRamp Generation (FREQ)

The MAX8686 has an adjustable internal oscillator thatcan be set to any frequency from 300kHz to 1MHz. To setthe switching frequency, connect a capacitor from theFREQ to GFREQ (see Setting the Switching Frequencysection).

A triangle ramp from 0 to AVL/2 is generated acrossFREQ capacitor. In a multiphase application, thecapacitor needs to be connected to the master device.

The FREQ inputs of the master and slave devices needto be connected together. FREQ is internally pulleddown to GFREQ during shutdown.

Phase Selection Input (PHASE/REFO)For single-phase or master device operation, thePHASE/REFO can be used as a reference for the con-verter output voltage (see the Reference Output(PHASE/REFO)/Reference Input (REFIN) section). Formultiphase operation, connect the PHASE/REFO ofeach slave device to the center tap of the resistor-divider from AVL of the master to GND. The resistor val-ues are selected to set delay time between phases (seethe Calculating the Phase Voltage section). The PWMclock cycle of slave devices starts 60ns after the risingedge of the voltage at FREQ crosses the voltage atPHASE/REFO. The PWM clock cycle of the masterdevice starts at the beginning of the ramp.

Remote Sense Input (RS+, RS-)For single-phase or master operation, connect RS+ tothe sense point at the load and RS- to the GND sensepoint of the load. The connections should be at the out-put regulation point to eliminate the voltage-sense errorcaused by voltage drop between the device and load.The RS+ and RS- traces should be laid out in parallel toreduce noise coupling. A common-mode filter to eachsense trace should be added if further noise reductionis needed.

For an output voltage higher than 3.3V, t iePHASE/REFO to REFIN and use a resistor-divider fromthe output regulation point to the remote sense inputs(RS+, RS-), as shown in Figure 1b.

For multiphase operation, connect RS+ and RS- to AVL(slave) to select the slave mode.

MAX8686

VOUT

LOADRS+

REFIN R1

R2

PHASE/REFO

RS-

Figure 1b. Output Voltage Above 3.3V

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14 ______________________________________________________________________________________

Overvoltage ProtectionThe MAX8686 provides output overvoltage protection(OVP). The OVP threshold is set at 20% above the setoutput voltage. When the overvoltage condition is expe-rienced, the output is latched to PGND through the low-side MOSFET. To clear the latch, the EN/SLOPE inputshould be pulled logic-low and then reinitialized. Theoutput starts up in a soft-start mode. To prevent theovervoltage protection from initializing during power-up,some consideration should be given to the soft-starttiming to reduce the inrush current. In addition, theproper compensation network would prevent overshootduring power-up.

Power-OK (POK) SignalPOK is an open-drain output that monitors the output volt-age. When the output is above 90% of its nominal regula-tion voltage, POK goes high impedance. There is a 3%hysteresis to prevent the POK output from chattering. ThePOK indicator can be used for sequencing.

Thermal-Overload ProtectionThermal-overload protection limits total power dissipa-tion in the MAX8686. When the junction temperatureexceeds +160°C, an internal thermal sensor shutsdown the device, allowing it to cool down. The thermalsensor turns the device on again after the junction tem-perature cools by 30°C, resulting in a pulsed outputduring continuous thermal-overload conditions. SeeFigures 2, 3, and 4.

BST31

32

33

34

3536

37

38

39

40

+

LX

GFREQ

POWER-OK C1

330pF

C171μF

C180.22μF

C160.22μF

C150.1μF

C310nF

C42.2nF

C4150pF

R55.6kΩ

R110kΩ

R16162kΩ

R3200kΩ

R4115kΩ

R2150kΩ

C1310μF

C1210μF

C6220μF

C7220μF

C141μF

C1110μF

INPUT6V TO 20V

30 29 28 27 26 25 24 23 22 21

POK

SS

ILIM

COMP

RS+

RS-

LXGFREQ

REFIN

PHASE/REFO

FREQ IN

N.C.

LX

PGND

U1

PGND

PGND

PGND

PGND

IN

IN

LX RTN

PGND

PGND

PGND

EN/S

LOPE

GFRE

Q

CS+

CS-

AVL

GND

INA IN IN IN IN IN INVL

PGND

5 6 7 9 104321 8

15

16

17

19

20

14

13

12

11

18

R11270Ω

R1310Ω

ENABLE(EN)

OUTPUT1.2V/25A

L110.56μH

C215pF

R1210Ω

MAX8686

R14270Ω

Figure 2. Single-Phase Application Circuit Operating at VIN = 12V

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______________________________________________________________________________________ 15

BST31

32

33

34

3536

37

38

39

40

LX

GFREQ

POWER-OK C1

330pF

C171μF

C180.22μF

C160.22μF

C150.1μF

C310nF

C52.2nF

C4150pF

R55.6kΩ

R16162kΩ

R3200kΩ

R4115kΩ

R2130kΩ

C1310μF

C1210μF

C6220μF

C7220μF

C141μF

C1110μF

INPUT4.5V TO 5.5V

30 29 28 27 26 25 24 23 22 21

POK

SS

ILIM

COMP

RS+

RS-

LXGFREQ

REFIN

PHASE/REFO

FREQ IN

N.C.

LX

PGND

U1

PGND

PGND

PGND

PGND

IN

IN

LX RTN

PGND

PGND

PGND

EN/S

LOPE

GFRE

Q

CS+

CS-

AVL

GND

INA IN IN IN IN IN INVL

PGND

5 6 7 9 104321 8

15

16

17

19

20

14

13

12

11

18

R11270Ω

R1310Ω

R110kΩ

ENABLE(EN)

OUTPUT1.2V/25A

L110.56μH

MAX8686

R14270Ω

C215pF

+

Figure 3. Single-Phase Application Circuit Operating at VIN = 5V

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16 ______________________________________________________________________________________

BST

31 32 33 34 35 36 37 38 39 40

LX1

GFRE

Q

POW

ER OK

C127

0pF

C17

1μF

C18

0.22

μF

C16

0.22

μF

C15

0.1μ

F

C2 33nF

C4 2.2n

F

C3 150p

F R55.

6kΩ

R16

124k

Ω

R320

0kΩ

R411

5kΩ

R215

0kΩ

C12

10μ

FC1

110

μF

INPU

T: 6

V-20

V

30

29

28

27

26

25

24

23

22

21

POK

SS ILIM

COM

P

RS+

RS-

LX1

GFRE

Q

REFI

N

PHAS

E/RE

FO

FREQ

IN

N.C. LX

PGND

U1

PGND

PGND

PGND

PGNDININ

LX

RTN

PGND

PGND

PGND

EN/SLOPE

GFREQ

CS+

CS-

AVL

GND

INA

IN

IN

IN

IN

IN

IN

VL

PGND

5

6

7

9

10

4

3

2

1

8

1516171920 14 13 12 1118

R13

10Ω

R1 10kΩ

ENAB

LE(E

N)

OUTP

UT: 1

.2V/

150A

R46

124k

Ω

R12

10Ω

C42

10μ

F

C71–

C94

100μ

F x 2

4

C41

10μ

F

MAX

8686

BST

31 32 33 34 35 36 37 38 39 40

PHAS

ESH

EDDI

NG (PS)

LX4

C47

1μF C4

80.

22μ

F

C46

0.22

μF

C45

0.1μ

F

C49

10pF

R45

16.5

kΩR44

54.9

kΩ

30

29

28

27

26

25

24

23

22

21

POK

SS ILIM

COM

P

RS+

RS-

LX4

GFRE

Q

REFI

N

PHAS

E/RE

FO

FREQ

IN

N.C. LX

PGND

U4

PGND

PGND

PGND

PGNDININ

LX

RTN

PGND

PGND

PGND

EN/SLOPE

GFREQ

CS+

CS-

AVL

GND

INA

IN

IN

IN

IN

IN

IN

VL

PGND

5

6

7

9

10

4

3

2

1

8

1516171920 14 13 12 1118

R43

10Ω

AVL4

AVL1

AVL4

R42

10Ω MAX

8686

R56

124k

Ω

C52

10μ

FC5

110

μF C5

41μ

F

R51

270Ω

L51

0.56

μH

BST

31 32 33 34 35 36 37 38 39 40

LX5

C57

1μF C5

80.

22μ

F

C56

0.22

μF

C55

0.1μ

F

C59

10pF

R55

16.5

kΩR54

35.7

kΩ

30

29

28

27

26

25

24

23

22

21

POK

SS ILIM

COM

P

RS+

RS-

LX5

GFRE

Q

REFI

N

PHAS

E/RE

FO

FREQ

IN

N.C. LX

PGND

U5

PGND

PGND

PGND

PGNDININ

LX

RTN

PGND

PGND

PGND

EN/SLOPE

GFREQ

CS+

CS-

AVL

GND

INA

IN

IN

IN

IN

IN

IN

VL

PGND

5

6

7

9

10

4

3

2

1

8

1516171920 14 13 12 1118

R53

10Ω

AVL5

AVL1

AVL5

R52

10Ω MAX

8686

R66

124k

Ω

C62

10μ

FC6

110

μF

C64

1μF

R61

270Ω

L61

0.56

μH

BST

31 32 33 34 35 36 37 38 39 40

LX6

C67

1μF C6

80.

22μ

F

C66

0.22

μF

C65

0.1μ

F

C69

10pF

R65

16.5

kΩR64

24.3

kΩ

30

29

28

27

26

25

24

23

22

21

POK

SS ILIM

COM

P

RS+

RS-

LX6

GFRE

Q

REFI

N

PHAS

E/RE

FO

FREQ

IN

N.C. LX

PGND

U6

PGND

PGND

PGND

PGNDININ

LX

RTN

PGND

PGND

PGND

EN/SLOPE

GFREQ

CS+

CS-

AVL

GND

INA

IN

IN

IN

IN

IN

IN

VL

PGND

5

6

7

9

10

4

3

2

1

8

1516171920 14 13 12 1118

R63

10Ω

AVL6

AVL1

AVL6

R62

10Ω MAX

8686

R26

124k

Ω

C2 10μ

FC2

110

μF

C24

1μF

R21

270Ω

L21

0.56

μH

BST

31 32 33 34 35 36 37 38 39 40

LX2

C27

1μF C2

80.

22μ

F

C26

0.22

μF

C25

0.1μ

F

C29

10pF

R25

16.5

kΩR24

267k

Ω

30

29

28

27

26

25

24

23

22

21

POK

SS ILIM

COM

P

RS+

RS-

LX2

GFRE

Q

REFI

N

PHAS

E/RE

FO

FREQ

IN

N.C. LX

PGND

U2

PGND

PGND

PGND

PGNDININ

LX

RTN

PGND

PGND

PGND

EN/SLOPE

GFREQ

CS+

CS-

AVL

GND

INA

IN

IN

IN

IN

IN

IN

VL

PGND

5

6

7

9

10

4

3

2

1

8

1516171920 14 13 12 1118

R23

10Ω

AVL2

AVL1

AVL2

R22

10Ω MAX

8686

R36

124k

Ω

C32

10μ

FC3

110

μF

C34

1μF

R31

270Ω

L31

0.56

μH

BST

31 32 33 34 35 36 37 38 39 40

LX2

C37

1μF C3

80.

22μ

F

C36

0.22

μF

C35

0.1μ

F

C39

10pF

R35

16.5

kΩR34

97.6

kΩ

30

29

28

27

26

25

24

23

22

21

POK

SS ILIM

COM

P

RS+

RS-

LX3

GFRE

Q

REFI

N

PHAS

E/RE

FO

FREQ

IN

N.C. LX

PGND

U3

PGND

PGND

PGND

PGNDININ

LX

RTN

PGND

PGND

PGND

EN/SLOPE

GFREQ

CS+

CS-

AVL

GND

INA

IN

IN

IN

IN

IN

IN

VL

PGND

5

6

7

9

10

4

3

2

1

8

1516171920 14 13 12 1118

R33

10Ω

AVL3

AVL1

AVL3

R32

10Ω MAX

8686

R57

270Ω

C44

1μF

R48

270Ω

L41

0.56

μH

R47

270Ω

R37

270Ω

R67

270Ω

R27

270Ω

C14

1μF

R11

270Ω

L11

0.56

μH

R17

270Ω

Figure 4. Multiphase Application at VIN = 12V

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______________________________________________________________________________________ 17

Design ProceduresSetting the Output Voltage

To set the output voltage for the MAX8686, connectREFIN to the center of an external resistor-divider fromPHASE/REFO to GND (R3 and R4 of Figures 2, 3, or 4).The sum of R3 and R4 should exceed 165kΩ.

Preselect R4 and calculate R3 using the followingequation:

where VOUT is the desired output voltage and 3.3Vcomes from the reference voltage (VPHASE/REFO). Theresistor-divider should be placed as close as possible toREFIN. If an external reference is used, see theReference Output (PHASE/REFO)/Reference Input(REFIN) section for more details.

Inductor SelectionThe output inductor is selected based on the desiredamount of inductor ripple current. A larger inductancevalue minimizes output ripple current and increasesefficiency but slows down the output-inductor-currentslew rate during a load transient. LIR is the ratio of rip-ple current to the total current per phase. For the besttradeoff of efficiency and transient response, an LIR of30% to 60% is recommended (LIR = 0.3 to 0.6).Choose a higher LIR when more phases are used totake advantage of ripple-current cancellation. Theinductor value is determined from:

where fSW is the per-phase switching frequency,IOUT_MAX is the maximum-rated output current, D is theduty ratio (VOUT/VIN), N is the number of phases, andVOUT is the output voltage. The selected inductorshould have low DC resistance, and the saturation cur-rent should be greater than the peak inductor current,IPEAK. IPEAK is found from:

When the DC resistance (RDC) of the output inductor isused for current sensing, the DC resistance should beselected to ensure a sufficient current-sense signal for

robust current-mode control. The following equationcan be used as a guideline.

where RDC is the sense resistance value of the inductoror sense resistor at the highest operating temperature.

It is also important to choose lower LIR to keep the cur-rent-sense signal below 45mV, which is the maximumcurrent limit:

If this condition is not met, then the LIR must be adjust-ed or the input signal to the current-sense amplifiermust be scaled down with a resistor-divider.

Setting the Switching FrequencyTo set the switching frequency, connect a capacitorfrom FREQ to GFREQ. Calculate the capacitor valuefrom the following equation:

where fSW is the desired switching frequency in kilo-hertz and CFREQ is the total capacitance in picofarads.The operating frequency range is from 300kHz to1MHz, so the capacitance at FREQ should be between600pF and 180pF. Parasitic capacitance from devicepads and PCB layout should be deducted from theabove calculation especially at high switching frequen-cies. In the estimation of parasitic capacitance, 15pFper phase should be used. GFREQ may be connectedto GND (quiet ground).

Setting the Slope CompensationFor most applications where the duty cycle is less than40%, set EN/SLOPE = 1.25V. For applications with aduty cycle greater than 40%, set the slope compensa-tion with a resistor (RSLOPE) from EN/SLOPE to GND.

Calculate the RSLOPE using the following formula:

where RDC is the DC resistance of the inductor,VIN_MIN is the minimum operating input voltage, andfSW is the switching frequency.

Rx R

fx VSLOPE

DC

SW x LOUT

..= −

1 22 100 1

7882 _x VIN MIN( )

Cx f

x fFREQx SW

SW.=

−5 102 7

5 30

I

NLIR

x R mVOUT MAXDC

_ 12

45+⎡

⎣⎢⎤

⎦⎥≤

I

NLIR R mVOUT MAX

DC_ × × ≥10

II

NLIR

PEAKOUT MAX= × +

⎛⎝⎜

⎞⎠⎟

_ 12

LV D N

LIR f IOUT

SW OUT MAX≥

× − ×

× ×

( )

_

1

R RVOUT

3 43 3

1= × −⎛

⎝⎜⎞

⎠⎟.

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6 Setting the Peak Current LimitThe peak current-limit threshold (VCS+ - VCS-) is set bya resistor connected from ILIM to GND. An internal10µA current source flows through this resistor to set avoltage that is 61 times higher than the current-limitthreshold. For example, a 300kΩ resistor sets the cur-rent-limit threshold at (10µA x 300kΩ)/61 or 49mV:

where RILIM is in kilohms, VTH is in millivolts, and corre-sponds to the peak voltage across the sensing element(inductor resistance or current-sense resistor).

This allows a maximum average DC output current of(ILIM):

where RDC is the DC resistance of the inductor or senseresistor and IP-P is the peak-to-peak inductor current.

To ensure maximum output current, use the minimumvalue of VTH from each setting and the maximum RDCvalues at the highest expected operating temperature.The DC resistance of the inductor’s copper wire has a+0.38%/°C temperature coefficient.

When using a sense resistor, the current through thesense resistor sets a voltage compared with the peakcurrent limit.

To provide a more efficient and lower cost design, thecurrent can be measured through the inductor using aDCR method (voltage across the DC resistance of theinductor) as shown in Figure 5.

An RC circuit is connected across the inductor. The RCtime constant is set to be 1.1 to 1.2 times the inductortime constant (L/RDC). Pick the value of C1 in the 1µF to4.7µF range, and then calculate R1 from:

R2 is added in some applications to scale down thecurrent signal. R2 and LIR should be selected to meetthe following condition.

Calculating the Phase VoltageIn the multiphase converter, the phases are interleavedto reduce the output voltage ripple. The master startsconduction at the beginning of the FREQ ramp. Thephase delay time, tPHASE, is the conduction delay timeof slaves from the master. Determine the phase delaytime as follows:

where X is the number of the slave (X = 1 to 5 for 6phase converters) fSW is the switching frequency perphase in kilohertz, and N is the total number of phases.Calculate the phase voltage of each slave from:

where CFREQ is the total capacitance (in picofarads) atFREQ (see the Setting the Switching Frequency sec-tion). For better jitter immunity, VPHASE should be limit-ed between 0.3V and 2.5V.

Then determine resistor-divider for each slave.Preselect more than 10kΩ for phase resistor RX5 (X = 2to 6, R25, R35, R45, R55, and R65) in Figure 4, and cal-culate RX4 (R24, R34, R44, R54, and R64) as follows:

Input CapacitorThe input capacitor reduces the peak current drawnfrom the power source and reduces the noise and volt-age ripple on the input DC voltage bus caused by thecircuit’s switching. The input capacitors must meet the

RX RXV VV

PHASE X

PHASE X4 5

5 4= ×

−. ( )

( )

Vt x x

CPHASEXPHASEX

FREQ=

−5 10 308

tX

f x x NPHASEXSW

=103

IN

xLIR

x R xR

R ROUT MAX

DC_ 1

22

1+

⎛

⎝⎜

⎞

⎠⎟

+ 2245≤ mV

Rx L

R x CDC1

1 2 11

.=

IVR

ILIM

TH

DC

P P= − −2

V V Vx R

TH CS CSILIM= − =+ −

1061


18 ______________________________________________________________________________________

MAX8686

VOUT

L1

C1R1

R2

LX

CS+

CS-

Figure 5. Current Sense Using the Inductor’s DC Resistance

ripple-current requirement (IRMS) imposed by theswitching currents as defined by the following equations:

for (N x D) ≤ 1:

for (N x D) > 1.

where N is the number of phases, D is the duty cycle,and IOUT_MAX is the maximum output current.

Use the minimum input voltage for calculating the dutycycle to obtain the worst-case input-capacitor RMS rip-ple current. Low-ESR aluminum electrolytic, polymer, orceramic capacitors should be used to avoid large volt-age transients at the input during a large step loadchange at the output. The ripple-current specificationsprovided by the manufacturer should be carefullyreviewed for temperature derating. Additional small-value, low-ESL ceramic capacitors (1μF to 10μF withproper voltage rating) can be used in parallel to reduceany high-frequency ringing.

Output CapacitorThe minimum output capacitance, COUT(MIN), isrequired to meet load-dump requirements. The worst-case load dump is a sudden transition from full loadcurrent (I2OUT_MAX) to minimum load current(I2OUT_MIN). COUT(MIN) is estimated based on energybalance from:

where I2OUT_MAX and I2OUT_MIN are the initial and finalvalues of the load current during the worst-case loaddump, VINIT2 is the voltage prior to the load dump, VFINis the steady-state voltage after the load dump, andVOV is the allowed voltage overshoot above VFIN. Theterm (VFIN + VOV) represents the maximum transientoutput voltage reached during the load dump. Theabove equation is an approximation, and the outputcapacitance value obtained serves as a good startingpoint. The final value should be obtained from actualmeasurements. For ceramic output capacitors, the out-put capacitor requirement is determined mostly by loaddump requirements due to their low ESR and ESL. SeeFigures 7 and 8.

Compensation DesignThe MAX8686 uses an internal transconductance erroramplifier whose output compensates the control loop.The external inductor, output capacitor, compensation

C

LN

I I

V VOUT MIN

OUT MAX OUT MIN

FIN OV( )

_ _≥

× −( )+(

2 2

)) −2 2VINIT

I D IN D N D

RMS OUT MAX= × ××

−×

−_( )

3 21

2

I D IN DRMS OUT MAX= × ×

×−_

11

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______________________________________________________________________________________ 19

MAX8686

RC

CC

COMP

CF

Figure 6. Compensation Components

GAIN(dB)

FREQUENCY (Hz)fpMOD

fzMOD

fC

CLOSED LOOP

ERRORAMPLIFIER

0

VOLTAGE-DIVIDER

POWERMODULATOR

Figure 7. Simplified Gain Plot for the fzMOD > fC Case

GAIN(dB)

FREQUENCY (Hz)fpMOD

fzMOD fC

0

POWERMODULATOR

CLOSED LOOP

ERRORAMPLIFIER

VOLTAGE-DIVIDER

Figure 8. Simplified Gain Plot for the fzMOD < fC Case

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The regulator uses a current-mode control scheme thatregulates the output voltage by forcing the requiredcurrent through the external inductor. The voltage dropacross the DC resistance of the inductor or the alter-nate series current-sense resistor is used to measurethe inductor current. Current-mode control eliminatesthe double pole in the feedback loop caused by theinductor and output capacitor resulting in a smallerphase shift and requiring a less elaborate error-amplifi-er compensation than voltage-mode control. A simpleseries RC and CC is all that is needed to have a stable,high-bandwidth loop in applications where ceramiccapacitors are used for output filtering. For other typesof capacitors, due to the higher capacitance and ESR,the frequency of the zero created by the capacitanceand ESR is lower than the desired closed-loop crossoverfrequency. To stabilize a nonceramic output-capacitorloop, add another compensation capacitor from COMPto GND to cancel this ESR zero. See Figure 6.

The basic regulator loop is modeled as a power modula-tor, an output feedback divider, and an error amplifier.The power modulator has DC gain set by gmc x RLOAD,with a pole and zero pair set by RLOAD, the output capac-itor (COUT), and its equivalent series resistance (ESR).Below are equations that define the power modulator:

where RLOAD = VOUT/[IOUT(MAX)/N], fSW is the switch-ing frequency, L is the output inductance, gmc =1/(AVCS x RDC), where AVCS is the gain of the current-sense amplifier (30.5 typ), RDC is the DC resistance ofthe inductor, the duty cycle D = VOUT/VIN. KS is a slope

compensation factor calculated from the followingequation:

Find the pole and zero frequencies created by thepower modulator as follows:

when COUT comprises “n” identical capacitors in paral-lel, the resulting COUT = n x COUT(EACH), and ESR =ESR(EACH)/n. Note that the capacitor zero for a parallelcombination of like capacitors is the same as for anindividual capacitor.

The transconductance error amplifier has a DC gain,GEA(DC) = gmEA x RO, where gmEA is the error-amplifi-er transconductance, which is equal to 1.7mS, and ROis the output resistance of the error amplifier, which is30MΩ. A dominant pole (fpdEA) is set by the compen-sation capacitor (CC), the amplifier output resistance(RO), and the compensation resistor (RC); a zero (fzEA)is set by the compensation resistor (RC) and the com-pensation capacitor (CC). There is an optional pole(fpEA) set by CF and RC to cancel the output capacitorESR zero if it occurs near the crossover frequency (fC).Thus:

The crossover frequency, fC, should be much higherthan the power-modulator pole fPMOD. Also, fC should

fC R R

fC R

f

pdEAC O C

zEAC C

pEA

=× × +

=× ×

=×

12

12

12

π

π

π

( )

CC RF C×

fC ESRzMOD

OUT=

× ×

12π

fN

R CN

L f CK DpMOD

LOAD OUT SW OUTS=

× ×+

× × ×× × −

2 21

π π( )) .−[ ]

⎡

⎣⎢

⎤

⎦⎥0 5

KV x Vf x L x VSOUT IN MIN

SW IN= +

−

−1

0 182.(

_

VVOUT)

G gR

RL f

K DMOD DC mc

LOAD

LOAD

SWS

( ) = ×

+×

× × −( )( ) −1 1 0..5⎡⎣ ⎤⎦⎡

⎣⎢

⎤

⎦⎥


20 ______________________________________________________________________________________

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______________________________________________________________________________________ 21

be less than or equal to 1/5 the switching frequency.Select a value for fC in the range:

The feedback voltage-divider gain (VREF/VOUT) shouldbe included for an output voltage higher than 3.3V,where VREFIN is equal to 3.3V.

At the crossover frequency, the total loop gain mustequal 1, and is expressed as:

For the case where fzMOD is greater than fC:

Then RC can be calculated as:

where gmEA = 1.7mS.

The error-amplifier compensation zero formed by RCand CC should be set at the modulator pole fPMOD.Calculate the value of CC as follows:

If fPMOD is less than 5 x fC, add a second capacitor CFfrom COMP to GND. The value of CF is:

As the load current decreases, the modulator pole alsodecreases; however, the modulator gain increasesaccordingly and the crossover frequency remains thesame.

For the case where fzMOD is less than fC:

The power modulator gain at fC is:

The error-amplifier gain at fC is:

RC is calculated as:

where gmEA = 1.7mS.

CC is calculated from:

CF is calculated from:

The current-mode control model on which the abovedesign procedure is based requires an additional high-frequency term, GS(s), to account for the effect of sam-pling the peak inductor current. The term GS(s) producesadditional phase lag at crossover and should be modeledto estimate the phase margin obtainable by the selectedcompensation components. As a final step, it is useful toplot the dB gain and phase of the following loop-gaintransfer function and check the obtained phase margin. Aphase margin of at least 45° is recommended:

where the sampling effect quality factor is:

QK DC

S=

× × − −[ ]11 0 5π ( ( ) . )

G ss

Q fs

f

S

c SW SW

( ) =

+× ×

+×( )

⎛

⎝

⎜⎜

⎞

⎠

⎟⎟

1

12

2π π

G sR g

RL f

Ks DLOOP

LOAD MC

LOAD

SW

( )

( )

=×

+×

× × −( ) −1 1 00 5

1 21 2

.

( / )( / )

⎡⎣ ⎤⎦⎡

⎣⎢

⎤

⎦⎥

×+ ×

+ ×

s fs f

zMOD

pMOD

π

π××

+ ×

+ × × + ×

( / )( / ) ( / )

1 21 2 1 2

s fs f s f

zEA

pEA pdEA

π

π π××

× ×g Ro VV

GmEA REFIN

OUTS(

CR fF

C zMOD=

× ×

12π

Cf RCpMOD C

=× ×

12π

RVV

fg G fC

OUT

FB

C

mEA MOD fc zMOD= ×

× ×( )

G g Rf

fEA fc mEA CzMOD

C( ) = × ×

G Gf

fMOD fc MOD dcpMOD

zMOD( ) ( )= ×

CR fF

C zMOD=

× ×

12π

Cf RCpMOD C

=× ×

12π

RV

g V GCOUT

mEA REFIN MOD fc=

× × ( )

G g R

G Gf

f

EA fc mEA C

MOD fc MOD dcpMOD

C

( )

( ) ( )

= ×

= ×

G GVVEA fc MOD fcREFIN

OUT( ) ( )× × = 1

f ff

pMOD CSW<< ≤5

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22 ______________________________________________________________________________________

Applications InformationPCB Layout Guidelines

Careful PCB layout is critical to achieve low switchinglosses and clean, stable operation. The switchingpower stage requires particular attention. Follow theseguidelines for good PCB layout:

1) Place IC decoupling capacitors as close to the ICpins as possible. Separate the power and analogground planes. Place the input ceramic decouplingcapacitor directly across and as close as possibleto IN and PGND. This is to help contain the highswitching current within this small loop.

2) For output current greater than 10A, a four-layerPCB is recommended. Pour an analog groundplane in the second layer underneath the IC to min-imize noise coupling.

3) Connect input and output capacitor to the PGNDplane and the VL capacitor to RTN. Connect allanalog signals to GND. The frequency-settingcapacitor should be connected to GFREQ.

4) Connect PGND, GND, and RTN at the return pathof the input bypass capacitor.

5) Signals shared by the master and slave (ILIM,COMP, and FREQ) should not run close to switch-ing signals.

6) Place the inductor current-sense resistor andcapacitor as close to the inductor as possible.Make a Kelvin connection to minimize the effect ofPCB trace resistance.

7) Connect the exposed pad sections to the corre-sponding IC pins and allow sufficient copper areato help cooling the device.

8) Place the REFIN and compensation componentsas close to the IC pins as possible.

9) Connect remote-sense input RS+ and RS- directlyto the load voltage regulation point and use Kelvinconnection for the two traces.

10) Refer to the MAX8686 Evaluation Kit for an exam-ple layout.

Package InformationFor the latest package outline information and land patterns, goto www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” inthe package code indicates RoHS status only. Package draw-ings may show a different suffix character, but the drawing per-tains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

40 TQFN T4066M+1 21-0177

40 TQFN T4066MN+1 21-0177

MAX8686

TQFN

+

TOP VIEW

35

36

34

33

12

11

13

CS+

EN/S

LOPE LX RTN

PGND

14

CS-

INA

IN INGND

AVL

VL IN IN

1 2

SS

4 5 6 7

27282930 26 24 23 22

ILIM

REFIN

IN

N.C.

LX

PGND

GFRE

Q

IN

3

25

37PHASE/REFO PGND

38

39

40

COMP

RS+

RS-

PGND

PGND

PGND

FREQ

32

15

INPOK

31

16

17

18

19

20 IN

GND_EP

IN_EP

LX_EP

PGND

PGND

PGND

IN

8 9 10

21

BST

Pin Configuration Chip InformationPROCESS: BiCMOS

http://pdfserv.maxim-ic.com/package_dwgs/21-0177.PDF

http://pdfserv.maxim-ic.com/package_dwgs/21-0177.PDF

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23

© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

REVISIONNUMBER

REVISIONDATE

DESCRIPTIONPAGES

CHANGED

0 5/08 Initial release —

1 10/10Modified TOC 5, Figure 4, Setting the Switching Frequency section, Calculatingthe Phase Voltage section, and the Compensation Design section

5, 16, 17, 18, 21

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