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F. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERS0
Slide Set
Data Converters
—————————
Circuits For Data Converters
F. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERS
F. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERS1
SummarySample-and-Hold
Diode Bridge S&H
Switched Emitter Follower
Features of S&H with BJT
CMOS Sample-and-Hold
CMOS Switch with low Voltage Supply
Folding Amplifiers
Voltage-to-Current Converter
Clock Generation
F. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
Chapter 5
CIRCUITS FOR DATA CONVERTERS
F. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERS2
SAMPLE-AND-HOLD
The S&H uses two phases, one for sampling and the other for retaining andmaking the signal available during the hold phase. If the output is availableduring the sampling period we have a track and hold (T&H).
Ain . Aout .
Cs
Vin VS&HFs
InputBuffer
OutputBuffer
F. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERS
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CIRCUITS FOR DATA CONVERTERS3
DIODE BRIDGE S&H
.Cs
I1
I2
SAMPLEHOLD
Vin VS&HD1 D2
D3 D4
A
B
QH QS
IC
t
SAMPLE
HOLD
1
F. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERS
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If you want ultra-speed use ... xxxxxxx
Diodes in the bridge
The speed of the diodesestablishes the speed of thediode-bridge S&H.The use of Sckottly diodesmakes the scheme very fastand suitable for medium-resoluton samplers running atmulti-GHz frequencies.
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CIRCUITS FOR DATA CONVERTERS5
Diode Bridge Imperfections
Aperture distortion
IC =1
Cs·dVindt
(1)
Hold Pedestal :
Track-mode Distortion
Hold feed-through
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Improved Diode Bridge
.Cs
I1
I2
SH
Vin VS&H
D1 D2
D3 D4
A
B
QH QS
Ix
Ix DB
DACs
VS&H
VinCD1 CD2CD3 CD4
B
A
RB
RA
VB
VA
(a) (b)
1
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SWITCHED EMITTER FOLLOWER
I1
D1 D2
2I1
Vin
1 .Cs
VS&H
CLK
CLK
I1
I1
D2
2I1
Vin 1 .
Cs
VS&H
CLK
CLK
Q1
(a) (b)
Fig. (a) reduces this by 0.7 V. A more convenient scheme is Fig. (b)
F. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERSF. MalobertiDATA CONVERTERS Springer2007
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CIRCUITS FOR DATA CONVERTERS
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But you have to remember the ...
Observation
The bipolar or diode basedswitch must simultaneouslyturn off all the currents flowingin the sampling capacitanceconnection. A 1 psec delaywith 1mA and 1 pF gives riseto an offset of 1mV!
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CIRCUITS FOR DATA CONVERTERS9
How to fix the problem ...
VT&H 1 .
Ibias
FSQHCs
1
Vin Rb
FH QS
QEVB
VE
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Circuit Implementation of the buffer
Ibias
Vin1 Vin2
R1 R2
Q1 Q2
Q3 Q4
R3 R4Vout1 Vout2
IbiasVin2
Q4Q3
Vout1 Vout2
Ibias
Q1 Q2
Vin1
Ibias/2 Ibias/2
(a) (b)
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Improvements
QC
Ibias
SH QHCs
1
Ibias
SH
S
H
(a) (b)
Vout+
Vout-VinVin
QS
QE
QC
QH QS
QE
QD1
QD2
D1 D2
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Complementary Bipolar S&H
VinQ1
I1
I2
Q2
VinQ1
I1
I2
Q2
Q3
Q4Vout
Vout
VinQ1
I1
I2
Q2
Q3
Q4 Vout
QS1
QS2
QH1
QH2
A
B
A
B
(a) (b) (c)
Cs
VS
VS
VH
VH
CL
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Complementary schemes are good but ...
Observe that
Complementary bipolarS&H requires a comparablefT for the npn and thepnp devices. The featureis not granted by manytechnologies.
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FEATURES OF S&Hs WITH BJT
Input range
Vin(nT )− VD < Vin(t) < Vin(nT ) + VD (2)
Linearity issues:
The VBE depends on the emitter current
VBE ' VBE0 + VT lnIEIbias
(3)
IE = Ibias + CSdVindt
. (4)
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Vout+ = Vin+ − VBE0 − VT lnIbias + CS
dVindt
Ibias(5)
Vout− = Vin− − VBE0 − VT lnIbias − CS
dVin, dt
Ibias(6)
δVout,d = VT ln
Ibias + CSdVindt
Ibias − CSdVindt
; (7)
δVout,d = VT ln
[Ibias +AωinCScos(ωint)
Ibias −AωinCScos(ωint)
]. (8)
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Example 5.1
1 2 3 4 5 6 7 8 9 1060
65
70
75
80
85
90
95
100
105
110
Ibias/IC
SFDR
[dB]
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Features of S&H s With BJT
IQ2= Ibias − CS
dVindt
; IQ4= Ibias + CS
dVindt
, (9)
v2n,in =
2
3
4kT
gm+ 4kTrbb′ (10)
v2n,eq = γ
4kT
gm=
2
3
4kT
gm+ 4kTrbb′ +
4kT
R0g2m
(11)
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V 2n,CS
=γkT
CS(12)
V 2n,CS
=kT
CS·γ + gmRS1 + gmRS
(13)
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1/gm
v2 R0R0
i2Ibias
v2
Vin
1/gm
(a) (b)
(c)
i2
1/gm
(d)
Vout
CS
RS 4kT RS
n,0n,0
n,in
n,in
v2n,eq v2
n,eq4kTgm
= g CS
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Trade-off
A resistance in serieswith a S&H slows downits speed but reduces theexcess noise caused bythe rbb′ base resistanceand the current source,bringing the noise powerclose to the fundamentalkT/C limit.
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CMOS SAMPLE-AND-HOLD
Ron =L
µCoxW (VGS − VTh)(14)
1 .
clk
clkb
clk
Vin+
clk
clk
Vin-
clk
MS MD
MS MD
CS
CS
MB
MB
Vout+
Vout-
IB
IB
(a)clk
(c)
1 .
Ron
CS
CS
on
off
VDDGND
Vin,d
clk
Vout,d
Vin Vout
(b)
Vin Vout
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Clock Feed-through
Qch = (WL)Cox(VG,on − VTh) (15)
B = Vov
√√√√µCoxW/L|α|CS
. (16)
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VG
Vin
VS Vout
CSCin
ON
VG (on)
VG (off)
OFF
Vin
VTh
dttoff
RinRin
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CS=Cin
CS>>Cin
CS<<Cin
DQSQch 3CS=Cin
CS=3Cin
B0.10.01 1 10
1
0.5
0
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Example 5.2
Vos =1
2
CGCs
Vov = 0.64mV (17)
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Clock Feed-through Compensation
Keep in Mind
The effectiveness of the clockfeed-through compensation de-pends on symmetric workingconditions and the matching ofelements. She expected maxi-mum cancellation is about 90%,the best to do is to obtain a dc(signal independent) term.
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Two-stage OTA as T&H
Vout(nT ) =[Vin(nT ) + Vos]A1A2
1 +A1A2; V1(nT ) =
Vout(nT )
A2(18)
+ -- +
+
-_
+
F1
F1
Vin,d Vout,d
VinF1d
F1F2
F2F1
F2
F1dVout
(a) (b) (c)
CS
CS
S1 S4
S2 S3
CS A
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+
-A1
Vin
FS
Vin
CcVout
(a) (b)
-
+A1 -A2
Rz Vout -A2
Rz Cs
VosVos
Vout(nT ) =[Vin(nT ) + Vos]A1A2
1 +A1A2; V1(nT ) =
Vout(nT )
A2(19)
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Use of this T&H
The use of a two stagesOTA T&H is convenientlywhen input buffering is re-quired. The second stagegain must be large enoughto ensure a constant clockfeed-through.
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Use of the Virtual Ground in CMOS S&H
+--
+
+
-
CS
CS
CH
CH
FS
FS
FS
FS
FS
FH
FH
FH
VCM,in VCM,out CL CL
VinA
VinB
VoutA
VoutB
+--
+
+
-
CS
CS
FS
FS
FS
FSFH
FH
VCM,in
CL CL
VinA
VinB
VoutA
VoutB
FSVCM,out
(a)
(b)
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Noise Analysis
+--
+
+
-
CS
(a)
v2 Ronn
v2 Ronn
+--
+
+
-
CS
v2
Ron
n,op
(b)
v2n
CL
v2out =
4kTRon1 + (ω/ωT )2
(20)
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V 2n,flip =
kT
CS+ gmRon
kT
CL+γkT
CL. (21)
+--
+
+
-
CS CH
(a)
v2 Ron
v2 Ron
vn2Ronn
n
+--
+
+
-
CS CHv2 Ron
v2
vn2Ronn
n,op
(b)
(1) (2)
(3)
(4) (5)
CL
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Heq(s) = HCS(s)−HCH(s) =1
1 + 3sRonCS; if CS = CH (22)
V 2n,chtr
=2kT
3CS+ +gmRon
kT
CL+
2γkT
CL(23)
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Intuitive Conclusions
The noise power of a sam-ple and hold is inversely pro-portional to the used capac-itances (sampling and load)through the kT/C relationship.The use of noisy op-amp cansignificantly worsen the noiseperformance.
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Example 5.3
CS
FS FS
FHVin
Vout
(a)
+-
CL
v2 Ronn,f
v2 Ronn,ivout
+
-
CLv2n,op gmvdVos
(b)
CS
vd
+
+
+
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CIRCUITS FOR DATA CONVERTERS36
vout = vn,i + vn,f + vn,CS(1 + 2sRonCS)
vd = vn,op − vout + vn,f + vn,CSsRonCS
gmvd = vout · sCL + vn,CSsCS
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CIRCUITS FOR DATA CONVERTERS37
vn,CS =vn,i(gm + sCL) + vn,fsCL − vn,opgm
gm + s{CL + CS(1 + gmRon)}+ 2s2CLCSRon
v2n,CS
= v2n,iH
2n,i(f) + v2
n,fH2n,f(f) + v2
n,opH2n,op(f). (24)
v2n,CS
= 4kTRon2πRonCS
(0.51 + 0.45) + 4kTγgm2πRonCS
0.05 = 1.14kTCS
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CIRCUITS FOR DATA CONVERTERS38
10−4 10−3 10−2 10−1 100 101 102 10310−8
10−7
10−6
10−5
10−4
10−3
10−2
10−1
100
f (2πRonC )S
|Hn(f)
|
Hn,i
Hn,f
Hn,op Hn,ref
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CIRCUITS FOR DATA CONVERTERS39
CMOS Switch with Low Voltage Supply
NMOS PMOS
gon
VTh,P VTh,N
VDD
NMOS
gon
VTh,P VTh,N
VDD
PMOS
gon
VTh,P VTh,N
VDD
NMOS
PMOS
(b) (c) (d)
VDD
GND
Vin
Vin Vin Vin
(a)
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CIRCUITS FOR DATA CONVERTERS40
Gon,n = µnCox
[W
L
]nVov,n + µpCox
[W
L
]pVov,p, (25)
Vov,n = VDD − Vin − VTh,n; Vov,p = Vin − VTh,p. (26)
µn
[W
L
]n
= µp
[W
L
]p
(27)
Gon,sw = µnCox
[W
L
]n
(VDD − VTh,n − VTh,p
). (28)
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CIRCUITS FOR DATA CONVERTERS41
+
-
CS
FF B
Vin
F
F
Vlow
Sin
Sb
VT&H
secondpush-pull stage
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CIRCUITS FOR DATA CONVERTERS42
Switch bootstrapping
VDDCB
S1
S2 S4
S3 SOFF
FOFFFOFF
FOFF
FON
FON
IN
OUT
FON
FOFFMS
Cp
GS
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CIRCUITS FOR DATA CONVERTERS43
VGS = (Vin + VDD)CB
CB + Cp(29)
VGS,MS= VDD
CBCB + Cp
− VinCp
CB + Cp(30)
Gon = µnCox
(W
L
)MS
[VDD
CBCB + Cp
− VinCp
CB + Cp− VTh,n
](31)
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CIRCUITS FOR DATA CONVERTERS44
• S1 must be able to switch on and off VDD;
• the switch S3 must sustain the boosted voltage during the on phase;
• the switch S4 must operate under the same conditions as the mainswitch;
• SOFF must be able to swing from the boosted voltage to zero.
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CIRCUITS FOR DATA CONVERTERS45
FON
VDD
CBC1 C2
S1
S2
S3
S4
SOFF
GS
FOFF
FOFF
M1
M2
M3
MSM4
Md1 Md2
Mo
Mi3Mi1
Mi2
Mpo
IN
OUT
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FOLDING AMPLIFIERS - Current Folding
VCC
Iin
Q1 Q2 Q3 Q4
D1 D2 D3 D4
IE IE IE IE=IFS/4
Vout,d
RL RL
VDD
Iin
M1
IS
Vout,d
RL RL
-+
M2
IS
-+
M3
IS
-+
M4
IS
-+
M5
IS
-+
M6
IS
-+
M7
IS
-+
M8
IS=IFS/8
-+
(a)
(b)
VB
VA
VA
+
-
+
-
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Vout,d = RLIin. (32)
Vout,d = RLIE −RL(Iin − IE) = −RLIin (33)
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FOLDING AMPLIFIERS - Voltage Folding
MP,1 MN,1
VR1
VR1Vin
IS IS
MP,1 MN,1
VR2
IS IS
MP,1 MN,1
VR3
IS IS
MP,1 MN,1 VR4
IS IS
VDD
RL RL
Vout,d+-
RD RD RD RD
2ISRL
2ISRD
VinVR1
2ISRL
VR3 VR4
VR2
(a)
(b) (c)
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VOLTAGE-TO-CURRENT CONVERTER
+_
R
Vin
VDD
+_ +_Vin+ Vin-
R
R
IBIB
Vin+ Vin-
IBIB
(a) (b) (c)
M1 M2
Iout
Iout-Iout+
Iout+ Iout-
M1
Iout± ' IB ±Vin+ − Vin+
R(34)
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Example 5.4
RT = R+Vov
2(IB + Iout)+
Vov
2(IB − Iout)
RT = R+VovIB
I2B − (Iout)2
.
∆Vin = RIout +VovIBIout
I2B − (Iout)2
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k2 = −5.95 · 10−18; k3 = −3.78 · 10−04;
k4 = −4.02 · 10−18; k5 = −1.55 · 10−06;
k6 = −7.83 · 10−20; k7 = −4.92 · 10−08.
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!1.5 !1 !0.5 0 0.5 1 1.5x 10!3
!3
!2
!1
0
1
2
3
Differential Output Current [A]
Diffe
rent
ial I
nput
Vol
tage
[V]
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M1 M2
M3 M4M5 M6
IBIB
Vin+ Vin-
VB
R
A B
M7 M8
Aloop = −gM3
R/2
1 + gM1R/2
· gM1Rout,A (35)
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CLOCK GENERATION
FF1
F2
F
11
0
0
0
1
F1
F2
F
1
10
0
100
F
F1
F2
1F1
F2
3t 3t
3t 3t
(a)
(b)
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![ABB Serial Data Converters[1]](https://img.pdfslide.net/doc/110x75/5525aded550346a26e8b4a20/abb-serial-data-converters1.jpg)
