Slow Wires, Hot Chips, and Leaky Transistors: New Challenges in the

New Millenium

Norm JouppiCompaq - WRL

Disclaimer: The views expressed herein are the views of Norm and are not statements by Compaq

Computer Corporation

Slow Wires Wires have been slow before (Cray’s

computers) It is not the end of the world

Cray-1 core < 1.5M transistors Designers need to pay attention Machine architecture is affected Opportunity for innovation:

CMP makes more sense Formerly slow inter-chip MP communication gets

faster

Hot Chips Chips have been hot before

E.g., 115W BIPS-0 It is not the end of the world Designers need to pay attention Opportunity for innovation:

Low-power computing (i.e., running off a battery) will not scale well

Now pick only 1 (instead of 2) out of 3: More function Lower power Higher clock speed

Background: Leaky MOS Transistors Two types of leakages

Subthreshold conduction Leakage between source and drain Like having a dimmer light switch Carver Mead has been exploiting for years Many possible ways to “fix”: SOI, low temp, …

Gate oxide leakage Leakage between gate and source or drain Like having a “hot” light switch handle Over last 25 years, Tox = Le / 45 Tox = 2.1nm for 0.10um process Alternative gate dielectrics?

Prognosis: Leaky Transistors Transistors have been leaky before

(BJTs) It is not the end of the world Designers need to pay attention Opportunity for innovation:

New CAD tools at the circuit level Need separate gate processing for memory

core Traditional memory may not scale as well Exacerbates the power problem

Real Problem: Design Complexity Design team size > 250 people for flagship uP Design team growing 1/feature size Designs take longer and have fewer changes Hennessy’s verification to design team ratio ROI negative:

200people x 3years x 167K$/personyear = 100M$ NRE/unit = 1K$ for 100,000 units

“Consolidation” has been and will continue In the number of architectures In the number of distinct designs

Increasing NRE - Example: Mask Cost A mask set used to cost less than $25K EUV mask sets may cost >1M$ Raises barrier to implementation in latest

tech Standard uP: flagship, DSP, embedded Standard RAM: DRAM, Non-Vol, SRAM? FPGA’s ? ASICs SOC Custom-fit ? VLSI project chips via maskless tech

Summary + Lots of opportunities for research - ROIC (human, $) for implementation

decreasing More and more things will be

technically feasible but economically unjustifiable