ISSCC 2007/1 SESSION 29 1 ANALOG AND POWER MANAGEMENT TECHNIQUES /29.6

29.6 A 3MHz Low-Voltage Buck Converter with The circuit of Figure 29.6.2 operates as follows: the drain-sourceImproved Light Load Efficiency voltage of M, is sensed while the device is conducting. As men-

tioned before, PWM11mp ensures that Vd, is sampled when ID =

Michael D. Mulligan',2, Bill Broach', Thomas H. Lee2 an assumption made in the derivation of the Vd, reference value.These samples are compared to Vd,,,f and the feedback controller

'National Semiconductor, Santa Clara, CA acts to minimize the resulting error. A lower bound is placed on2Stanford University, Stanford, CA V,or, by the voltage limiter block, setting a minimum gate swing

The synchronous buck switching converter has become ubiqui- that is equal to Assuming that the gate of M, is initiallytous in portable consumer electronics. However, one inherent dis- discharged, a fallingPWM edge causes the gate ofM2 to be pulsedadvantage of this converter topology is its reliance on large, off- low, with V, setting the length of the on-time, Tp,,,. Turning M2chip passive components. Although these components could be on pulls the gate of M1 up to a value, VswirLg

"

V,,, set by the feed-reduced in size by increasing the converter switching frequency, back controller. To turn M, off a PWM rising edge turns M3 on,such a change would lead to reduced efficiency as a result of var- pulling V,1 to ground.ious converter losses that scale proportionally with switching fre-quency. This lreduction is parcticularly severe at light loads. The GCR circCuit used to drive the NMOS power device is illus-

trated in Fig. 29.6.3. The overshoot of the underdamped networkFor most low-voltage applications the dominant frequency- comprisingLw., CD. and the parasitic series resistance modeleddependent loss at light loads is gate-drive loss. Pulse-frequency by Ra,,, is exploited to enhance charge storage over what is possi-modulation (PFM) has been proposed as a means to scale such ble with purely capacitive charge-sharing. Assume that the gateswitching losses along with conduction losses to increase light- of M1 is initially charged to Vi,, that Cs ., is initially discharged,load efficiency [1]. The disadvantage of PFM is that it can gener- and that M2 and M1 are off. While 1, is pulsed for T,o seconds, M4ate spectral power-supply artifacts that degrade signal integrity and M, conduct and transfer charge through L,,, to C,t,,.,. 1 ide-in the load IC. Consequently, PFM operation is relegated to appli- ally goes low when Vt,,, reaches its peak value in order to reusecations where only minimal IC functionality is required. In addi- the maximum amount of charge possible. d* then goes high totion to PFM, resonant gate drive techniques have been proposed turn M1 off completely. To turn M1 back on, <_ goes low and 0, is[2], but generally require components that are not easily integrat- pulsed once again, returning a portion of the stored charged toed in standard CMOS processes. the gate of M1. M2 subsequently turns on to bring the gate of M,

to V., and MC is turned on to prepare the storage network for theWe have previously described a method for scaling the gate swing following cycle. To combine GCR with GCM, M2 is simply pulsedof CMOS power devices to improve light-load efficiency [3]. for a short time, swinging the gate of M, to the desired level asTraditional PWM converters exhibit a rapid drop-off in efficiency described previously.as the load is decreased, an example of which is shown in [4]. Theproposed gate-charge modulation (GCM) technique maintains For the present design, both NMOS and PMOS drivers useLore =near-constant efficiency over a broader dynamic load range by 22nH, while C,,S,,, is 35pF and 85pF for the NMOS and PMOS net-balancing the gate drive and channel conduction losses of the

>/rn 1 1 1 1 ~~~~~works, respectively. The GCR systemn was tested using both on-power MOSFETs. The underlying idea is similar in principle toth wit-wthn scem decie in1151 'F InTh curen work chip and off-chip passive components. In order to reduce potentialthewidth-switching scheme described in 5],.In the currentwork, timing errors when generatin geatin a calibration step that seekswe develop a feedback control method for autonomous operation to maximize the return charge is included in the system opera-of GCM, as well as a gate charge recycling (GCR) technique that tion. For this design, GCR performance was limited by a larger-further improves efficiency, These techniques can be operated than-expected series parasitic resistance in the storage network.alone or in tandem.

Figure 29.6.1 shows a simplified top-level view of the buck con- Figure 29.6.6 shows key performance data for the converter whenverter. An external clock input, CLK, is fed into the pulse-width both gate charge modulation and recycling (GCMR) are enabled.

modulation1 PWM)bl7ock to control the switching frqec1while*1 Figure 29.6.4 shows a plot of measured efficiency versus load cur-modulation*iPM blc to cn rol the swthn frequencywhile rent with and without GCMR gate drive enabled. For V,>, = 1.8Vthe duty-cycle is determined by the feedback control signal, VorThe PWM block genelrates two non-overlappinLg gate drCive sig- the converter achieves a peak efficiency of 89. 1% at I',,, = 125mA.nals PWMP anad PWM, with dead-time

o

Xl

to ensure that the The efficiency remains above 80% over a 20:1 load current rangenasCW,n W , wit ded-i ecT*, toesr ta h spanning from 20mA to I = 400mA. The plot of Figure 29.6.5two power devices do not conduct simultaneously. These signals spanning rom20to i po4r00loss Thers pot of F e 296.in turn drive their respective gate drivers. The PWM block also shows the reduction in power loss versus cedwhen the GCMRgenerates a clock signal, PWM,, whose rising and falling edges drivers are enabled. At 20mAPth is reduced by 22.7%, fromare aligned with the midpoint of the PWM ON and OFF times. 11 5mW to 8.9mW At 200mA thetreduction is 8 7%. AmicrographThis signal is used to sample the drain-source voltages of the of the test die, fabricated in a 0.5Fm CMOS n-well process, ispower devices when ID = Iod, required for the GCM controller shown in Fig 29.6.7described below. Ackrnowledgenments:

The authors would like to thank National Semiconductor for funding thisFigure 29.6.2 shows a simplified schematic of the charge modu- work and for fabricating the test chip, Prof. Boris Murmann for helpfullated gate driver with feedback control for the NMOS power feedback on the manuscript, and Dr. Omer Oralkan for providing the diedevice. The driver for the PMOS device is similar. At light loads, micrograph.the RMS channel current, Ir,,,, is dominated by the ripple compo- References:nent of the inductor current, Ai, leading to an optimal gate swing [1] X. Zhou et al., "Improved Light-Load Efficiency for Synchronousthat is approximately independent of load current, and given by Rectifier Voltage Regulator Module," IEEE T Power Electronics, pp. 826-

D,,,A2 834, Sept., 2000.V .Ing,opt + Vt(1) [2] D. Maksimovif, "A MOS Gate Drive with Resonant Transitions," Proc.

swmg,opt@3kC5,,,Tj,f w thIEEE Power Electronics Specialists Conf, pp. 527-532, 1991.In s ~~~~~~[31M. Mulligan, B. Broach, T. Lee, "A Conlstant:-Frequency Method forHEere, DSW is the frzaction of switching cycle during which the Improving Light-Load Efficiency in Synchlronous Buck Converters," IEEEpower device conducts, k is a process-dependent parameter, and Power Electronics Letters, pp. 24-29, March, 2005.V1t is the device threshold voltage. As I, inLcreases, I, is increas- [41 "500-mA, 3-MH[z Synlchronlous Step-Down Conlverter in Chip Scale* {%{ 1 r vaz. 2 r71ts ~~~~~~~Packaging," Texas Instruments, Tech. Rep., TPS62300, Decembern, 2005.ingly affected by the DC component of the currgenLt. In thiLs rgegion, [5 S. Musunuri, P. C:hapman, "4Improvemnent of Light-Load Efficiencyforcing the dlrain-source voltage of the power devices to a constant Using Width-Switchinlg Scheme for CMOS Tranlsistors," IEEE Power(given in Fig. 29.6.2 as Vj f) achieves near-optimum efficiency. Electronics Letters, pp. 105-110, Sept., 2005.

5281 200 IEEE11 International Solid-State Circuits Con1ferenc 1-4244-0852-0/07/$25.0 ©2007 IEEE1

ISSCC 2007 / February 14, 2007 / 3:45 PM

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ISSCC 2007 PAPER CONTINUATIONS

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Figure 29.6.7: Die micrograph.

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