Solutions for EMC Issues in Automotive System Transmission ... · • Anticipate possible Electro Magnetic Compatibility (EMC) problems with your product designs • Make design decisions

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-ENT-F0174

Solutions for EMC Issues in Automotive System Transmission Lines

June 23, 2010

Todd HubingClemson University

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 2

► In automotive systems, the wiring harnesses play a key role in couplingelectronic noise to and from the components. Shielding and filtering of the wiringharness and connector are not generally viable options; therefore it is importantto address cable coupling issues with proper board-level design practices. Thispresentation reviews the various cable-coupling mechanisms and groundingstrategies. It also discusses the options available at the board level for ensuringthat automotive components do not put excessive amounts of noise on theharness and that noise on the harness does not affect the proper operation ofthe component circuitry.

► This session is intended to help the attendees learn to design electroniccomponents that function properly in harsh electromagnetic environments.

► Todd Hubing is the Michelin Professor of Vehicle Electronics at the ClemsonUniversity International Center for Automotive Research. He has over 25 yearsexperience designing products that meet electromagnetic compatibilityrequirements.

► This session is divided into four 40-minute presentations with 10 minutesallocated for questions and one 10-minute break each hour.

Session Introduction


►After completing this session you will be able to: • Anticipate possible Electro Magnetic Compatibility

(EMC) problems with your product designs• Make design decisions affecting the cost and

performance of your products• Specify grounding and shielding requirements for your

products

Session Objectives

Presenter

Presentation Notes

Insert Objectives notes here.


Agenda

1. When is a wiring harness a transmission line, and when is it just a bundle of wires?

2. If it’s just a bundle of wires, why do I care how it’s configured or routed?

3. When do wiring harnesses look like antennas?

4. How do I design automotive components to prevent harnesses from radiating?

5. How do I protect automotive components from noise or transients on the wiring harness?

4

14:00

15:00

16:00

17:00

18:00


When is a wiring harness a transmission line?

5



6

► Characteristic impedance: Z0, the ratio of voltage to current in a forward traveling wave.

► For a pair of wires side-by-side:

► For a pair of wires in the same bundle: Z0 is 100 to 300 ohms.

μ 10

dZ cosh ohms2aε

−=wire spacing

wire radius



7

► Steady state solution is always the wire-pair solution

► If we don’t care about how we get to the steady state, then we don’t need to worry about transmission line solutions.

► In most automotive applications, we don’t care!


Signal Termination

Eliminating ringing with a series resistor

Matched terminations


If it’s just a bundle of wires, why do I care how it’s configured or routed?

9


Common Impedance Coupling

10


Where does the return current flow?

11


Where does the return current flow?

12


Identify Current Paths

13

Current takes the path of least impedance!

> 100 kHz - This is generally the path of least inductance

< 10 kHz - This is generally the path(s) of least resistance



14



15



Where does the 10 kHz return current flow?


Conducted Coupling

17

VS1VS2

RS1 RS2

RL1RL2RRET

I

I2

1

IRET VRL2 VRL1

+ +

--

Requires 2 conductor connections between the source and victim.

The only mechanism that couples DC level shifts.

Most likely to be dominant at low frequencies, when source and victim share a current return path.

Most likely to be dominant when sources are low impedance (high current) circuits.

aka: Common Impedance Coupling

aka – “also known as”


Conducted Coupling Examples

18

Lights dim and radio dies when automobile engine is started.

Power bus voltage spikes are heard as audible “clicks” on an AM radio using the same power source.

An electrostatic discharge transient resets a microprocessor causing a system to shutdown.

A lightning-induced transient destroys the electronic components in a computer with a wired connection to the internet.


Electric Field Coupling

19

S 2 L2RL2

RL1S 2 L2

12

R || RVCrosstalk 20 log 20 logV 1R || R j Cω

= =⎛ ⎞+ ⎜ ⎟⎝ ⎠


Electric Field Coupling

20


Coupling proportional to dV/dt.

Most likely to be dominant at higher frequencies.

Most likely to be dominant when sources are high impedance (high voltage) circuits.

aka: Capacitive Coupling


Electric Field Coupling Examples

21

Coupling from circuit board heatsinks to cables or enclosures.

AM radio interference from overhead power lines.

Automotive component noise picked up by the rod antenna in CISPR 25 “radiated” emissions tests.

Microprocessor resets due to indirect electrostatic discharges.


Magnetic Field Coupling

22

S2

RL2 12 L2

RL1 L1 L2 S2 22when V 0

V M RCrosstalk =20 log 20 logV R R R j L

ωω

=

⎛ ⎞= ⎜ ⎟+ +⎝ ⎠


Magnetic Field Coupling

23


Coupling proportional to dI/dt.

Most likely to be dominant at higher frequencies.

Most likely to be dominant when sources are low impedance (high current) circuits.

aka: Inductive Coupling


Magnetic Field Coupling Examples

24

Coupling from power transformers or fluorescent lighting ballasts.

Jitter in CRT displays.

60 Hz “hum” in a handheld AM radio.

Hard-drive corruption due to motor or transformer currents.


When do wiring harnesses look like antennas?

25


Identifying Antennas

λ/2

λ/4 Quarter-Wave Monopole

Half-Wave Dipole

• Size

• Two Halves

Electrically Small Loop

What makes an efficient antenna?


Good Antenna Parts Poor Antenna Parts

<100 MHz >100 MHz <100 MHz >100 MHz

•Cables •Heatsinks

•Power planes

•Tall components

•Seams in shielding enclosures

•Microstripor striplinetraces

•Anything that is not big

•Microstripor striplinetraces

Free-space wavelength at 100 MHz is 3 meters



Common-Mode vs. Differential Mode

rzfI

1026.1E c6max

Δ×= −

rzsfI

1032.1E2

d14max

Δ×= −

⎟⎠⎞

⎜⎝⎛Δ

×= −

λs

rzfI

104 d6

zΔ

s



Voltage-Driven Mechanism

How are common-mode currents induced on cables?

~

CableEquivalent voltage

VCM

sinheat kCM DM

board

CV VC

= maxsin

0.2234 boardDM

heat k board cable

C rV EC F F

= × ×

~VDM Noise voltage

Heatsink



Signal current loop induces a voltage between two good antenna parts.

- Vcm +

At 10 MHz and higher, milliamps of current flowing in a ground plane produces millivolts of voltage across the

ground plane. A few millivolts driving a resonant antenna can result in radiated fields exceeding FCC limits.

Current-Driven Mechanism



Signals coupled to I/O lines can carry high frequency (HF) power off the board.

Direct-Coupling Mechanism



DM-to-CM conversion due to cable and load imbalance


How do I design components to prevent harnesses from radiating?

33

► Don’t rely on EMC Design Guidelines

► Be familiar with currents and current paths

► Learn to recognize good electromagnetic interference (EMI) sources

► Learn to recognize good antennas

► Be aware of fundamental EMI radiation mechanisms


Don’t Rely on EMC Design Guidelines

34

Board Level – Trace routing

► No trace unrelated to I/O should be located between an I/O connector and the device(s) sending and receiving signals using that connector.

► All power planes and traces should be routed on the same layer.► A trace with a propagation delay more than half the transition time of the signal it carries must have a matched

termination.► Capacitively-loaded nets must have a total source impedance equal to or greater than one-quarter of the line

characteristic impedance or a series resistor must be added to meet this condition.► Nets driven at faster than 1V/ns slew rate must have a discrete series resistor at the source.► Guard traces should be used to isolate high-speed nets from I/O nets.► Guard traces should be connected to the ground plane with vias located less than one-quarter wavelength apart at the

highest frequency of interest.► All power and ground traces must be at least three times the nominal signal line width. This does not include guard

traces.► If a ground or power separation is required, the gap must be at least 3 mm wide.► Additional decoupling capacitors should be placed on both sides of a power or ground plane gap.► Critical nets should be routed in a daisy chain fashion with no stubs or branches.► Critical nets should be routed at least 2X from the board edge, where X is the distance between the trace and its return

current path.► Signals with high-frequency content should not be routed beneath components used for board I/O.► Differential pairs radiate much less than single-ended signals even when the traces in the pair are separated by many

times their distance above a ground plane. However, imbalance in the pair can result in radiation comparable to an equivalent single-ended signal.

► The length of high-frequency nets should be minimized.► The number of vias in high-frequency nets should be minimized.► On a board with power and ground planes, no traces should be used to connect to power or ground. Connections should

be made using a via adjacent to the power or ground pad of the component.► Gaps or slots in the ground plane should be avoided. They should ONLY be used in situations where it is necessary to

control the flow of low-frequency (i.e. less than 100 kHz) currents.


EE371 Design Problem

35


EMC Design Guideline Collection

http://www.cvel.clemson.edu/emc/tutorials/guidelines.html



Where does the 56 MHz return current flow?

37


Control Transition Times

t

t

f

Control transition times of digital signals!

f



CMOS Driver Model CMOS Input Model



Digital Signal Currents in CMOS Circuits

t

t

f

f

Control transition times of digital signals:

Can use a series resistor or ferrite when load is capacitive.

Use appropriate logic for fast signals with matched loads.



Reducing risetime with a series resistor

Reducing risetime with a parallel capacitor

Good idea Bad idea


Noise Sources and Coupling Mechanisms

42


Clocks

Digital Data

Analog signals

Power supply switching

Arcing

Parasitic oscillations

Identify Sources

Narrow band, consistent

Not as narrow as clocks, but clock frequency is usually identifiable.

Bandwidth determined by signal source, consistent

Appears broadband, but harmonics of switching frequency can be identified, consistent

Broadband, intermittent

Narrowband, possibly intermittent


Active Devices (Power Pins)

Identify Sources

For some ICs, the high-frequency currents drawn from the power pins can be much greater than the high-frequency currents in the signals!


Noise on the low-speed I/O

For some ICs, significant high-frequency currents appear on low-speed I/O including outputs that never change state during normal operation!

Identify Sources


Circuit Board Grounding, Filtering and Shielding

46


Ground vs. Signal Return

“Whenever I see more than one ofthese symbols on the schematic, Iknow there is [EMC] work for ushere.”

T. Van Doren

AGND

DGND


The purpose of a system ground is to provide areference voltage and/or a safe path for fault currents.


Signal currents flowing on a “ground” conductor canprevent a ground conductor from serving its intendedpurpose.

Don’t confuse ground conductors with signal returnconductors. Rules for the routing of “ground” may conflictwith the rules for routing signal or power returns.



Circuit boards should have high-frequency ground!

Conductors referenced to different grounds can be good antennas.

Signals referenced to two different grounds will be noisy (i.e., include the noise voltage between the two grounds.)

Layouts with more than one ground are more difficult, require more space, and present more opportunities for critical mistakes.

Excuses for employing more than one ground are generally based on inaccurate or out-dated information.

Why?



If grounds are divided, it is generally to control the flow of low-frequency (<100 kHz) currents.

For example,

Isolating battery negative (i.e. chassis ground) from digital ground

Isolating digital ground from analog ground in audio circuits.

This can be necessary at times to prevent common impedancecoupling between circuits with low-frequency high-current signals andother sensitive electronic circuits.

HOWEVER, it is still necessary to ensure that there is only 1 high-frequency ground.



D/A

Exercise: Trace the path of the digital and analog return currents.



D/A




D/A




Design Exercise: What is wrong with this design and how would you improve it?


Lateral Isolation

55

Digital GND

Analog GND

Chassis GND

Rarely appropriate

Often the source of significant problems


Vertical Isolation

56

Digital GND

Analog GND

Chassis GND

Only one plane usually needs to be full size.

One or zero vias should connect planes with different labels.



You don’t need to gap a plane to control the flow of high frequency(> 1 MHz) currents. If you provide a low-inductance path for thesecurrents to take, they will confine themselves to this path very well.



Rules for gapping a ground plane:

1. Don’t do it!

2. If you must do it, never ever allow a trace or another plane to cross over the gap.

3. If you must do it, never ever place a gap between two connectors.

4. Remember that the conductors on either side of the gap are at different potentials.

5. See Rule #1!



Sensitive A/D Isolation

60

Digital GND

Analog GND

ONE VIA

Digital GND

If you think you need two vias, then you shouldn’t be isolating the analog and digital grounds.


Exceptions:

When there is no chassis ground

When there are no connectors with cables

Cables and enclosures are both good antenna parts. If they are not held to the same potential, they are likely to create a radiation problem.

Note: Sometimes low-frequency isolation between chassis and digital ground isnecessary control the flow of low-frequency currents. However, even in thesesituations it is usually important to provide a good high-frequency connection.

Provide a Good HF Chassis Ground at the Connector


Isolating Chassis and Digital Grounds

62


Caps with traces

Better implementation

63


Low-Pass Filters

Filtering


Filtering

Design Exercise: Which low-pass filter is most appropriate in each case?


Filtering

Parasitics


Two capacitors more than twice as good as one.

Filtering with Two Capacitors


Shielding

Electric Field

Shielding


Shielding

Magnetic Field

Shielding

(at low frequencies)


Shielding

Magnetic Field

Shielding

(at high frequencies)


Shielding

Enclosure

Shielding


DC Power Distribution and Decoupling

72


Printed Circuit Board

Power Supply

VVsupplyboard

LG

LP

The Concept of Power Bus Decoupling



Printed Circuit Board

Power Supply

VVsupplyboard

L G

LP

Vinductance

Vinductance


C b

traceL

traceL

traceLtraceL

Cd Cd

L d L d



Effective Strategies for Choosing and Locating Printed Circuit Board Decoupling Capacitors

76


Rules for PCB Decoupling?

Use small-valued capacitors for high-frequency decoupling.

Use capacitors with a low ESR!

Avoid capacitors with a low ESR!

Use the largest valued capacitors you can find in a given package size.

Locate capacitors near the power pins of active

devices.

Locate capacitors near the ground pins of active

devices.

Location of decoupling capacitors is not relevant.

Run traces from device to capacitor, then to power planes.

Never put traces on decoupling capacitors.

Use 0.01 μF for local decoupling!

Use 0.001 μF for local decoupling!

Local decoupling capacitors should have a range of values from 100 pF to 1 μF!


How much capacitance do you need?

sourceLf

ZfC

ZCf

20

max0min

max0

)2(1

21

21

π

π

π

=

=

=

)()(

)(max fIfV

fZMAXDEVICE

MAXNOISE=

Impedance approach

maxZ

0f 1f

tracefLπ2Cf121π

Cb

traceL traceL

traceLtraceL



Recognizing that CMOS loads are capacitances, we are simplyusing decoupling capacitors to charge load capacitances.

Total decoupling capacitance is set to a value that is equal to the total device capacitance times the power bus voltage divided by the maximum power bus noise.

Capacitance Ratio Approach



Let’s do it the way that worked forsomebody at sometime in the past.

“… include one 0.01 uF local decoupling capacitor for each VCC pin of every active component on the board plus 1 bulk decoupling capacitor with a value equal to 5 times the sum of the local decoupling capacitance.” .

Guidelines approach


Printed Circuit Board Decoupling Strategies


Boards with Closely Spaced Power Planes

Power Distribution Model ~ (5 - 500 MHz)

Cb

Cd

Board with power and ground planes

Cd


Boards with Closely Spaced Power Planes

C = 1 μFBULK C = 10nFD

L = 5 nHBULK L = 2nHDC = 3.4 nFB

0.1

1.

10.

100.

1 MHz 100 MHz0.1 MHz 1 GHz10 MHz

Bare Board

Board withdecoupling


For Boards with “Closely-Spaced” Planes

► The location of the decoupling capacitors is not critical.

► The value of the local decoupling capacitors is not critical, but it must be greater than the interplane capacitance.

► The inductance of the connection is the most important parameter of a local decoupling capacitor.

► None of the local decoupling capacitors are effective above a couple hundred megahertz.

► None of the local decoupling capacitors are supplying significant charge in the first few nanoseconds of a transition.



Inductance of Connections to Planes

On boards with closely spaced power and ground planes:

Generally speaking, 100 decoupling capacitors connected through 1 nH of inductance will be as effective as 500 decoupling capacitors connected through 5 nH of inductance.

5 nH 0.5 nH


Power Bus Decoupling Strategy

87

With closely spaced (<.25 mm) planes

► Size bulk decoupling to meet board requirements► Size local decoupling to meet board requirements► Mount local decoupling in most convenient locations► Don’t put traces on capacitor pads► Too much capacitance is ok► Too much inductance is not ok

References:

T. H. Hubing, J. L. Drewniak, T. P. Van Doren, and D. Hockanson, “Power Bus Decoupling on Multilayer Printed CircuitBoards,” IEEE Transactions on Electromagnetic Compatibility, vol. EMC-37, no. 2, May 1995, pp. 155-166.

T. Zeeff and T. Hubing, “Reducing power bus impedance at resonance with lossy components,” IEEE Transactions onAdvanced Packaging, vol. 25, no. 2, May 2002, pp. 307-310.

M. Xu, T. Hubing, J. Chen, T. Van Doren, J. Drewniak and R. DuBroff, “Power bus decoupling with embedded capacitance inprinted circuit board design,” IEEE Transactions on Electromagnetic Compatibility, vol. 45, no. 1, Feb. 2003, pp. 22-30.


Boards with Power Planes Spaced >0.5 mm

Cb

CdCd


Boards with Power Planes Spaced >0.5 mm

On boards with a spacing between power and ground planes of ~30 mils (0.75 mm) ormore, the inductance of the planes can no longer be neglected. In particular, the mutualinductance between the vias of the active device and the vias of the decouplingcapacitor is important. The mutual inductance will tend to cause the majority of thecurrent to be drawn from the nearest decoupling capacitor and not from the planes.

ACTIVE DEVICE

LOOP A LOOP A and LOOP B

DECOUPLINGCAPACITOR

SIGNAL PLANEPOWER PLANE

GROUND PLANESIGNAL PLANE

PORT 1 PORT 2

LTRACE

LTRACE

CBOARD

VIAL

VIAL

M


Where do I mount the capacitor?

VCC

GND Here?

Here?

POWER

GND



For Boards with “Widely-Spaced” Planes

► Local decoupling capacitors should be located as close to the active device as possible (near pin attached to most distant plane).

► The value of the local decoupling capacitors should be 10,000 pF or greater.

► The inductance of the connection is the most important parameter of a local decoupling capacitor.

► Local decoupling capacitors can be effective up to 1 GHz or higher if they are connected properly.




With Widely Spaced (>.5 mm) Planes:

► Size bulk decoupling to meet board requirements► Size local decoupling to meet device requirements► Mount local decoupling near pin connected to furthest plane► Don’t put traces on capacitor pads► Too much capacitance is ok► Too much inductance is not ok

References:

J. Chen, M. Xu, T. Hubing, J. Drewniak, T. Van Doren, and R. DuBroff, “Experimental evaluation of power bus decoupling on a 4-layerprinted circuit board,” Proc. of the 2000 IEEE International Symposium on Electromagnetic Compatibility, Washington D.C., August2000, pp. 335-338.

T. H. Hubing, T. P. Van Doren, F. Sha, J. L. Drewniak, and M. Wilhelm, “An Experimental Investigation of 4-Layer Printed Circuit BoardDecoupling,” Proceedings of the 1995 IEEE International Symposium on Electromagnetic Compatibility, Atlanta, GA, August 1995, pp.308-312.

J. Fan, J. Drewniak, J. Knighten, N. Smith, A. Orlandi, T. Van Doren, T. Hubing and R. DuBroff, “Quantifying SMT Decoupling CapacitorPlacement in DC Power-Bus Design for Multilayer PCBs,” IEEE Transactions on Electromagnetic Compatibility, vol. EMC-43, no. 4,Nov. 2001, pp. 588-599.



With No Power Plane:

► Layout low-inductance power distribution► Size bulk decoupling to meet board requirements► Size local decoupling to meet device requirements► Two caps can be much better than one► Avoid resonances by minimizing inductance

References:

T. Hubing, “Printed Circuit Board Power Bus Decoupling,” LG Journal of Production Engineering, vol. 3, no. 12, December2000, pp. 17-20. (Korean language publication) .

T. Zeeff, T. Hubing, T. Van Doren and D. Pommerenke, “Analysis of simple two-capacitor low-pass filters,” IEEETransactions on Electromagnetic Compatibility, vol. 45, no. 4, Nov. 2003, pp. 595-601.



Low-impedance Planes or Traces?

► Choice is based on bandwidth and board complexity► Planes are not always the best choice► It is possible to achieve good decoupling either way► Trace inductance may limit current to active devices

Planes Widely Spaced or Closely Spaced?

► Want local or global decoupling?► Want stripline traces?► Lower impedances are obtainable with closely spaced planes.


Embedded Capacitance

Input impedance of a populated 2” x 3” board with a plane separation of about 5 microns:


Decoupling Myth

In order to be effective, capacitors must be located within aradius of the active device equal to the distance a wave cantravel in the transition time of the circuitry.

On boards with closely spaced planes (where this rule isnormally applied) none of the capacitors on the board cantypically respond within the transition time of the circuitry nomatter where they are located.


Decoupling Myth

Smaller valued capacitors (i.e. 10 pF) respond faster than highervalued capacitors.

The ability of a capacitor to supply current quickly isdetermined by its mounted inductance. The value of thecapacitance only affects its ability to respond over longerperiods of time. For a given value of inductance, higher valuedcapacitors are more effective for decoupling.


Printed Circuit Board Layout Guidelines

Design rules won’t make you a good circuit board designer:

►Use common sense!

►Visualize signal current paths

►Locate antennas and crosstalk paths

►Be aware of potential EMI sources


Example: How would you modify this design?

Example Design


Example: A much better design

Example Design


Example: How would you modify this design?

Example Design


Design Review

104

►Keep signal loop areas small

►Don’t locate circuitry between connectors

►Control transition times in digital signals

►Never cut gaps in a solid return plane


Other design rules you may have heard of, but shouldn’t be too concerned with

►Avoid right angle corners on traces.

►20-H rule

►Multiple decoupling cap values or traces on caps

►Maximum trace lengths on striplines or microstrip traces


Design Example

106


Design Example

107


Design Example 2


Design Examples


Summary

Don’t rely on design guidelines!►Use common sense

►Visualize signal current paths

►Locate antennas and crosstalk paths

►Be aware of potential EMI sources

►Ask other engineers to review your designs


Digital GND

How do I protect components from transients on the harness?

Chassis GND

OR

Design Exercise: Where should the transient protection be grounded?


Diodes

0.5 volts to ~10 volts

Lowest Energy

High Capacitance (10’s of pF)

Usually fail short

Voltage limiting device

112


Varistors

0.5 volts to 10’s of volts

Low Energy

Higher Capacitance (10’s of pF)

Usually fail short

Voltage limiting device

113


Thyristors

0.5 volts to 10’s of volts

Medium Energy

Higher Capacitance (10’s of pF)

Fail open or short

Crowbar device

114


Gas Discharge Tubes

10’s of volts to 1000’s of volts

High Energy

Low Capacitance (< 1 pF)

Fail open

Crowbar device

115


Session Review

1. When is a wiring harness a transmission line, and when is it just a bundle of wires?

2. If it’s just a bundle of wires, why do I care how it’s configured or routed?

3. When do wiring harnesses look like antennas?

4. How do I design automotive components to prevent harnesses from radiating?

5. How do I protect automotive components from noise or transients on the wiring harness?

116


For Further InformationCited Referenfces regarding Power Bus Decoupling Strategy:

T. H. Hubing, J. L. Drewniak, T. P. Van Doren, and D. Hockanson, “Power Bus Decoupling on Multilayer Printed Circuit Boards,”IEEE Transactions on Electromagnetic Compatibility, vol. EMC-37, no. 2, May 1995, pp. 155-166.

T. Zeeff and T. Hubing, “Reducing power bus impedance at resonance with lossy components,” IEEE Transactions onAdvanced Packaging, vol. 25, no. 2, May 2002, pp. 307-310.

M. Xu, T. Hubing, J. Chen, T. Van Doren, J. Drewniak and R. DuBroff, “Power bus decoupling with embedded capacitance inprinted circuit board design,” IEEE Transactions on Electromagnetic Compatibility, vol. 45, no. 1, Feb. 2003, pp. 22-30.

J. Chen, M. Xu, T. Hubing, J. Drewniak, T. Van Doren, and R. DuBroff, “Experimental evaluation of power bus decoupling on a 4-layer printed circuit board,” Proc. of the 2000 IEEE International Symposium on Electromagnetic Compatibility, WashingtonD.C., August 2000, pp. 335-338.

T. H. Hubing, T. P. Van Doren, F. Sha, J. L. Drewniak, and M. Wilhelm, “An Experimental Investigation of 4-Layer Printed CircuitBoard Decoupling,” Proceedings of the 1995 IEEE International Symposium on Electromagnetic Compatibility, Atlanta, GA,August 1995, pp. 308-312.

J. Fan, J. Drewniak, J. Knighten, N. Smith, A. Orlandi, T. Van Doren, T. Hubing and R. DuBroff, “Quantifying SMT DecouplingCapacitor Placement in DC Power-Bus Design for Multilayer PCBs,” IEEE Transactions on Electromagnetic Compatibility, vol.EMC-43, no. 4, Nov. 2001, pp. 588-599.

T. Hubing, “Printed Circuit Board Power Bus Decoupling,” LG Journal of Production Engineering, vol. 3, no. 12, December2000, pp. 17-20. (Korean language publication) .

T. Zeeff, T. Hubing, T. Van Doren and D. Pommerenke, “Analysis of simple two-capacitor low-pass filters,” IEEE Transactionson Electromagnetic Compatibility, vol. 45, no. 4, Nov. 2003, pp. 595-601.

EMC Guideline Collection: http://www.cvel.clemson.edu/emc/tutorials/guidelines.html

117

TM

Documents

Solutions for EMC Issues in Automotive System Transmission ... · • Anticipate possible Electro Magnetic Compatibility (EMC) problems with your product designs • Make design decisions