Spartan-3 5m Protoboard

OPERATIONAL MANUAL

FOR

SPARTAN-3 FG900 PROTOBOARD MODEL : MXS3FK- 5M

Rev : 002

MECHATRONICS TEST EQUIPMENT (I)PVT.LTD. B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR,

NEAR YASHAVANTRAO CHAVAN NATYAGRUH, KOTHRUD, PUNE- 411038

PHONE : +91-20-25386926 FAX : +91-20-25386930 EMAIL : [email protected] URL : www.mte-india.com

TABLE OF CONTENTS

PREFACE .......................................................................................................................................1 About Thi s Manual.......................................................................................................................1

Manual Contents ......................................................................................................................... 1

CHAPTER 1 ....................................................................................................................................2 Introduction...................................................................................................................................2

1.1 Features ................................................................................................................................ 2

CHAPTER 2 ....................................................................................................................................5 High Speed Synchronous SDRAM..............................................................................................5

2.1 Address Bus Connection ........................................................................................................ 5 2.2 Bank Address Selection ......................................................................................................... 6 2.3 Dat a Bus Connection ............................................................................................................. 6 2.4 Dat a Mask Lines Connection .................................................................................................. 7 2.5 Control Lines Connection ....................................................................................................... 7

CHAPTER 3 ....................................................................................................................................8 USB Interface ...............................................................................................................................8

3.1 Dat a Bus Connection ............................................................................................................. 9 3.2 Control Lines: ........................................................................................................................ 9 3.3. FTDI Driver Inst allation.......................................................................................................... 9

CHAPTER 4 ..................................................................................................................................11 Serial Interface........................................................................................................................... 11

4.1 RS- 232 Int erf ace..................................................................................................................11 4.2 RS- 422 Int erf ace..................................................................................................................12

CHAPTER 5 ..................................................................................................................................13 PS/2 Mouse/Keyboard Interface................................................................................................ 13

5.1 PS/2 Keyboard .....................................................................................................................14 5.2 PS/2 Mouse..........................................................................................................................15 5.3 Control Signal Connection .....................................................................................................16

CHAPTER 6 ..................................................................................................................................17 Switches And LEDs ................................................................................................................... 17

6.1 DIP Switches ........................................................................................................................17 6.2 Key Switches ........................................................................................................................17 6.3 LEDS ...................................................................................................................................17

CHAPTER 7 ..................................................................................................................................19 Seven Segment LED Di splay .................................................................................................... 19

CHAPTER 8 ..................................................................................................................................21 VGA In terface............................................................................................................................. 21

8.1 VGA Display Theory ..............................................................................................................22 8.2 VGA signal TI MING...............................................................................................................24

CHAPTER 9 ..................................................................................................................................25 LCD Interface ............................................................................................................................. 25

9.1 Dat a Lines Connection..........................................................................................................26 9.2 Control Line Interf ace: ...........................................................................................................26

CHAPTER 10 ................................................................................................................................27 10/100 Non PCI Ethernet Interface ........................................................................................... 27

10.1 System Address Bus Connection .........................................................................................28 10.2 System Data Bus Connection ..............................................................................................28

10.3 Control Signals Connection..................................................................................................29

CHAPTER 11 ................................................................................................................................32 Connector Details....................................................................................................................... 32

11.1 I O Connectors ....................................................................................................................32 11.2 Stackable Connect or ...........................................................................................................36

CHAPTER 12 ................................................................................................................................39 Clock and Reset Sources .......................................................................................................... 39

CHAPTER 13 ................................................................................................................................40 SPARTAN-3 Configuration Details............................................................................................ 40

13.1 Boundary Scan mode: .........................................................................................................40 13.2 Master Serial Mode .............................................................................................................40 13.3 Jumper Setting....................................................................................................................40

CHAPTER 14 ................................................................................................................................43 Power Supplies.......................................................................................................................... 43

14.1 Voltage Regulators ..............................................................................................................43

APPENDIX A.................................................................................................................................44 Consolidated UCF For The Complete Board ............................................................................ 44

APPENDIX B.................................................................................................................................58 Operating Inst ruction To Start A New Design ........................................................................... 58

B.1 Starting The ISE Sof tware: ....................................................................................................58 B.2 Design Flow.........................................................................................................................58 B.3 Design Desc ription ...............................................................................................................59 B.4 Truth Table of Half adder ......................................................................................................59 B.5 VHDL Code f or Half adder ....................................................................................................59 B.6 Steps to implement the Half adder in the FPGA using Xilinx iSE(8.1i) ......................................60

APPENDIX C.................................................................................................................................74 ASCII Table 5 X 7 LCD Display ................................................................................................. 74

APPENDIX D.................................................................................................................................75 ADC–DAC Add On Card ............................................................................................................ 75

APPENDIX E.................................................................................................................................81 Video ADC – DAC Add On Card ............................................................................................... 81

F.1 Video ADC int erf ace .............................................................................................................81 F.2 VIDEO DAC .........................................................................................................................82 F.3 SYNC SEPERATOR .............................................................................................................83 F.4 Consol idated UCF f or All Mother Boards: ...............................................................................85

LIST OF TABLES

Table 1 Address Bus Interface to SPARTAN-3 FPGA ...................................................................6 Table 2: Bank Address Selection Interface to SPARTAN-3 FPGA ................................................6 Table 3 Data Bus Interface to SPARTAN-3 FPGA.........................................................................6 Table 4: Data Bus Interface to SPARTAN-3 FPGA........................................................................7 Table 5: Control Lines Interface to SPARTAN-3 FPGA.................................................................7 Table 6: Data Bus Interface to SPARTAN-3 FPGA........................................................................9 Table 7: Control Lines Interface to SPARTAN-3 FPGA.................................................................9 Table 8: RS232 Interface to SPARTAN-3 FPGA..........................................................................11 Table 9: RS422 Interface to SPARTAN-3 FPGA..........................................................................12 Table 10: PS/2 Connector Details.................................................................................................13 Table 11: PS/2 Bus Tim ing...........................................................................................................13 Table 12: Common PS/2 Keyboard Commands..........................................................................15 Table 13: LED Status....................................................................................................................15 Table 14: PS/2 Interface to SPARTAN-3 FPGA...........................................................................16 Table 15: DIP switch Interface to SPARTAN-3 FPGA .................................................................17 Table 16: KEY switch Interface to SPARTAN-3 FPGA ................................................................17 Table 17: LED Interface to SPARTAN-3 FPGA............................................................................17 Table 18: Seven Segment Di splay Interface to SPARTAN-3 FPGA............................................20 Table 19: VGA Interface to SPARTAN-3 FPGA...........................................................................22 Table 20: VGA signal timing..........................................................................................................24 Table 21: Data Line Interface to SPARTAN-3 FPGA...................................................................26 Table 22: Control Line Interface to SPARTAN-3 FPGA...............................................................26 Table 23: Address Bus Interface to SPARTAN-3 FPGA..............................................................28 Table 24: Data Bus Interface to SPARTAN-3 FPGA....................................................................28 Table 25: Synchronous Bus Interface to SPARTAN-3 FPGA ......................................................30 Table 26: Asynchronous Bus Interface to SPARTAN-3 FPGA ....................................................30 Table 27: M iscellaneous Signal s Interface to SPARTAN-3 FPGA ..............................................31 Table 28: IOCON1 Connector Interface to FPGA ........................................................................32 Table 29: IOCON2 Connector Interface to FPGA ........................................................................33 Table 30: IOCON3 Connector Interface to FPGA ........................................................................33 Table 31: IOCON4 Connector Interface to FPGA ........................................................................34 Table 32 IOCON5 Connector Interface to FPGA .........................................................................34 Table 33: IOCON6 Connector Interface to FPGA ........................................................................35 Table 34: IOCON7 Connector Interface to FPGA ........................................................................35 Table 35: IOCON8 Connector Interface to FPGA ........................................................................36 Table 36: IOCON9 Connector Interface to FPGA ........................................................................36 Table 37: Stackable Connector Interface to FPGA ......................................................................36 Table 38: IO Clock-Reset Interface to FPGA ...............................................................................39 Table 39: Mode Selection Jumper Settings..................................................................................40 Table 40: Mode Selection Table...................................................................................................40 Table 41: Power Supply Details....................................................................................................43

LIST OF FIGURES

Figure 1: Block Diagram..................................................................................................................3 Figure 2: FPGA – SDRAM Interface...............................................................................................5 Figure 3: FPGA – USB Interface.....................................................................................................8 Figure 4: FPGA – RS232 Interface ...............................................................................................11 Figure 5: FPGA – RS422 Interface ...............................................................................................12 Figure 6: PS/2 Connector..............................................................................................................13 Figure 7: PS/2 Timing Diagram.....................................................................................................14 Figure 8: PS/2 Keyboard with scan codes....................................................................................14 Figure 9: Data fo rmat for PS/2 mouse interface...........................................................................16 Figure 10: Seven Segment Di splay ..............................................................................................19 Figure 11: FPGA –VGA Interface .................................................................................................21 Figure 12: CRT Di splay Tim ing.....................................................................................................23 Figure 13: VGA Tim ing..................................................................................................................24 Figure 14: LCD Interface to SPARTAN-3 FPGA ..........................................................................25 Figure 15: LAN 91C111 Interface to SPARTAN-3 FPGA.............................................................28 Figure 16: Positional Details of On Board Connectors.................................................................38 Figure 17: JTAG Mode Selection..................................................................................................41 Figure 18: JTAG Connector Details..............................................................................................42

1

PREFACE A bout This Manual

This manual gives operational details for all the interfaces.

Manual Contents This manual contains following chapters: • Chapter 1, “Int roduction” • Chapter 2, “High Speed Synchronous SDRAM ” • Chapter 3, “USB Interface” • Chapter 4, “Serial Interface” • Chapter 5, “PS/2 Mouse/Keyboard Interface” • Chapter 6, “Switches And LEDs” • Chapter 7, “Seven Segment LED Display” • Chapter 8, “VGA Interface” • Chapter 9, “LCD Interface” • Chapter 10, “10/100 Non PCI Ethernet Interface” • Chapter 11, “Connector Detail s” • Chapter 12, “Clock And Reset Sources” • Chapter 13, “SPARTAN-3 Configuration Details” • Chapter 14, “Power Supplies” • Appendix A Consolidated UCF for the complete Board • Appendix B Operating Inst ruction to Start a New Design • Appendix C ASCII Table 5x7 LCD Di splay • Appendix D ADC DAC Add – On Card Detail s • Appendix E VIDEO ADC DAC Add – On Card Details

2

CHAPTER 1 Introduction

SPARTAN-3-FG900 Development Board (MXS3FK-5M) provides an easy to use development platform for realizing various desi gns around SPART AN-3 FPGA.

1.1 Features Figure 1 shows the SPARTAN-3 Development Board, which includes the following components and features: • Spartan-3 family is building on the successor Spartan-IIE family by increasi ng the amount of

logic resources, the capacity of internal RAM, the total no of I/O’s and overall level of perfo rmance as well as by improving clock management functions.

• Revolutionary 90 nm process technology • Very low cost, high performance logic solutions for high volume consumer–oriented

application • Densities as high as 74,880 logic cell s’ • Upto 326 MHz system clock rate • Three separate power supplies fo r the core (1.2), I/Os(1 .2 to 3.3), and special function(2.5V) • Select I/O signalling • Abundant, flexible logic cells with regi sters, wide multiplexer, dedicated 18x18 multiplier, • Up to 1872 Kbits of total block RAM • Up to 520 Kbits of total dist ributed RAM • Digital clock manager (up to four DCM) • Eight global clock lines and abundant routing. • Fully supported by Xilinx ISE development system • Unlim ited reprogram ability. • Very low cost.

• Platform Flash: 16 Mbit Xilinx XCF16P in-system configurable platform flash for configuration th rough PROM in VO 48 package. 1.8V supply voltage Serial or parallel FPGA configuration interface (up to 33 MHz) Available in small-footprint VO48, VOG48, FS48, and FSG48 packages Design revi sion technology enables storing and accessing multiple design revi sions for

configuration. Built-in data decompressor compatible with Xilinx advanced compression technology

• SDRAM : 4 Meg x 32 M icron SDRAM MT48LC4M32B2 as a high speed synchronous memory interface in TSOP-86 package PC100 functionality Fully synchronous; all signal s regi stered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks fo r hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes concurrent Auto precharge, and Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh (15.6µs/row) LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply Supports CAS latency of 1, 2, and 3

3

Figure 1: Block Diagram

• USB Controller: Cost effective, easy to use USB FIFO IC FT245BM from FTDI in LQFP-32

package to t ransfer da ta to / f rom FPGA and host PC at upto 1Mbyte per second. Single Chip USB ó Parallel FIFO bi-directional Data Transfer Transfer Data rate to 1M Byte / Sec - D2XX Drivers

4

Transfer Data rate to 300 Kilobyte / Sec - VCP Drivers Simple to interface to MCU / PLD/ FPGA logic with a 4 wire handshake interface Entire USB protocol handled on-chip, no USB-specific firmware programming required 384 Byte FIFO Tx buffe r / 128 Byte FIFO Rx Buffe r for high data throughput . Integrated 3.3V regulator fo r USB IO Integrated Power-On-Reset circuit Integrated 6MHz – 48MHz clock multiplier PLL USB Bul k or Isochronous data t ransfer modes

• Ethernet Controller: 10/100 Non PCI single chip Ethernet controller LAN 91c111 f rom SMSC in QFP package. Supports full duplex switched Ethernet. Supports burst transfer. 8 Kbytes of internal memory for receive and t ransmit FIFO buffers. Optional configuration th rough serial EEPROM Supports 8, 16, 32 bit CPU accesses. Single 25 MHz Clock fo r both PHY and MAC. Fully integrated IEEE 802.3 / 802.3 u -100 Base –TX/ 10 Base-T physical layer.

• VGA display Port: 12 bit, 512 colours VGA di splay port.

• RS232 Serial Interface: 9 pin two channel serial interfaces. DB9 9-pin female connector (DCE connector) RS-232 t ransceiver/level t ranslator using MAX3223 in SSOP package. Uses straight-th rough serial cable to connect to computer or workstation serial port.

• RS422 Serial Interface: 10 pin two channel serial interfaces. 10 pin berg connector. RS-422 dual differential drivers and receivers SN65C118 in TSSOP package

• PS/2 Interface: PS/2-style mouse/keyboard port.

• Seven Segment Display: Four-character, seven-segment LED display.

• DIP Switches: Eight DIP switches.

• LEDs: 13 onboard LEDS 8 user LEDs (RED) Single configuration status LED (GREEN) 4 Power on indicator LEDs(RED)

• Push Button Switches: Four momentary-contact push button switches.

• LCD interface: 16 character 2 row LCD .

• Mictor Connector: Facilitates provision for Logic Analyzer interface.

• Stackable Connector: Facilitates provision fo r interface of ADD ON Boards

• Free IOs: 289 f ree IOs.

• Clock Oscillator: 40 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator clock source.

• JTAG port: 10 Pin FRC male connector fo r JTAG download cable (parallel III) interface that connects to the parallel port of host PC.

• Pow er Supplies: 5 volts regulated power supply provided along with the board. On board 3.3V, 2.5V, 1.8V, 1.2V regulators. On board generation of -5V supply.

5

CHAPTER 2 High Speed Synchronous SDRA M

SPARTAN-3 Development Board has a single 4 Meg x 32 high speed synchronous SDRAM (MT48LC4M32B2), surface mounted on top side of the board. A detailed interface is as shown in Figure 2.

Figure 2: FPGA – SDRAM Interface

This SDRAM i s internally configured as quad bank DRAM with synchronous interface (all signals regi stered on positive clock edge). The SDRAM provides for p rogrammable READ or WRITE burst lengths of 1, 2, 4, o r 8 locations, or the full page, with a burst te rminate option. An auto precharge function may be enabled to provide a self-timed row precharge that i s initiated at the end of the burst sequence.

2.1 Address Bus Connection • SDRAM has a 12 bit address bus interface with FPGA. • A0–A11 are sampled during the ACTIVE command (row-address A0–A10) and

READ/WRITE command (column-address A0–A8 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 i s sampled during a PRECHARGE command to determ ine if all banks are to be precharged (A10 [HIGH]) o r bank selected by BA0, BA1 (LOW). The address inputs al so provide the op-code during a LOAD MODE REGISTER command.

6

Table 1 Address Bus Interface to SPARTAN-3 FPGA Address Bit FPGA Pin

"A0_S1" AA7

"A1_S1" Y8

"A2_S1" Y7

"A3_S1" K7

"A4_S1" L8

"A5_S1" L7

"A6_S1" M8

"A7_S1" M7

"A8_S1" N8

"A9_S1" P7

"A10_S1" AB8

"A11_S1" AC7

2.2 Bank Address Selection Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

Table 2: Bank Addr ess Selection Interface to SPARTAN-3 FPGA

Bank Address Selection Bit FPGA Pin

"BA0_S1" V8

"BA1_S1" W7

2.3 Data Bus Connection 32 bit bidirectional data bus interface.

Table 3 Data Bus Interface to SPARTAN-3 FPGA

Data Bit FPGA Pin Data Bit FPGA Pin

"D0_S1" AE5 "D16_S1" T5

"D1_S1" AD6 "D17_S1" T6

"D2_S1" AC6 "D18_S1" U6

"D3_S1" AC5 "D19_S1" V5

"D4_S1" AB6 "D20_S1" V6

"D5_S1" AB5 "D21_S1" W5

"D6_S1" AA6 "D22_S1" W6

"D7_S1" Y6 "D23_S1" Y5

"D8_S1" L6 "D24_S1" R5

7


"D9_S1" K6 "D25_S1" R6

"D10_S1" J5 "D26_S1" P6

"D11_S1" J6 "D27_S1" N5

"D12_S1" H5 "D28_S1" N6

"D13_S1" H6 "D29_S1" M5

"D14_S1" G6 "D30_S1" M6

"D15_S1" F5 "D31_S1" L5

2.4 Data M ask Lines Connection DQM is sampled high and i s an input mask signal fo r write accesses and an output enable signal fo r read accesses. Input da ta i s masked during a WRITE cycle. The output buffe rs are placed in a High-Z state (two clock latency) during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 is considered same state when referenced as DQM.

Table 4: Data Bus Interface to SPARTAN-3 FPGA


"DQM0_S1" R8 "DQM2_S1" W8

"DQM1_S1" H7 "DQM3_S1" J8

2.5 Control Lines Connection • Clock: CLK i s d riven by the system clock. All SDRAM input signals are sampled on the

positive edge of CLK. • CKE activates (HIGH) and deactivates (LOW) the CLK signal. • CS# enables (regi stered LOW) and di sables (regi stered HIGH) the command decoder. • Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command.

Table 5: Control Lines Interface to SPARTAN-3 FPGA

Control Bit FPGA Pin Control Bit FPGA Pin

"CAS#_S1" T7 "CS#_S1" U7

"CKE_S1" K9 "RAS#_S1" T8

"CLK_S1" K10 "WE#_S1" R7

8

CHAPTER 3 USB Interface

SPARTAN-3 Board has a USB interface using device FT245BM from FT DI. It offers data transfer rates up to 8 M illion bits (1 Megabyte) per second. To send data f rom the FPGA to the host computer, simply write the byte-wide data into the module when TXE# is low. If the (384-byte) t ransmit buffe r fills up or is busy storing the previousl y written byte, the device keeps TXE# high in order to stop further da ta from being written until some of the FIFO data has been t ransferred over USB to the host. TXE# goes high after every byte written. When the host sends data to the FPGA over USB, the device will take RXF# low to let the FPGA know that at least one byte of data i s available. The FPGA can read a data byte every time RXF# goes low. RXF# goes high after every byte read. FTDI chip supports two drivers: • VCP Drivers • D2xx Drivers SPARTAN-3 board uses D2xx Drivers that allow application software to access the device “directly” th rough a published DLL based API. For more details on Drivers vi sit http://www.ftdichip.com

Figure 3: FPGA – USB Interface

9

3.1 Data Bus Connection 8 bit bidirectional data bus for data transfer from / to FPGA and USB interface.

Table 6: Data Bus Interface to SPARTAN-3 FPGA Data Bit FPGA Pin

"USB_D0" T28

"USB_D1" R28

"USB_D2" R27

"USB_D3" P28

"USB_D4" N27

"USB_D5" M28

"USB_D6" M27

"USB_D7" L28

3.2 Control Lines: Control group interface consi st of following signal s: • RD #: Enables reading of data byte f rom USB controller on data line interface when low. • WR#: Writes data byte from D0-D7 into the transmit FIFO of USB. • TXE #: Data write enable. • RXF #: Data read enable.

Table 7: Control Lines Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

"TXE#" H28

"WR#" J27

"RD#" K28

"RXF#" L27

3.3. FTDI Driver Installation

• To install the FT DI drivers on your PC simply run the FTDI_Setup.exe file provided in the CD accompanied with your Development board.

• After successful installation following message will be displayed on screen

10

• After installation when USB device plugged in Device Manager will add USB Serial Converter controller into its USB Serial Bus Controller list as shown below:

• When USB device plugged in Device Manager will add USB Serial Converter

controller into its USB Serial Bus Controller list as shown below

Your system is ready to communicate through USB port.

11

CHAPTER 4 Serial Interface

The SPARTAN-3 development board supports RS-232 and RS-422 (differential) serial interface. Details of both interface is described below.

4.1 RS- 232 Interface The RS-232 transmit and receive si gnals appear on the female DB9 connector, indicated as in Figure 4. The connector i s a DCE-style port and connects to the DB9 DTE-style serial port connector available on most personal computers and workstations. Use a standard straight-through serial cable to connect the SPARTAN-3 development board to the PC’s serial port.

Figure 4: FPGA – RS232 Interface

Figure 4-1 shows the connection between the FPGA and the DB9 connector, including the Maxim MAX3223 RS-232 voltage converter. The FPGA supplies serial output data as LVTTL or LVCMOS level s to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Li kewise, the Maxim device converts the RS-232 serial input data to LVTTL levels fo r the FPGA. Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR signals are left unconnected. Similarly, the port’s CTS and Ring Indicator are used as an auxiliary RS232 channel signal s The FPGA connections to the Maxim RS-232 t ranslator appear in Table 4-1 .

Table 8: RS232 Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

"TXD1-F" AH8

"TXD2-F" AG8

"RXD1-F" AG9

"RXD2-F" AH10

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For more details on RS232 UART application please refer the following application note AN2141 f rom Maxim.

4.2 RS- 422 Interface Two – RS422 compatible transmit and receive channel s are provided on board using SN65C1168 a dual differential driver and receiver. External connectivity is p rovided using 10-pin Berg connector for transmitter as well as receiver.

Figure 5: FPGA – RS422 Interface

Figure 5 shows the connection between the FPGA and the 10 pin external connector. The FPGA supplies serial output data as LVTTL or LVCMOS level s to the SN65C118.device. SN65C118.i s a dual differential driver and receiver that converts the logic value to the appropriate RS-422 voltage level and vice versa. The FPGA connections to RS-422 dual differential transmitter/receiver appear as in Table 4-2.

Table 9: RS422 Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

"TTL_IN1_QS" G10

"TTL_IN2_QS" H9

"TTL_OUT1_QS" E6

"TTL_OUT2_QS" F6

13

CHAPTER 5 PS/2 Mouse/Keyboard Interface

SPARTAN-3 development board includes a separate PS/2 ports for mouse and keyboard interface using a standard 6 in PS/2 connector as shown in figure 6.

Figure 6: PS/2 Connector

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the SPARTAN-3 FPGA in thi s case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit words tha t include a start, stop and odd parity bit. However, the data packets are organized differently fo r a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers.

Table 10: PS/2 Connector Details PS/2 Connector Pin Signal

1 DATA(PS2D)

2 Reserved

3 GND

4 Voltage Supply

5 CLK(PS2C)

6 Reserved

The PS/2 bus timing appears Table 11 and Figure 7. The clock and data signal s are only driven when data t ransfers occur, and otherwi se they are held in the idle state at logic High. The timings define signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 7, the attached keyboard or mouse writes a bit on the data line when the clock signal i s high, and the host reads the data line when the clock signal i s low.

Table 11: PS/2 Bus Timing Symbol Parameter Min Max

TCK Clock high or low time 30µs 50µs

TSU Data to clock setup time 5µs 25µs

THLD Clock to data hold time 5µs 25µs

14

Figure 7: PS/2 Timing Diagram

5.1 PS/2 Keyboard The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all keyboards in use today are PS/2 style. Each key has a single, unique scan code that i s sent whenever the corresponding key i s p ressed. The scan codes fo r most keys appear in Figure 8.

Figure 8: PS/2 Keyboard with scan codes

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Some keys, called extended keys, send an “E0” ahead of the scan code and fu rthermore, they may send more than one scan code. When an extended key is released, a “E0 F0” key up code is sent, followed by the scan code. If the key i s pressed and held, the keyboard repeatedly sends the scan code every 100 ms or so. When a key i s released, the keyboard sends a “F0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has different “shift ” and “non-shift” characters and regardless whether the Shift key is pressed or not. The host determ ines which character i s intended. The most commonly used commands for PS/2 keyboard are as follows:

Table 12: Common PS/2 Keyboard Commands Command Description

ED

Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an “ED” command by replying with an “FA”, after which the host sends another byte to set LED status. The bit positions for the keyboard LEDs appear in Table 13. Write a ‘1’ to the specific bit to illuminate the associated keyboard LED.

EE Upon receiving an echo command, the keyboard replies with the same scan code “EE”.

FE Resend. Upon receiving a resend command, the keyboard resends the last scan code sent.

FF Reset. Resets the keyboard.

F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA” after which the host sends a second byte to set the repeat rate.

Table 13: LED Status 7 6 5 4 3 2 1 0

caps lock

num lock

scroll lock

The keyboard sends data to the host only when both the data and clock lines are High, the idle state. Because the host i s the “bus master”, the keyboard checks whether the host i s sending data before driving the bus. The clock line can be used as a “clear to send” signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock i s released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ sta rt bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and te rminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data i s valid on the falling edge of the clock as shown in Figure 7.

5.2 PS/2 M ouse A mouse generates a clock and data signal when moved; otherwise, these signal s remain High indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each o f the 11-bit words contains a ‘0’ start bit, followed by 8 data bits (LSB first ), followed by an odd parity bit, and term inated with a ‘1 ’ stop bit. Each data transmi ssion contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 32 are ‘1 ’ stop bits. The th ree 8-bit data fields contain movement data as shown in

16

Figure 9.Data i s valid at the falling edge of the clock, and the clock period is 20 to 30 kHz. PS/2 mouse employs a relative coordinate system wherein moving the mouse to the right generates a positive value in the X field, and moving to the left generates a negative value. Likewise, moving the mouse up generates a positive value in the Y field, and moving down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a ‘1’ indicates a negative value. The magnitude of the X and Y values represent the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates when an overflow occurs. If the mouse moves continuousl y, the 33-bit transmissions repeat every 50 ms or so . The L and R fields in the status byte indicate Left and Right button presses. A ‘1 ’ indicates that the associated mouse button i s being pressed.

Figure 9: Data format for PS/2 mouse interface

5.3 Control Signal Connection Table 14: PS/2 Interface to SPARTAN-3 FPGA

KEYBOARD Control Bit FPGA Pin

"KBD_CLOCK_QS" G19

"KBD_DATA_QS" H18

MOUSE

Control Bit FPGA Pin

"MOUSE_CLOCK_QS" J18

"MOUSE_DATA_QS" K17

17

CHAPTER 6 Switches And LEDs

6.1 DIP Switches The SPARTAN-3 development board has eight DIP switches. The switches connect to an associated FPGA pin, as shown in Table 15 A 4.7KΩ series resi stor provides nominal input protection.

Table 15: DIP switch Interface to SPARTAN-3 FPGA

Control Bit "IL0" "IL1" "IL2" "IL3" "IL4" "IL5" "IL6" "IL7"

FPGA Pin AJ12 AK11 AJ11 AJ10 AK8 AJ8 AK7 AJ7

When in the UP or ON position, a switch connects the FPGA pin to VCC O, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 m s of mechanical bounce and there i s no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.

6.2 Key Switches The SPARTAN-3 development board has four momentary-contact Key switches, indicated as in Figure xx. These are located along the lower edge of the board, toward the left edge. The switches are labeled K0 th rough K3.key switch K3 i s the left-most switch, K0 the right-most switch. The switches connect to an associated FPGA pin, as shown in Table 16. Pressing a key generates logic High on the associated FPGA pin. There is no active debouncing circuitry on the key switches.

Table 16: KEY switch Interface to SPARTAN-3 FPGA Control Bit "KEY0" "KEY1" "KEY2" "KEY3"

FPGA Pin AG20 AH20 AG19 AH19

6.3 LEDS The SPARTAN-3 development board has eight individual surface-mount red LEDs located above the key switches, indicated by in Figure xx. The LEDs are labeled LED7 through LED0. LED7 i s the left-most LED, LED0 the right-most LED. Table 17 shows the FPGA connections to the LEDs. A series current lim iting resi stor of 270Ω i s associated with every LED. To light an individual LED, drive the associated FPGA control signal High

Table 17: LED Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

"TESTLED0" AG18

"TESTLED1" AH17

"TESTLED2" AG15

"TESTLED3" AH14

"TESTLED4" AG13

"TESTLED5" AH12

"TESTLED6" AG12

"TESTLED7" AH11

18

19

CHAPTER 7 Seven Segment LED Display

The SPARTAN-3 development board has a four-character, seven segment LED di splay controlled by FPGA user-I/O pins. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate cathode control input. To light an individual signal, drive the individual segment control signal High along with the associated cathode control signal for the individual character. The control signal i s high, enabling the control inputs for the left-most character. The segment control inputs, A th rough G and DP, drive the individual segments that compri se the character. A High value lights the individual segment, a Low turns off the segment.

Figure 10: Seven Segment Display

The two types of the seven segment di splays are as shown below • Common Cathode Display: In thi s type of di splay the cathode of all the LEDs are tied

together and the anode terminals decides the sta tus of the LED, either ON or OFF. • To turn ON the LED i.e segment value of d riven segment should be 1 and 0 for turn OFF.

• Common Anode Display: In this type of display all the anode te rm inals of LEDs are tied

together and the cathode terminals decide the status of the LED either ON or OFF. • To turn ON the LED i.e. segment value of driven segment should be 0 and 1 for turn OFF.

20

Interface detail s fo r the seven segment di splay with SPART AN-3 di splay i s as follows

Table 18: Seven Segment Display Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

"SEGA" AC9

"SEGB" AF9

"SEGC" AJ6

"SEGD" AK5

"SEGE" AJ5

"SEGF" AJ4

"SEGG" AK4

"SEGDP" AG11

"CSDIS0" AD8

"CSDIS1" AC8

"CSDIS2" AD7

"CSDIS3" AE9

21

CHAPTER 8 VGA Interface

The SPARTAN-3 development board includes a VGA di splay port and DB15 connector, indicated as in Figure 1. Thi s port connects directly to most PC monitors or flat -panel LCD displays using a standard monitor cable. VGA stands for Video Graphics Array, sometimes referred to as Video Graphics Adapter. It i s a video card, which i s an interface between a computer and its corresponding monitor. The VGA card i s the most common video card – nearly every video card has VGA compatibility – and it is fairly easy to program. It offers many different video modes, f rom 2 colours to 256 colour, and resolutions f rom 320x200 to 640x480.

Figure 11: FPGA –VGA Interface

22

As shown in Figure 11, the SPARTAN-3 FPGA controls 9 VGA signals: three for Red, three fo r Green, th ree fo r Blue, Horizontal Sync, and Vertical Sync, all available on the VGA connector. The FPGA pins that drive the VGA port appear in Table 19.

Table 19: VGA Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

"RED_0" AH7

"RED_1" AG7

"RED_2" AH6

"GREEN_0" AG5

"GREEN_1" AH4

"GREEN_2" AG4

"BLUE_0" AF4

"BLUE_1" AE3

"BLUE_2" AD4

"HOR_SYNC" AG3

"VER_SYNC" AD3

Each colour line compri ses of 3 bits .Thus total of 23 x 23 x23 i.e. 256 colours are generated. The series resistor uses the 75Ω VGA cable termination to ensure that the colour si gnal s remain in the VGA-specified 0V to 0.7V range. The HS and VS signal s are TTL level. Red, Green Blue bits a re driven High or Low to generate different colours.

8.1 VGA Di splay Theory CRT-based VGA di splays use amplitude-modulated, moving electron beam s (or cathode rays) to display information on a phosphor-coated screen. LCD di splays use an array of switches that impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basi s. Although the following description is limited to CRT displays, LCD di splays have evolved to use the same signal tim ings as CRT di splays. Consequently, the following di scussion pertains to both CRT s and LCD di splays. Within a CRT display, current waveforms pass th rough the coils to produce magnetic fields that deflect electron beams to transverse the di splay surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 12, information is only di splayed when the beam is moving in the “forward” direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.

23

Figure 12: CRT Display Timing

The size of the beams, the frequency at which the beam traces across the display and the modulation frequency of electron beam determine the di splay resolution. Modern VGA di splays support multiple display resolutions, and the VGA controller dictates the resolution by producing tim ing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows th rough the deflection coils, and it ensures that pixel or video data i s applied to the electron guns a t the correct time. Video data typically comes f rom a video ref resh memory with one or more bytes assigned to each pixel location. The controller indexes into the video data buf fer as the beams move across the di splay. The controller then retrieves and applies video data to the di splay at preci sely the time the electron beam is moving across a given pixel. As shown in Figure 12, the VGA controller generates the HS (horizontal sync) and VS (vertical sync) tim ings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the di splay, or the f requency at which all information on the display i s redrawn. The m inimum refresh frequency i s a function of the di splay’s phosphor and elect ron beam intensity, with practical re fresh f requencies in the 60 Hz to 120 Hz range. The number of

24

horizontal lines displayed at a given refresh f requency defines the horizontal “re trace” frequency.

8.2 VGA si gnal TIM ING The signal timings in Table 20 are derived fo r a 640-pixel by 480-row di splay using a 25 MHz pixel clock and 60 Hz ±1 ref resh. Figure 13 shows the relation between each o f the tim ing symbols.

Figure 13: VGA Timing

The timing for the sync pul se width (TPW) and front and back porch interval s (TFP and TBP) are based on observations from various VGA di splays. The f ront and back porch interval s are the pre- and post-sync pul se times. Information cannot be di splayed during these times.

Table 20: VGA signal timing Vertical Sync Horizontal Sync Symbol Parameter

Time Clocks Lines Time Clocks

TS Sync pulse time 16.7 ms 416,800 521 32µs 800

TDISP Display time 15.36 ms 384,000 480 25.6 µs 640

TPW Pulse width 64 µs 1,600 2 3.84 µs 96

TFP Front porch 320 µs 8,000 10 640 µs 16

TBP Back porch 928 µs 23,200 29 1.92 µs 48

25

CHAPTER 9 LCD Interface

SPARTAN-3 development board includes the Oriole’s Di splay Module a dot matrix liquid crystal display that displays alphanumeric, Kana (Japanese) characters and symbols. Built in controller provides connectivity between LCD and FPGA. This LCD has a built in Dot Matrix controller, with font 5x7 or 5x10 dots, di splay data RAM for 80 characters ( 80 x 8 bit) and a character generator ROM which provides 160 characters with 5x7 font and 32 characters with font of 5x10. All the functions required fo r LCD are provided internally. Internal ref resh i s provided by the Controller. The Interface detail s of the LCD di splay are as shown in figure 14.

Figure 14: LCD Interface to SPARTAN-3 FPGA

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9.1 Data Lines Connection LCD has 8 bit bidirectional data bus interface to FPGA. The data bus interface has a th ree state construction. When Enable signal is at low level, these data bus terminal remain in high impedance state. Interface detail s of the data lines with SPARTAN-3 FPGA are as in Table 21.

Table 21: Data Line Interface to SPARTAN-3 FPGA Data Bit FPGA Pin

"DL0_QS" C27

"DL1_QS" D27

"DL2_QS" D28

"DL3_QS" E27

"DL4_QS" F28

"DL5_QS" G27

"DL6_QS" G28

"DL7_QS" H27

9.2 Control Line Interface: The control lines of LCD comprises of RS, R/W# and E The significance of the above mentioned control signals i s as follows • RS: Regi ster select signal used to select Data register or a Command/Status register.

High on RS selects the data register. Low on RS selects the Command/Status regi ster.

• R/W#: Read/Write select control line.

High on R/W # selects the read operation Low on R/W # selects the write operation.

• E: Enable signal used to enable or di sable the data bus.

Low on the enable signal puts the data bus into a high impedance state. High on the enable signal selects the data bus.

The control line interface of LCD with FPGA i s as shown in table

Table 22: Control Line Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

"RS_QS" G17

"E_QS" D26

"R/W_QS" C25

27

CHAPTER 10 10/100 Non PCI Ethernet Interface

SPARTAN-3 development board has a 10 / 100 Mbps Ethernet inte rface using LAN 91C111 from SMSC. The block diagram for the same i s as shown in figure 10.1. This interface i s designed to facilitate the implementation of fast Ethernet connectivity for embedded applications. LAN 91C111 i s a mixed analog/digital device that implements MAC and PHY portion of CSMA /CD protocol at 10 and 100 Mbps. SMSC LAN 91C111 provides a flexible slave interface to industry standard bus interface. Supports 32, 16 and 8 bit bus host interface with synchronous and asynchronous data t ransfer modes. Two different interfaces are supported on network side. The first inte rface is standard magnetics transmit –receive pair inte rfacing to 10/100 Base –T utilizing internal physical layer block. Second i s a MII (Media Independent Interface) specification standard that use nibble wide data transfer. Thi s i s applicable for both 10 and 100 Mbps speed.

Interface detail s fo r the Ethernet interface are as mentioned below.

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Figure 15: LAN 91C111 Interface to SPARTAN-3 FPGA

10.1 System Address Bus Connection These consi st of A1-A15, AEN and nBE0-nBE3 signals. • A1-A15: Address bus input. LAN 91C111 uses A1-A3 to access internal registers selection

while A4-A15 i s used fo r address decoding for register access. • AEN: Address enable signal, active low on these signal s enables the address decoding. • nBE0 – nBE3: Active low byte valid used to define the width of access and regi sters being

accessed.

Table 23: Address Bus Interface to SPARTAN-3 FPGA Address Bit FPGA Pin

"LAN_A1" AB30

"LAN_A2" AB29

"LAN_A3" AC30

"LAN_A4" AC29

"LAN_A5" AD30

"LAN_A6" AD29

"LAN_A7" AE29

"LAN_A8" AF30

"LAN_A9" AF29

"LAN_A10" AG30

"LAN_A11" AG29

"LAN_A12" V21

"LAN_A13" T25

"LAN_A14" W22

"LAN_A15" W21

"LAN_AEN" AF27

“LAN_nBE0” Y21

“LAN_nBE1” AA22

“LAN_nBE2” AB22

“LAN_nBE3” AA21

10.2 System Data Bus Connection 32 bit bidirectional data bus used to access the LAN 91C111 internal registers. Data bus has an internal weak pull-up.

Table 24: Data Bus Interface to SPARTAN-3 FPGA Data Bit FPGA Pin

"LAN_D0" W25

"LAN_D1" W26

29

"LAN_D2" V25

"LAN_D3" V26

Data Bit FPGA Pin

"LAN_D4" U25

"LAN_D5" AA19

"LAN_D6" AA20

"LAN_D7" AB21

"LAN_D8" AA29

"LAN_D9" Y29

"LAN_D10" Y30

"LAN_D11" W29

"LAN_D12" W30

"LAN_D13" V29

"LAN_D14" V30

"LAN_D15" U29

"LAN_D16" T29

"LAN_D17" T30

"LAN_D18" R29

"LAN_D19" R30

"LAN_D20" W24

"LAN_D21" W23

"LAN_D22" Y24

"LAN_D23" Y23

"LAN_D24" AE28

"LAN_D25" AD27

"LAN_D26" AD28

"LAN_D27" AC27

"LAN_D28" AC28

"LAN_D29" AB27

"LAN_D30" AA28

"LAN_D31" Y27

10.3 Control Signals Connection Control signals are broadly categorized into three types • Synchronous Bus interface signal s • Asynchronous Bus interface signal s • M iscellaneous control signals

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10.3.1 Synchronous bus interface signals Following are the synchronous bus interface signals: • nCycle : Active low synchronous signal used to control EISA burst cycle. • nVL Bus: Active low signal to enable VL Bus interface. • W/nRD : Defines the direction of the cycle. High enables write cycles and low enables read

signal s. • LCLK : Synchronous bus clock . Maximum lim it is 50 MHz. During asynchronous cycle thi s

pin is tied high. • nSRDY : Thi s signal i s used to extend the access in VL Bus interface mode. Falling edge of

this signal indicates the cycle completion • nRDYRTN: Input to SMSC LAN 91C111 used to control completion of read cycle. Sampled

on falling edge of LCLK and synchronous cycles are delayed until it is sampled high.

Table 25: Synchronous Bus Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

LAN_CYCLE" AH25

"LAN_nSRD" V27

"LAN_RDYRTN" W28

"W/nR" AG26

"\VLBUS\" AG28

10.3.2 Asynchronous bus interface signals Following are the asynchronous bus interface signal s • ARDY: Used to extend the bus access in asynchronous bus interface. • nRD : Active low read strobe • nWR: Active low write st robe. • nADS: Address A1-A15 and AEN are latched on rising edge of nADS.

Table 26: Asynchronous Bus Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

ARDY AG27

nRD AG23

nWR AH24

nADS AH27

10.3.3 Miscellaneous Signals: • Reset: When thi s pin is asserted controller perfo rms system reset.(MAC + PHY ) • INTR: Active high input to interrupt the FPGA. • nCS: Output chip select used to provide fo r mapping of PHY functions into LAN 91C111

decoded space. • nLDEV: It i s a combinatorial decode of unlatched address and AEN signal. • IOS0, IOS1, and IOS2: Select the predefined EEPROM configuration. • ENEEP: Enables access to external serial EEPROM.

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Table 27: Miscellaneous Signals Interface to SPARTAN-3 FPGA Control Bit FPGA Pin

LAN_rst AH23

LAN_INTR" AG22

"LAN_nCS" AG24

LAN_nDEV" Y28

IOS0 Y26

IOS1 Y25

IOS2 AA25

ENEEP AB26

For detailed of SMSC LAN91C111 refer its datasheet and application note an96.

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CHAPTER 11 Connector Details

SPARTAN-3 Development Board has provision fo r 3 types connectors that can be categorized as follows:

11.1 IO Connectors These provide access to f ree IOs on board. • IOCON1: 50 pin connector provides 47 free IOs. • IOCON2: 50 pin connector provides 40 free IOs. • IOCON3: 50 pin connector provides 40 free IOs. • IOCON4: 50 pin connector provides 32 free IOs. • IOCON5:40 pin connector provides 38 free IOs. • IOCON6 :40 pin connector provides 32 free IOs • IOCON7: 40. pin connector provides 32 free IOs • IOCON8 : 40 pin connector provides 32 free IOs • IOCON9 : 40 pin connector p rovides 32 free IOs Table 28 gives the interface details of IOCON1 connector to FPGA

Table 28: IOCON1 Connector Interface to FPGA

Net Name FPGA

Pin NO Connector Details

Net Name FPGA Pin NO

Connector Details

"F_IO303" C10 #IOCON1 - 1 "F_IO327" A18 #IOCON1 - 31

"F_IO304" D11 #IOCON1 - 2 "F_IO328" B18 #IOCON1 - 32

"F_IO305" B5 #IOCON1 - 3 "F_IO329" A19 #IOCON1 - 33

"F_IO306" A5 #IOCON1 - 4 "F_IO330" B19 #IOCON1 - 34


"F_IO308" B7 #IOCON1 - 6 "F_IO332" B20 #IOCON1 - 36 "F_IO309" A7 #IOCON1 - 7 "F_IO333" B21 #IOCON1 - 37




"F_IO313" A9 #IOCON1 - 13 "F_IO337" B23 #IOCON1 - 43 "F_IO314" B10 #IOCON1 - 14 "F_IO338" A24 #IOCON1 - 44

"F_IO315" B11 #IOCON1 - 15 "F_IO339" B24 #IOCON1 - 45

"F_IO316" A11 #IOCON1 - 16 "F_IO340" D24 #IOCON1 - 46


"F_IO318" A12 #IOCON1 - 18 "F_IO333" B21 #IOCON1 - 37 "F_IO319" B13 #IOCON1 - 21 "F_IO334" A22 #IOCON1 - 38




"F_IO323" A15 #IOCON1 - 25 "F_IO338" A24 #IOCON1 - 44

"F_IO324" A16 #IOCON1 - 26 "F_IO339" B24 #IOCON1 - 45 "F_IO325" B16 #IOCON1 - 27 "F_IO340" D24 #IOCON1 - 46

"F_IO326" B17 #IOCON1 - 28

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Table 29 gives the interface details of IOCON2 connector to FPGA

Table 29: IOCON2 Connector Interface to FPGA Net Name

FPGA Pin

Connector Details

Net Name

FPGA Pin

Connector Details

"F_IO255" F7 #IOCON2 - 1 "F_IO275" E19 #IOCON2 - 25

"F_IO256" F8 #IOCON2 - 2 "F_IO276" F19 #IOCON2 - 26 "F_IO257" E8 #IOCON2 - 3 "F_IO277" E20 #IOCON2 - 27

"F_IO258" F9 #IOCON2 - 4 "F_IO278" F20 #IOCON2 - 28

"F_IO259" E9 #IOCON2 - 5 "F_IO279" F21 #IOCON2 - 31 "F_IO260" F10 #IOCON2 - 6 "F_IO280" E22 #IOCON2 - 32

"F_IO261" F11 #IOCON2 - 7 "F_IO281" F22 #IOCON2 - 33 "F_IO262" E11 #IOCON2 - 8 "F_IO282" E23 #IOCON2 - 34

"F_IO263" F12 #IOCON2 - 11 "F_IO283" K11 #IOCON2 - 35

"F_IO264" E12 #IOCON2 - 12 "F_IO284" K12 #IOCON2 - 36 "F_IO265" F13 #IOCON2 - 13 "F_IO285" H11 #IOCON2 - 37

"F_IO266" E13 #IOCON2 - 14 "F_IO286" G11 #IOCON2 - 38

"F_IO267" F14 #IOCON2 - 15 "F_IO287" H12 #IOCON2 - 41 "F_IO268" F15 #IOCON2 - 16 "F_IO288" G12 #IOCON2 - 42

"F_IO269" E15 #IOCON2 - 17 "F_IO289" H13 #IOCON2 - 43 "F_IO270" E16 #IOCON2 - 18 "F_IO290" G14 #IOCON2 - 44

"F_IO271" F16 #IOCON2 - 21 "F_IO291" H15 #IOCON2 - 45

"F_IO272" F17 #IOCON2 - 22 "F_IO292" G15 #IOCON2 - 46 "F_IO273" E18 #IOCON2 - 23 "F_IO293" G16 #IOCON2 - 47

"F_IO274" F18 #IOCON2 - 24 "F_IO294" H16 #IOCON2 - 48 Table 30 gives the interface details of IOCON3 connector to FPGA

Table 30: IOCON3 Connector Interface to FPGA Net Name

FPGA Pin

Connector Pin

Net Name

FPGA Pin

Connector Pin

"F_IO207" C4 #IOCON3 - 1 "F_IO227" D18 #IOCON3 - 25

"F_IO208" D5 #IOCON3 - 2 "F_IO228" C19 #IOCON3 - 26

"F_IO209" C6 #IOCON3 - 3 "F_IO229" D19 #IOCON3 - 27 "F_IO210" J9 #IOCON3 - 4 "F_IO230" C20 #IOCON3 - 28

"F_IO211" J10 #IOCON3 - 5 "F_IO231" AD24 #IOCON3 - 31 "F_IO212" D7 #IOCON3 - 6 "F_IO232" D20 #IOCON3 - 32

"F_IO213" C7 #IOCON3 - 7 "F_IO233" C21 #IOCON3 - 33

"F_IO214" D8 #IOCON3 - 8 "F_IO234" D22 #IOCON3 - 34 "F_IO215" C8 #IOCON3 - 11 "F_IO235" C23 #IOCON3 - 35

"F_IO216" D9 #IOCON3 - 12 "F_IO236" D23 #IOCON3 - 36

"F_IO217" C11 #IOCON3 - 13 "F_IO237" C24 #IOCON3 - 37 "F_IO218" D12 #IOCON3 - 14 "F_IO238" J12 #IOCON3 - 38

"F_IO219" C12 #IOCON3 - 15 "F_IO239" K13 #IOCON3 - 41

"F_IO220" D13 #IOCON3 - 16 "F_IO240" AC24 #IOCON3 - 42

"F_IO221" C14 #IOCON3 - 17 "F_IO241" K14 #IOCON3 - 43

"F_IO222" D15 #IOCON3 - 18 "F_IO242" J14 #IOCON3 - 44 "F_IO223" C15 #IOCON3 - 21 "F_IO243" K15 #IOCON3 - 45

"F_IO224" C16 #IOCON3 - 22 "F_IO244" J15 #IOCON3 - 46

34

Net Name

FPGA Pin

Connector Pin

Net Name

FPGA Pin

Connector Pin

"F_IO225" D16 #IOCON3 - 23 "F_IO245" J16 #IOCON3 - 47 "F_IO226" C17 #IOCON3 - 24 "F_IO246" K16 #IOCON3 - 48



Net Name FPGA Pin Connector

Pin Net Name FPGA Pin Connector Pin

"F_IO1" AD10 #IOCON4 - 1 "F_IO21" AF22 #IOCON4 - 25

"F_IO2" AC11 #IOCON4 - 2 "F_IO22" J13 #IOCON4 - 26

"F_IO3" AD11 #IOCON4 - 3 "F_IO23" AB23 #IOCON4 - 27

"F_IO4" AC12 #IOCON4 - 4 "F_IO24" AA24 #IOCON4 - 28 "F_IO5" AD12 #IOCON4 - 5 "F_IO25" AA11 #IOCON4 - 31

"F_IO6" AC13 #IOCON4 - 6 "F_IO26" AA12 #IOCON4 - 32

"F_IO7" AD14 #IOCON4 - 7 "F_IO27" AB12 #IOCON4 - 33 "F_IO8" AC15 #IOCON4 - 8 "F_IO28" AA13 #IOCON4 - 34

"F_IO9" AB9 #IOCON4 - 11 "F_IO29" AB13 #IOCON4 - 35 "F_IO10" AB10 #IOCON4 - 12 "F_IO30" AA15 #IOCON4 - 36

"F_IO11" AC16 #IOCON4 - 13 "F_IO31" AB15 #IOCON4 - 37

"F_IO12" AC18 #IOCON4 - 14 "F_IO32" AA16 #IOCON4 - 38

"F_IO13" AD19 #IOCON4 - 15 "F_IO33" AB16 #IOCON4 - 41


"F_IO15" AD20 #IOCON4 - 17 "F_IO35" AA17 #IOCON4 - 43 "F_IO16" AC20 #IOCON4 - 18 "F_IO36" AB18 #IOCON4 - 44

"F_IO17" AD21 #IOCON4 - 21 "F_IO37" AA18 #IOCON4 - 45


"F_IO19" AD23 #IOCON4 - 23 "F_IO39" AD10 #IOCON4 - 47

"F_IO20" AC23 #IOCON4 - 24 Table 32 gives the interface details of IOCON5 connector to FPGA

Table 32 IOCON5 Connector Interface to FPGA Net Name

FPGA Pin

Connector Pin

Net Name FPGA Pin Connector

Pin

"F_IO49" AE10 #IOCON5- 1 "F_IO65" AE19 #IOCON5- 21 "F_IO50" AE11 #IOCON5- 2 "F_IO66" AF20 #IOCON5- 22

"F_IO51" AF11 #IOCON5- 3 "F_IO67" AE20 #IOCON5- 23

"F_IO52" AE12 #IOCON5- 4 "F_IO68" AE21 #IOCON5- 24 "F_IO53" AF12 #IOCON5- 5 "F_IO69" AE22 #IOCON5- 25

"F_IO54" AE13 #IOCON5- 6 "F_IO70" AF23 #IOCON5- 26 "F_IO55" AF13 #IOCON5- 7 "F_IO71" AE23 #IOCON5- 27

"F_IO56" AE14 #IOCON5- 8 "F_IO72" AE24 #IOCON5- 28

"F_IO57" AE15 #IOCON5- 11 "F_IO73" AF25 #IOCON5- 31 "F_IO58" AF15 #IOCON5- 12 "F_IO74" AE25 #IOCON5- 32

"F_IO59" AF16 #IOCON5- 13 "F_IO75" AE26 #IOCON5- 33

"F_IO60" AE16 #IOCON5- 14 "F_IO76" AD25 #IOCON5- 34 "F_IO61" AE17 #IOCON5- 15 "F_IO77" AC25 #IOCON5- 35

"F_IO62" AF18 #IOCON5- 16 "F_IO78" AC26 #IOCON5- 36 "F_IO63" AE18 #IOCON5- 17 "F_IO79" AK24 #IOCON5- 37

35

"F_IO64" AF19 #IOCON5- 18 "F_IO80" AJ23 #IOCON5- 38 Table 33 gives the interface details of IOCON6 connector to FPGA


Net Name FPGA Pin

Connector Details Net Name FPGA

Pin Connector Details

"F_IO113" AB14 #IOCON6- 38 "F_IO129" AJ18 #IOCON6- 18

"F_IO114" AA14 #IOCON6- 37 "F_IO130" AK18 #IOCON6- 17

"F_IO115" AB25 #IOCON6- 36 "F_IO131" AJ17 #IOCON6- 16 "F_IO116" AK28 #IOCON6- 35 "F_IO132" AJ16 #IOCON6- 15

"F_IO117" AJ26 #IOCON6- 34 "F_IO133" AK16 #IOCON6- 14

"F_IO118" AK26 #IOCON6- 33 "F_IO134" AK15 #IOCON6- 13

"F_IO119" AJ25 #IOCON6- 32 "F_IO135" AJ14 #IOCON6- 12

"F_IO120" AJ24 #IOCON6- 31 "F_IO136" AK13 #IOCON6- 11

"F_IO121" AK23 #IOCON6- 28 "F_IO137" AJ13 #IOCON6- 8 "F_IO122" AJ22 #IOCON6- 27 "F_IO138" AD16 #IOCON6- 7

"F_IO123" AK22 #IOCON6- 26 "F_IO139" AD15 #IOCON6- 6 "F_IO124" AJ21 #IOCON6- 25 "F_IO140" AK12 #IOCON6- 5

"F_IO125" AJ20 #IOCON6- 24 "F_IO141" AE8 #IOCON6- 4

"F_IO126" AK20 #IOCON6- 23 "F_IO142" AE7 #IOCON6- 3 "F_IO127" AJ19 #IOCON6- 22 "F_IO143" AF6 #IOCON6- 2

"F_IO128" AK19 #IOCON6- 21 "F_IO144" AE6 #IOCON6- 1 Table 34 gives the interface details of IOCON7 connector to FPGA. IOs on connector IOCON3 are al so mapped to MICTOR connector (J10) for interface of Logic Analyzer. This connector provides 34 IOs for interface.


Net Name FPGA Pin

Connector Pin

Net Name FPGA Pin

Connector Pin

"MICTOR1" G1 #IOCON7- 8 "MICTOR18" L1 #IOCON7- 21

"MICTOR2" H2 #IOCON7- 11 "MICTOR20" M2 #IOCON7- 22 "MICTOR3" G2 #IOCON7- 7 "MICTOR21" AF8 #IOCON7- 38

"MICTOR4" H1 #IOCON7- 12 "MICTOR22" M1 #IOCON7- 23

"MICTOR5" F2 #IOCON7- 6 "MICTOR23" AG2 #IOCON7- 37 "MICTOR6" J2 #IOCON7- 13 "MICTOR24" N2 #IOCON7- 24

"MICTOR7" E1 #IOCON7- 5 "MICTOR25" W1 #IOCON7- 36

"MICTOR8" J1 #IOCON7- 14 "MICTOR26" N1 #IOCON7- 25

"MICTOR9" E2 #IOCON7- 4 "MICTOR27" V2 #IOCON7- 35

"MICTOR10" K2 #IOCON7- 15 "MICTOR28" P2 #IOCON7- 26 "MICTOR11" D1 #IOCON7- 3 "MICTOR29" V1 #IOCON7- 34

"MICTOR12" L2 #IOCON7- 16 "MICTOR30" R2 #IOCON7- 27

"MICTOR13" D2 #IOCON7- 2 "MICTOR31" T2 #IOCON7- 32 "MICTOR14" H8 #IOCON7- 17 "MICTOR32" R1 #IOCON7- 28

"MICTOR15" G8 #IOCON7- 1 "MICTOR33" U2 #IOCON7- 33

"MICTOR16" G7 #IOCON7- 18 "MICTOR34" T1 #IOCON7- 31

36



Net Name FPGA Pin

Connector Pin Net Name FPGA

Pin Connector

Pin "F_IO177" D4 #IOCON8- 1 "F_IO193" U10 #IOCON8- 21 "F_IO178" D3 #IOCON8- 2 "F_IO194" V9 #IOCON8- 22 "F_IO179" E4 #IOCON8- 3 "F_IO195" V10 #IOCON8- 23 "F_IO180" F3 #IOCON8- 4 "F_IO196" W9 #IOCON8- 24 "F_IO181" L10 #IOCON8- 5 "F_IO197" W10 #IOCON8- 25 "F_IO182" M10 #IOCON8- 6 "F_IO198" Y10 #IOCON8- 26 "F_IO183" M9 #IOCON8- 7 "F_IO199" AA9 #IOCON8- 27 "F_IO184" N10 #IOCON8- 8 "F_IO200" AA10 #IOCON8- 28 "F_IO185" N9 #IOCON8- 11 "F_IO201" W2 #IOCON8- 31 "F_IO186" P10 #IOCON8- 12 "F_IO202" Y1 #IOCON8- 32 "F_IO187" P9 #IOCON8- 13 "F_IO203" Y2 #IOCON8- 33 "F_IO188" R10 #IOCON8- 14 "F_IO204" AA2 #IOCON8- 34 "F_IO189" R9 #IOCON8- 15 "F_IO205" AB1 #IOCON8- 35 "F_IO190" T9 #IOCON8- 16 "F_IO206" AB2 #IOCON8- 36 "F_IO191" T10 #IOCON8- 17 "MICTOR17" AG1 #IOCON8- 38 "F_IO192" U9 #IOCON8- 18 "MICTOR19" AC1 #IOCON8- 37



Net Name FPGA Pin

Connector Pin

Net Name FPGA Pin

Connector Pin

"F_IO145" AF2 #IOCON9 37 "F_IO161" T4 #IOCON9 17

"F_IO146" AF1 #IOCON9 38 "F_IO162" T3 #IOCON9 18

"F_IO147" AE2 #IOCON9 35 "F_IO163" R3 #IOCON9 15

"F_IO148" AD2 #IOCON9 36 "F_IO164" R4 #IOCON9 16

"F_IO149" AD1 #IOCON9 33 "F_IO165" P3 #IOCON9 13 "F_IO150" AC2 #IOCON9 34 "F_IO166" N4 #IOCON9 14

"F_IO151" AC4 #IOCON9 31 "F_IO167" M3 #IOCON9 11

"F_IO152" AC3 #IOCON9 32 "F_IO168" M4 #IOCON9 12

"F_IO153" AB4 #IOCON9 27 "F_IO169" L3 #IOCON9 7

"F_IO154" AA3 #IOCON9 28 "F_IO170" L4 #IOCON9 8 "F_IO155" Y4 #IOCON9 25 "F_IO171" K3 #IOCON9 5

"F_IO156" Y3 #IOCON9 26 "F_IO172" J4 #IOCON9 6

"F_IO157" W4 #IOCON9 23 "F_IO173" H3 #IOCON9 3

"F_IO158" W3 #IOCON9 24 "F_IO174" H4 #IOCON9 4

"F_IO159" V4 #IOCON9 21 "F_IO175" G3 #IOCON9 1

"F_IO160" U3 #IOCON9 22 "F_IO176" G4 #IOCON9 2

11.2 Stackable Connector Two stackable connectors J1 and J2 are provided on board for the interface of ADD ON daughter boards (optional) provided along with the SPARTAN-3 Development board. Table 37 gives the interface details of Stackable connector to FPGA.

Table 37: Stackable Connector Interface to FPGA Net Name

FPGA Pin

Connector Details

Net Name

FPGA Pin

Connector Details

"STEC_IO0" K18 #J1 - 2 "STEC_IO23" G25 #J1 - 27

"STEC_IO2" H19 #J1 - 4 "STEC_IO24" L26 #J1 - 32

37

Net Name

FPGA Pin

Connector Details

Net Name

FPGA Pin

Connector Details

"STEC_IO1" J19 #J1 - 1 "STEC_IO25" H25 #J1 - 31 "STEC_IO3" G20 #J1 - 3 "STEC_IO26" M25 #J1 - 34

"STEC_IO4" K19 #J1 - 6 "STEC_IO27" H26 #J1 - 33

"STEC_IO5" H20 #J1 - 5 "STEC_IO28" M26 #J1 - 36 "STEC_IO6" K20 #J1 - 8 "STEC_IO29" G29 #J1 - 35

"STEC_IO7" G21 #J1 - 7 "STEC_IO30" G30 #J1 - 38

"STEC_IO8" J21 #J1 - 12 "STEC_IO31" F29 #J1 - 37 "STEC_IO9" H22 #J1 - 11 "STEC_IO32" H29 #J1 - 40

"STEC_IO10" G24 #J1 - 14 "STEC_IO33" E30 #J1 - 39

"STEC_IO11" G23 #J1 - 13 "STEC_IO34" H30 #J1 - 42 "STEC_IO12" H23 #J1 - 16 "STEC_IO35" E29 #J1 - 41

"STEC_IO13" F23 #J1 - 15 "STEC_IO36" J29 #J1 - 44 "STEC_IO14" H24 #J1 - 18 "STEC_IO37" D30 #J1 - 43

"STEC_IO15" F24 #J1 - 17 "STEC_IO38" J30 #J1 - 46

"STEC_IO16" J25 #J1 - 22 "STEC_IO39" D29 #J1 - 45 "STEC_IO17" E25 #J1 - 21 "STEC_IO40" K29 #J1 - 48

"STEC_IO18" J26 #J1 - 24 "STEC_IO41" B26 #J1 - 47

"STEC_IO19" F25 #J1 - 23 "STEC_IO42" L29 #J1 - 50 "STEC_IO20" K25 #J1 - 26 "STEC_IO43" A26 #J1 - 49

"STEC_IO21" F26 #J1 - 25 "STEC_IO44" L30 #J1 - 52 "STEC_IO22" L25 #J1 - 28 "STEC_IO45" B25 #J1 - 51

"STEC_IO46" V22 #J2 - 2 "STEC_IO68" R24 #J2 - 28

"STEC_IO47" P22 #J2 - 1 "STEC_IO69" M24 #J2 - 27 "STEC_IO48" U21 #J2 - 4 "STEC_IO70" R23 #J2 - 32

"STEC_IO49" P21 #J2 - 3 "STEC_IO71" M23 #J2 - 31

"STEC_IO50" U22 #J2 - 6 "STEC_IO72" P24 #J2 - 34 "STEC_IO51" N22 #J2 - 5 "STEC_IO73" L24 #J2 - 33

"STEC_IO52" T21 #J2 - 8 "STEC_IO74" T26 #J2 - 36 "STEC_IO53" N21 #J2 - 7 "STEC_IO75" L23 #J2 - 35

"STEC_IO54" T22 #J2 - 12 "STEC_IO76" R26 #J2 - 38

"STEC_IO55" M22 #J2 - 11 "STEC_IO77" K24 #J2 - 37 "STEC_IO56" R22 #J2 - 14 "STEC_IO78" R25 #J2 - 42

"STEC_IO57" M21 #J2 - 13 "STEC_IO79" J23 #J2 - 41

"STEC_IO58" R21 #J2 - 16 "STEC_IO80" U28 #J2 - 44 "STEC_IO59" L21 #J2 - 15 "STEC_IO81" P25 #J2 - 43

"STEC_IO60" V23 #J2 - 18 "STEC_IO82" T27 #J2 - 46 "STEC_IO61" K22 #J2 - 17 "STEC_IO83" N26 #J2 - 45

"STEC_IO62" U24 #J2 - 22 "STEC_IO84" P29 #J2 - 48

"STEC_IO63" K21 #J2 - 21 "STEC_IO85" N25 #J2 - 47 "STEC_IO64" T23 #J2 - 24 "STEC_IO86" N29 #J2 - 52

"STEC_IO65" J22 #J2 - 23 "STEC_IO87" M29 #J2 - 51

"STEC_IO66" T24 #J2 - 26 "STEC_IO88" N30 #J2 - 54 "STEC_IO67" N23 #J2 - 25 "STEC_IO89" M30 #J2 - 53

The positional details of these connectors on development board i s as shown in figure 16

38

Figure 16: Positional Details of On Board Connectors

39

CHAPTER 12 Clock and Reset Sources

The SPARTAN-3 Development board has a dedicated 40 MHz oscillator source and an optional socket fo r another clock oscillator source. This dedicated clock source can be used to derive other f requencies using DCM (digital clock mangers) available in SPARTAN-3 FPGA. Another clock oscillator can be mounted on 8 pin DIP Socket whose footprint i s compatible with oscillators upto 200 MHz. SPARTAN-3 development board has a on board reset ci rcuitry (a key switch) that i s used to reset (active high) the hardware present on the board. Board also provides facility for external clock which i s selected by connecting jumper JP1 The interface details of clock and reset with FPGA i s given in Table 31.

Table 38: IO Clock-Reset Interface to FPGA Control Bit FPGA Pin

Clock AJ15

Clock1 AH15

Reset AH21

External Clock B15

40

CHAPTER 13 SPA RTA N-3 Configuration Details

SPARTAN-3 development board supports two configuration modes as stated below • Boundary Scan mode • Master Serial Mode

13.1 Boundary Scan mode: In boundary scan mode of configuration the SPARTAN-3 FPGA i s directly configured via a JTAG port using the dedicated configuration pins TCK, TMS, TDI and TDO. The jumper setting for selection of boundary scan mode is di scussed in jumper set ting section (section 12.3).

13.2 Master Serial M ode In master serial mode the SPARTAN-3 i s configured through a FLASH PROM. In Master Serial mode, the FPGA automatically loads the configuration bitst ream in bit-serial form from configuration flash synchronized by the configuration clock (CCLK) generated by the FPGA. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Master Serial configuration mode. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines (INIT and DONE) are required to configure an FPGA. Data from the PROM is read out sequentially on a single data line (DIN), accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The serial Bitst ream data must be set up at the FPGA’s DIN input pin a short time before each ri sing edge of the FPGA's internally generated CCLK signal. The jumper setting for selection of Master Serial Mode is discussed in jumper setting section (section 12.3).

13.3 Jumper Setting • Mode Selection Jumpers: M0, M1, M2 are the mode selection jumpers used to select the

configuration mode either Boundary Scan or Master Serial Mode.

Table 39: Mode Selection Jumper Settings

Configuration Mode 1 2

MODE0 (M0)

MODE1 (M1)

MODE2 (M2)

• Connecting 1-2 selects Logic –0,

• Disconnecting 1-2 selects Logic- 1

Table 40: Mode Selection Table

Configuration Mode MODE0 MODE1 MODE2 Boundary Scan Mode 1 0 1

Master Serial Mode 0 0 0

41

• JTAG Chain Selection Jumper: JP2 jumper i s used to select the JTAG chain for configuration. When jumper is connected between 2-3, then PROM and FPGA both get added in the JTAG Chain where as connecting jumper between 1-2 brings only FPGA in Chain.

Figure 17: JTAG Mode Selection

42

13.4 JTAG Header: An on board JT AG connector is provided for configuring the FPGA through parallel port of PC via a parallel III cable. The details of thi s connector are as shown in figure 18.

Figure 18: JTAG Connector Deta ils

43

CHAPTER 14 Power Supplies

SPARTAN-3 Development board i s p rovided with a regulated power supply of + 5V DC output. This supply i s used to generate the required on board supply voltages. Output of the regulated power supply i s given to power connector present on board. The power LED (Red LED) lights up when power i s p roperly applied to the board.

14.1 Voltage Regulator s The list of various voltage regulators present on board are as given in Table 34.

Table 41: Power Supply Details Voltage Source

+ 5 V DC Generated f rom external power supply provided along with the development Board.

+ 3.3 V DC A regulated 3.3 V DC supply i s generated on board using a DC-DC converter PTH05010W with input voltage of 5 Volts

+2.5 V DC A regulated 2.5 V DC supply i s generated onboard using a linear low drop out regulator LT1963 with input voltage of 3.3 Volts

+1.8 V DC A regulated 1.8 V DC supply i s generated onboard using a linear low drop out regulator LT1963 with input voltage of 3.3 Volts

+1.2 V DC A regulated 1.2 V DC supply i s generated on board using a DC-DC converter PTH05010W with input voltage of 5 Volts

-5V DC A negative supply i s generated on board using a inverting charge pump MAX1673 with input voltage of 5 Volts

Overall, the 5V DC switching power adapter powers the board. a 3.3V regulator, powered by the 5V DC supply, p rovides power to the inputs of the 2.5V and 1.2V regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s I/O banks and powers most of the components on the board. The 2.5V regulator supplies power to the FPGA’s VCCAUX supply inputs. The FPGA configuration interface on the board i s powered by 3.3V. Consequently, the 2.5V supply has a current shunt resi stor to prevent reverse current. Finally, a 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which power the FPGA’s core logic.

44

APPENDIX A Consolidated UCF For The Complete Board

Clock And Reset

net "CLOCK" LOC = AJ15 net "CLOCK1" LOC = AH15

net "RESET" LOC = AH21

net “External Clock” LOC = B15

Free IOs

net "F_IO1_QS" LOC = AD10

net "F_IO2_QS" LOC = AC11 net "F_IO3_QS" LOC = AD11

net "F_IO4_QS" LOC = AC12




net "F_IO8_QS" LOC = AC15 net "F_IO9_QS" LOC = AB9

net "F_IO10_QS" LOC = AB10



net "F_IO13_QS" LOC = AD19 net "F_IO14_QS" LOC = AC19




net "F_IO18_QS" LOC = AC22 net "F_IO19_QS" LOC = AD23


net "F_IO21_QS" LOC = AF22

net "F_IO23_QS" LOC = J13


net "F_IO25_QS" LOC = AA24 net "F_IO26_QS" LOC = AA11

net "F_IO27_QS" LOC = AA12



net "F_IO30_QS" LOC = AB13 net "F_IO31_QS" LOC = AA15





PC-2

Cross-Out

PC-2

Cross-Out

45


net "F_IO38_QS" LOC = AA18 net "F_IO39_QS" LOC = AB19

net "F_IO49_QS" LOC = AE10 net "F_IO50_QS" LOC = AE11


net "F_IO52_QS" LOC = AE12 net "F_IO53_QS" LOC = AF12

net "F_IO54_QS" LOC = AE13

net "F_IO55_QS" LOC = AF13 net "F_IO56_QS" LOC = AE14













net "F_IO76_QS" LOC = AD25 net "F_IO77_QS" LOC = AC25


net "F_IO79_QS" LOC = AK24 net "F_IO80_QS" LOC = AJ23



net "F_IO116_QS" LOC = AK28 net "F_IO117_QS" LOC = AJ26

net "F_IO118_QS" LOC = AK26

net "F_IO119_QS" LOC = AJ25 net "F_IO120_QS" LOC = AJ24


net "F_IO122_QS" LOC = AJ22 net "F_IO123_QS" LOC = AK22

net "F_IO124_QS" LOC = AJ21 net "F_IO125_QS" LOC = AJ20

46




net "F_IO131_QS" LOC = AJ17




net "F_IO137_QS" LOC = AJ13 net "F_IO138_QS" LOC = AD16


net "F_IO140_QS" LOC = AK12 net "F_IO141_QS" LOC = AE8



net "F_IO145_QS" LOC = AF2 net "F_IO146_QS" LOC = AF1


net "F_IO148_QS" LOC = AD2 net "F_IO149_QS" LOC = AD1


net "F_IO151_QS" LOC = AC4 net "F_IO152_QS" LOC = AC3


net "F_IO155_QS" LOC = Y4

net "F_IO156_QS" LOC = Y3 net "F_IO157_QS" LOC = W4

net "F_IO158_QS" LOC = W3

net "F_IO159_QS" LOC = V4 net "F_IO160_QS" LOC = U3

net "F_IO161_QS" LOC = T4

net "F_IO162_QS" LOC = T3 net "F_IO163_QS" LOC = R3

net "F_IO164_QS" LOC = R4 net "F_IO165_QS" LOC = P3

net "F_IO166_QS" LOC = N4

net "F_IO167_QS" LOC = M3 net "F_IO168_QS" LOC = M4

net "F_IO169_QS" LOC = L3

net "F_IO170_QS" LOC = L4 net "F_IO171_QS" LOC = K3

net "F_IO172_QS" LOC = J4 net "F_IO173_QS" LOC = H3

47

net "F_IO174_QS" LOC = H4

net "F_IO175_QS" LOC = G3 net "F_IO176_QS" LOC = G4

net "F_IO177_QS" LOC = D4 net "F_IO178_QS" LOC = D3

net "F_IO179_QS" LOC = E4

net "F_IO180_QS" LOC = F3 net "F_IO181_QS" LOC = L10

net "F_IO182_QS" LOC = M10

net "F_IO183_QS" LOC = M9 net "F_IO184_QS" LOC = N10

net "F_IO185_QS" LOC = N9 net "F_IO186_QS" LOC = P10

net "F_IO187_QS" LOC = P9

net "F_IO188_QS" LOC = R10 net "F_IO189_QS" LOC = R9

net "F_IO190_QS" LOC = T9

net "F_IO191_QS" LOC = T10 net "F_IO192_QS" LOC = U9

net "F_IO193_QS" LOC = U10 net "F_IO194_QS" LOC = V9

net "F_IO195_QS" LOC = V10

net "F_IO196_QS" LOC = W9 net "F_IO197_QS" LOC = W10


net "F_IO199_QS" LOC = AA9 net "F_IO200_QS" LOC = AA10

net "F_IO201_QS" LOC = W2 net "F_IO202_QS" LOC = Y1




net "F_IO207_QS" LOC = C4 net "F_IO208_QS" LOC = D5

net "F_IO209_QS" LOC = C6

net "F_IO210_QS" LOC = J9 net "F_IO211_QS" LOC = J10

net "F_IO212_QS" LOC = D7 net "F_IO213_QS" LOC = C7

net "F_IO214_QS" LOC = D8





48


net "F_IO223_QS" LOC = C15 net "F_IO224_QS" LOC = C16





net "F_IO231_QS" LOC = AD24 net "F_IO232_QS" LOC = D20




net "F_IO238_QS" LOC = J12

net "F_IO239_QS" LOC = K13 net "F_IO240_QS" LOC = AC24

net "F_IO241_QS" LOC = K14 net "F_IO242_QS" LOC = J14

net "F_IO243_QS" LOC = K15

net "F_IO244_QS" LOC = J15 net "F_IO245_QS" LOC = J16


net "F_IO255_QS" LOC = F7 net "F_IO256_QS" LOC = F8

net "F_IO257_QS" LOC = E8 net "F_IO258_QS" LOC = F9




net "F_IO263_QS" LOC = F12 net "F_IO264_QS" LOC = E12

net "F_IO265_QS" LOC = F13

net "F_IO266_QS" LOC = E13 net "F_IO267_QS" LOC = F14







49

net "F_IO278_QS" LOC = F20




net "F_IO284_QS" LOC = K12 net "F_IO285_QS" LOC = H11

net "F_IO286_QS" LOC = G11

net "F_IO287_QS" LOC = H12 net "F_IO288_QS" LOC = G12

net "F_IO289_QS" LOC = H13 net "F_IO290_QS" LOC = G14


net "F_IO292_QS" LOC = G15 net "F_IO293_QS" LOC = G16



net "F_IO305_QS" LOC = B5 net "F_IO306_QS" LOC = A5

net "F_IO307_QS" LOC = B6



net "F_IO311_QS" LOC = A8 net "F_IO312_QS" LOC = B9




net "F_IO318_QS" LOC = A12









net "F_IO332_QS" LOC = B20 net "F_IO333_QS" LOC = B21

50






M ICTOR Connector

net "MICTOR1_QS" LOC = G1

net "MICTOR2_QS" LOC = H2 net "MICTOR3_QS" LOC = G2

net "MICTOR4_QS" LOC = H1

net "MICTOR5_QS" LOC = F2 net "MICTOR6_QS" LOC = J2

net "MICTOR7_QS" LOC = E1

net "MICTOR8_QS" LOC = J1

net "MICTOR9_QS" LOC = E2 net "MICTOR10_QS" LOC = K2

net "MICTOR11_QS" LOC = D1

net "MICTOR12_QS" LOC = L2

net "MICTOR13_QS" LOC = D2

net "MICTOR14_QS" LOC = H8

net "MICTOR15_QS" LOC = G8 net "MICTOR16_QS" LOC = G7

net "MICTOR17_QS" LOC = AG1

net "MICTOR18_QS" LOC = L1 net "MICTOR19_QS" LOC = AC1

net "MICTOR20_QS" LOC = M2

net "MICTOR21_QS" LOC = AF8 net "MICTOR22_QS" LOC = M1

net "MICTOR23_QS" LOC = AG2

net "MICTOR24_QS" LOC = N2

net "MICTOR25_QS" LOC = W1 net "MICTOR26_QS" LOC = N1

net "MICTOR27_QS" LOC = V2

net "MICTOR28_QS" LOC = P2

net "MICTOR29_QS" LOC = V1

net "MICTOR30_QS" LOC = R2

net "MICTOR31_QS" LOC = T2 net "MICTOR32_QS" LOC = R1

net "MICTOR33_QS" LOC = U2

net "MICTOR34_QS" LOC = T1

Stackable Connector

net "STEC_IO0" LOC = K18

net "STEC_IO1" LOC = H19

net "STEC_IO2" LOC = J19

net "STEC_IO3" LOC = G20

51


net "STEC_IO5" LOC = H20 net "STEC_IO6" LOC = K20

net "STEC_IO7" LOC = G21 net "STEC_IO8" LOC = J21


net "STEC_IO10" LOC = G24 net "STEC_IO11" LOC = G23


net "STEC_IO13" LOC = F23 net "STEC_IO14" LOC = H24

net "STEC_IO15" LOC = F24 net "STEC_IO16" LOC = J25

net "STEC_IO17" LOC = E25

net "STEC_IO18" LOC = J26 net "STEC_IO19" LOC = F25


net "STEC_IO21" LOC = F26 net "STEC_IO22" LOC = L25

net "STEC_IO23" LOC = G25 net "STEC_IO24" LOC = L26


net "STEC_IO26" LOC = M25 net "STEC_IO27" LOC = H26

net "STEC_IO28" LOC = M26

net "STEC_IO29" LOC = G29 net "STEC_IO30" LOC = G30

net "STEC_IO31" LOC = F29 net "STEC_IO32" LOC = H29

net "STEC_IO33" LOC = E30

net "STEC_IO34" LOC = H30 net "STEC_IO35" LOC = E29


net "STEC_IO37" LOC = D30 net "STEC_IO38" LOC = J30

net "STEC_IO39" LOC = D29

net "STEC_IO40" LOC = K29 net "STEC_IO41" LOC = B26

net "STEC_IO42" LOC = L29 net "STEC_IO43" LOC = A26

net "STEC_IO44" LOC = L30

net "STEC_IO45" LOC = B25 net "STEC_IO46" LOC = V22

net "STEC_IO47" LOC = P22

net "STEC_IO48" LOC = U21 net "STEC_IO49" LOC = P21

net "STEC_IO50" LOC = U22 net "STEC_IO51" LOC = N22

52

net "STEC_IO52" LOC = T21

net "STEC_IO53" LOC = N21 net "STEC_IO54" LOC = T22

net "STEC_IO55" LOC = M22 net "STEC_IO56" LOC = R22


net "STEC_IO58" LOC = R21 net "STEC_IO59" LOC = L21

net "STEC_IO60" LOC = V23

net "STEC_IO61" LOC = K22 net "STEC_IO62" LOC = U24

net "STEC_IO63" LOC = K21 net "STEC_IO64" LOC = T23


net "STEC_IO66" LOC = T24 net "STEC_IO67" LOC = N23

net "STEC_IO68" LOC = R24

net "STEC_IO69" LOC = M24 net "STEC_IO70" LOC = R23

net "STEC_IO71" LOC = M23 net "STEC_IO72" LOC = P24

net "STEC_IO73" LOC = L24

net "STEC_IO74" LOC = T26 net "STEC_IO75" LOC = L23

net "STEC_IO76" LOC = R26

net "STEC_IO77" LOC = K24 net "STEC_IO78" LOC = R25

net "STEC_IO79" LOC = J23 net "STEC_IO80" LOC = U28


net "STEC_IO82" LOC = T27 net "STEC_IO83" LOC = N26


net "STEC_IO85" LOC = N25 net "STEC_IO86" LOC = N29


net "STEC_IO88" LOC = N30 net "STEC_IO89" LOC = M30

LED interface

net "TESTLED0" LOC = AG18 net "TESTLED1" LOC = AH17

net "TESTLED2" LOC = AG15 net "TESTLED3" LOC = AH14

net "TESTLED4" LOC = AG13

net "TESTLED5" LOC = AH12 net "TESTLED6" LOC = AG12

net "TESTLED7" LOC = AH11

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Switch interface net "IL0" LOC = AJ12

net "IL1" LOC = AK11

net "IL2" LOC = AJ11

net "IL3" LOC = AJ10

net "IL4" LOC = AK8

net "IL5" LOC = AJ8

net "IL6" LOC = AK7

net "IL7" LOC = AJ7

Serial Interface RS232

net "TXD1-F" LOC = AH8

net "TXD2-F" LOC = AG8

net "RXD1-F" LOC = AG9

net "RXD2-F" LOC = AH10 Serial Interface RS422

net "TTL_IN1_QS" LOC = G10

net "TTL_IN2_QS" LOC = H9

net "TTL_OUT1_QS" LOC = E6

net "TTL_OUT2_QS" LOC = F6 Seven Segment LED Display interface

net "CSDIS0_QS" LOC = AD8

net "CSDIS1_QS" LOC = AC8

net "CSDIS2_QS" LOC = AD7

net "CSDIS3_QS" LOC = AE9 net "SEGA_QS" LOC = AC9

net "SEGB_QS" LOC = AF9 net "SEGC_QS" LOC = AJ6

net "SEGD_QS" LOC = AK5 net "SEGDP_QS" LOC = AG11

net "SEGE_QS" LOC = AJ5 net "SEGF_QS" LOC = AJ4

net "SEGG_QS" LOC = AK4

LCD interface

net "DL0_QS" LOC = C27

net "DL1_QS" LOC = D27

net "DL2_QS" LOC = D28

net "DL3_QS" LOC = E27

net "DL4_QS" LOC = F28

net "DL5_QS" LOC = G27

net "DL6_QS" LOC = G28

net "DL7_QS" LOC = H27

net "E_QS" LOC = D26

net "R/W_QS" LOC = C25 net "RS_QS" LOC = G17

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KEY Interface

net "KEY0" LOC = AG20

net "KEY1" LOC = AH20

net "KEY2" LOC = AG19

net "KEY3" LOC = AH19

VGA interface

net "GREEN_0" LOC = AG5

net "GREEN_1" LOC = AH4

net "GREEN_2" LOC = AG4

net "RED_0" LOC = AH7 net "RED_1" LOC = AG7

net "RED_2" LOC = AH6

net "BLUE_0" LOC = AF4

net "BLUE_1" LOC = AE3

net "BLUE_2" LOC = AD4 net "HOR_SYNC" LOC = AG3

net "VER_SYNC" LOC = AD3

USB interface

net "USB_D0" LOC = T28

net "USB_D1" LOC = R28

net "USB_D2" LOC = R27

net "USB_D3" LOC = P28 net "USB_D4" LOC = N27

net "USB_D5" LOC = M28

net "USB_D6" LOC = M27 net "USB_D7" LOC = L28

net "RD#" LOC = K28

net "WR#" LOC = J27

net "TXE#" LOC = H28 net "RXF#" LOC = L27

PS/2 Key Board Interface

net "KBD_CLOCK_QS" LOC = G19

net "KBD_DATA_QS" LOC = H18 PS/2 Mouse Interface

net "MOUSE_CLOCK_QS" LOC = J18

net "MOUSE_DATA_QS" LOC = K17

LAN interface Data Lines

net "LAN_D0" LOC = W25

net "LAN_D1" LOC = W26 net "LAN_D2" LOC = V25

net "LAN_D3" LOC = V26

net "LAN_D4" LOC = U25 net "LAN_D5" LOC = AA19

55

net "LAN_D6" LOC = AA20

net "LAN_D7" LOC = AB21


net "LAN_D9" LOC = Y29






net "LAN_D15" LOC = U29

net "LAN_D16" LOC = T29

net "LAN_D17" LOC = T30

net "LAN_D18" LOC = R29

net "LAN_D19" LOC = R30





net "LAN_D24" LOC = AE28

net "LAN_D25" LOC = AD27

net "LAN_D26" LOC = AD28

net "LAN_D27" LOC = AC27

net "LAN_D28" LOC = AC28

net "LAN_D29" LOC = AB27



Address Lines:

net "LAN_A1" LOC = AB30

net "LAN_A2" LOC = AB29

net "LAN_A3" LOC = AC30

net "LAN_A4" LOC = AC29

net "LAN_A5" LOC = AD30

net "LAN_A6" LOC = AD29

net "LAN_A7" LOC = AE29

net "LAN_A8" LOC = AF30

net "LAN_A9" LOC = AF29

net "LAN_A10" LOC = AG30 net "LAN_A11" LOC = AG29

net "LAN_A12" LOC = V21

net "LAN_A13" LOC = T25

net "LAN_A14" LOC = W22 net "LAN_A15" LOC = W21

net "LAN_nBE0" LOC = Y21

net "LAN_nBE1" LOC = AA22

56

net "LAN_nBE2" LOC = AB22

net "LAN_nBE3" LOC = AA21

net "LAN_AEN" LOC = AF27 Control Signals

net "ENEEP" LOC = AB26

net "IOS0" LOC = Y26

net "IOS1" LOC = Y25 net "IOS2" LOC = AA25

net "LAN_ARDY" LOC = AG27

net "LAN_CYCLE" LOC = AH25 net "LAN_INTR" LOC = AG22

net "LAN_nADS" LOC = AH27 net "LAN_nCS" LOC = AG24

net "LAN_nDEV" LOC = Y28

net "LAN_nLCLK" LOC = W27

net "LAN_nRD" LOC = AG23 net "LAN_nSRD" LOC = V27

net "LAN_nWR" LOC = AH24 net "LAN_RDYRTN" LOC = W28

net "LAN_RST" LOC = AH23

net "\INIT\" LOC = AG16

net "\VLBUS\" LOC = AG28 net "W/nR" LOC = AG26

SDRAM interface Address Lines

net "A0_S1" LOC = AA7

net "A1_S1" LOC = Y8

net "A2_S1" LOC = Y7

net "A3_S1" LOC = K7

net "A4_S1" LOC = L8

net "A5_S1" LOC = L7 net "A6_S1" LOC = M8

net "A7_S1" LOC = M7

net "A8_S1" LOC = N8 net "A9_S1" LOC = P7

net "A10_S1" LOC = AB8

net "A11_S1" LOC = AC7 net "BA0_S1" LOC = V8

net "BA1_S1" LOC = W7

DATA Lines net "D0_S1" LOC = AE5

net "D1_S1" LOC = AD6

net "D2_S1" LOC = AC6

net "D3_S1" LOC = AC5

net "D4_S1" LOC = AB6 net "D5_S1" LOC = AB5

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net "D6_S1" LOC = AA6

net "D7_S1" LOC = Y6 net "D8_S1" LOC = L6

net "D9_S1" LOC = K6 net "D10_S1" LOC = J5

net "D11_S1" LOC = J6

net "D12_S1" LOC = H5 net "D13_S1" LOC = H6

net "D14_S1" LOC = G6

net "D15_S1" LOC = F5 net "D16_S1" LOC = T5

net "D17_S1" LOC = T6 net "D18_S1" LOC = U6

net "D19_S1" LOC = V5

net "D20_S1" LOC = V6 net "D21_S1" LOC = W5

net "D22_S1" LOC = W6

net "D23_S1" LOC = Y5 net "D24_S1" LOC = R5

net "D25_S1" LOC = R6 net "D26_S1" LOC = P6

net "D27_S1" LOC = N5

net "D28_S1" LOC = N6 net "D29_S1" LOC = M5

net "D30_S1" LOC = M6

net "D31_S1" LOC = L5 net "DQM0_S1" LOC = R8

net "DQM1_S1" LOC = H7 net "DQM2_S1" LOC = W8

net "DQM3_S1" LOC = J8 Control Lines

net "CKE_S1" LOC = K9

net "CLK_S1" LOC = K10

net "CS#_S1" LOC = U7 net "RAS#_S1" LOC = T8

net "CAS#_S1" LOC = T7

net "WE#_S1" LOC = R7

58

APPENDIX B Operating Instruction To Start A New Design

B.1 Starting The ISE Softwar e: • Start ISE f rom the Start menu by selecting Start -> Programs -> Xilinx ISE Project

Navigator.

B.2 Design Flow • DESIGN ENTRY • SIMULATION • SYNTHESIS • IMPLEMENTATION • DEVICE PROGRAMMING

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Sample Design of Half Adder i s used to explain the Design Flow.

B.3 Design Description

Half Adder

A

B

Sum

Carry

B.4 Truth Table of Half adder

Inputs Output A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

B.5 VHDL Code for Half adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end full_adder; architecture Behavioral of half_adder is begin sum <= a xor b ; carry <= a and b; end Behavioral;

60

B.6 Steps to implement the Half adder in the FPGA using Xilinx iSE(8.1i) Step 1 : Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start

Programs Xilinx ISE (8.1i)

Source Window

Process Window

Workspace

Transcript

Step 2 Create a new project In the window go to FILE New project. Specify the project name and location and say NEXT

Select Device. Use the pull-down arrow to select the Value for each Property Name. Click in the field to access the pull-down list.

61

Say FINISH. Project summary is seen.

62

Step 3: Creating a new VHD file

Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the File name

VHDL Module

Then say Next Define ports.In this case

• a and b are the input ports defined as in • sum and carry are output ports defined as out

after thi s say Next twice and then Finish Skeleton of the design is shown in the VHDL editor.

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Step 4: Writing the Behavioral VHDL Code in VHDL Editor

Sample code is given below for thi s experiment.

Design Entry

Step 5 Check Syntax Run the Check syntax Process window synthesize check syntax >, and remove errors if present.

Step 6 Creating a test bench file Verify the operation of your design before you implement it as hardware. Simulation can be done using ISE simulator. For thi s click on the symbol of FPGA device and then right click Click on new source Test Bench Waveform and give the name Select entity Finish.

Select the desi red parameters fo r simulating your design. In thi s case combinational circuit and Si mulation time.

64

Step 7: Si mulate the code

Si mulation Tools ISE tool supports the following si mulation tools: • HDL Bencher is an automated test bench creation tool. It is fully integrated with

Pro ject Navigator. • ModelSi m f rom Model Technology, Inc., is integrated in Project Navigator to

simulate the design at all steps (Functional and Timing). ModelSim XE, the Xilinx Edition of Model Technology, Inc.’s ModelSi m application, can be installed from the MTI CD included in your ISE Tool

In source Window from the Drop-down menu select Behavioral Si mulation to view the created test Bench file.

65

For simulation

Click on test bench file. Test bench file will open in main window. Assign all the signal s and save File. From the source of process window. Click on Si mulate Behavioral Model in Process window.

Verify your design in wave window by seeing behaviour of output signal with respect to input signal. Close the ISE simulator window

66

Simulated Output

Step 8: Synthesize the design using XST. Translate your design into gates and optimize it for the target a rchitecture . This i s the synthesi s phase. Again for synthesi zing your design, from the source window select, synthesis/ Implementation f rom the drop-down menu.

Synthesis

Highlight file in the Sources in Project window. To run synthesi s, right-click on

67

Synthesize, and the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesi s will run, and

• a green check will appear next to Synthesi ze when it i s successfully completed.

• a red cross indicates an error was generated and • a yellow exclamation ! mark indicates that a warning was generated,

(warnings are OK). Check the synthesi s report. If there are any errors correct it and rerun synthesi s..

Synthesis completed successfully

Step 9: Create Constraints File(UCF) Click on the symbol of FPGA device and then right click Click on new source

Implementation Constraints File and give the name Select entity Fini sh. Click on User Constraint and in that Double Click on Assign Package Pins option in Process window. Xilinx PACE window opens. Enter all the pin assignments in PACE., depending upon ta rget device and number of input and outputs used in your design. (sample code is given below for given design.)

68

Pin assignments

Step 10: Implementing a Design

Once synthesi s i s complete, you can place and route your design to fit into a Xilinx device, and you can also get some post place-and-route timing information about the design. The implementation stage consi sts of taking the synthesi zed netlist through translation, mapping, and place and route. To check your design as it i s implemented, reports are available for each stage in the implementation process. Use the Xilinx Constraints Editor to add timing and location constraints fo r the implementation of your design. Thi s procedure runs you through the basi c flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

Implementation done

69

Step 11: Generating Progra mming File

Right-click on Generate Programming File, choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream

Step 12 Downloading in Boundary Scan Mode. Note : Xilinx provides 2-tools for downloading purpose, viz. • iMPACT - is a command line and GUI based tool • PROM File For matter

Boundary Scan Mode

Procedure for downloading using iMPACT • Boundary Scan Mode

1. Right click on “Configure Device (i MPACT)” -> and Say RUN or Double click on “Configure Device (i MPACT)”.

2. Right click in workspace and say Initialize chain .The device i s seen. 3. Right click on the device and say Program.

If the device i s programmed properly, it says Programming Succeeded or else. Programming Failed. The DONE Led glows green if programming succeeds.

70

Note: Before downloading make sure that Protoboard i s connected to PC's parallel port with the cable provided and power to the Protoboard i s ON.

Step 13: Apply input through DIP Switches, output is displayed on LEDs Step 14: Configuration through PROM: Generating PROM file:

FPGA can also be configured in Master Serial Mode through PROM. For this you need to program the PROM through a .mcs file.

Right click on “Generate PROM,ACE or JTAG file” -> and Say RUN or Double click on “Generate PROM,ACE or JTAG file”

Specify the PROM file name and location where it is to be generated.

71

Specify the desired parameters of the PROM on board and say ADD then FINISH

72

Say Generate File from the Process Window.

PROGRAMMING THE PROM

Note: Check the Jumper setting on the board. Ref er the Chapt er jumper Setting Similar to Step 12.Initialize chain through iMPACT. PROM and FPGA devices on board are seen .Assign the generated mcs file and bit file as desired. Right click the PROM symbol and say PROGRAM.

73

Now, whenever the board i s powered on in master serial mode, FPGA i s configured through PROM automatically.

74

APPENDIX C ASCII Table 5 X 7 LCD Display

The ASCII code fo r 5 x 7 LCD Display is as shown below:

75

APPENDIX D ADC–DA C Add On Card

About this Card: ADC- DAC add on card provides an analog interface to the VIRTEX-5, VIRTEX-4 and SPARTAN-3 based development board developed by Bitmapper Integration Technologies PVT Ltd.. This interface enables the user to implement design that involve dual channel analog input and output function that can be used fo r communication, video and DSP based applications. Add On Card Details: ADC-DAC add on card compri ses of a two single channel ADC AD9240 and DAC 7541 fo rm TI. The specifications of the above mentioned are as follows: ADC AD9240: • 14 bit analog to digital converter with sampling rate of 10 MSPS. • Operates on single supply voltage of 5 V. • A single-ended CLK input control s converter operation. • Input range of 0 to 5 .0 V. DAC AD7541: • 12 bit 10 MSPS digital to analog converter. • Dual input channel. • Single supply voltage of 5V. Control of the A/Ds and D/As i s handled by the FPGA through a SAMTEC connector interface provided on mother board and add on card. The supply voltage for the ADC/DAC interface is also provided via a SAMTEC connector. The interface details fo r the ADC and DAC unit with FPGA are as mentioned in section E-1 and E-2. E-1: ADC Interface Details: Block diagram for ADC interface as shown below:

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Unipolar analog input of amplitude range 0 – 5.0 V can be applied at analog in of SMA connector J3 and J4. ADC can sample the input at up to 10Msps sampling rate with a resolution of 14 bit. Data lines of ADC are interfaced to FPGA to process the sampled data. OTR signal provides the over-range indication. Clock to ADC is provided th rough FPGA. The AD9240 uses four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last, consi sts of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash in put fo r the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consi sts of a flash A/D. The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency i s not a concern in most applications. The digital output, together with the out-of -range indicator (OT R), i s latched into an output buffe r to drive the output pins. The output d rivers can be configured to interface with +5 V or +3.3 V logic families.

77

The timing diagram for ADC i s as shown below:

Output of ADC i s in straight binary format with lowest value representing all ‘0’s and highest value representing all ‘1’s. For more detail s on ADC AD9240 please refer the datasheet provided along with thi s board

78

E-2: DAC Interface Details: Block diagram for DAC interface i s as shown below

Data lines of both the DACs are interfaced to FPGA. Analog output o f DACs i s available on SMA connector J5 and J6.The range available at DAC output extends f rom 0 to 5V for a reference voltage of 2.5V. Thi s range can be varied by adjusting the value of Vref by varying the value of preset PR11 and PR12 for DAC1 and DAC2 respectively. AD7541A does not require an input clock for its operation and has a conversion time of 100ns with 12 bit resolution. Input to DAC is in straight binary fo rmat with lowest value represented by all ‘0’s and highest value represented by all ‘1’s. For more details on DAC please refer the datasheet p rovided along with the board.

79

The User constraint file for the ADC –DAC add on card i s as in table C-1. NET NAME CONNECTOR

PIN NO. FPGA PIN NO.

VIRTEX-4 PROTOBOARD

SPARTAN-3 5M

PROTBOARD

SPARTAN-3 5M PCI

PROTOBOARD

VIRTEX-5 PROTOBOARD

DAC-1 "DAC1-D0" IO-34 #J1-42 LOC = H21 LOC = H30 LOC = G6 LOC = M24 "DAC1-D1" IO-36 #J1-44 LOC = G24 LOC = J29 LOC = F5 LOC = N23 "DAC1-D2" IO-38 #J1-46 LOC = H23 LOC = J30 LOC = F6 LOC = N24 "DAC1-D3" IO-40 #J1-48 LOC = H24 LOC = K29 LOC = E6 LOC = P24 "DAC1-D4" IO-42 #J1-50 LOC = J23 LOC = L29 LOC = F8 LOC = P23 "DAC1-D5" IO-44 #J1-52 LOC = K23 LOC = L30 LOC = F7 LOC = R23 "DAC1-D6" IO-32 #J1-40 LOC = H22 LOC = H29 LOC = T4 LOC = R21 "DAC1-D7" IO-28 #J1-36 LOC = J22 LOC = M26 LOC = G11 LOC = P21 "DAC1-D8" IO-26 #J1-34 LOC = K21 LOC = M25 LOC = H12 LOC = N22 "DAC1-D9" IO-24 #J1-32 LOC = K22 LOC = L26 LOC = G12 LOC = N21 "DAC1-D10" IO-22 #J1-28 LOC = L21 LOC = L25 LOC = H13 LOC = M22 "DAC1-D11" IO-20 #J1-26 LOC = N22 LOC = K25 LOC = G14 LOC = M21 DAC-2 "DAC2-D0" IO-0 #J1-2 LOC = C24 LOC = K18 LOC = J12 LOC = K20 "DAC2-D1" IO-1 #J1-1 LOC = D16 LOC = H19 LOC = K13 LOC = J19 "DAC2-D2" IO-5 #J1-5 LOC = D17 LOC = H20 LOC = K14 LOC = T25 "DAC2-D3" IO-7 #J1-7 LOC = D18 LOC = G21 LOC = J14 LOC = P26 "DAC2-D4" IO-9 #J1-11 LOC = C19 LOC = H22 LOC = K15 LOC = P25 "DAC2-D5" IO-11 #J1-13 LOC = D19 LOC = G23 LOC = M3 LOC = G21 "DAC2-D6" IO-12 #J1-16 LOC = G23 LOC = H23 LOC = H8 LOC = P20 "DAC2-D7" IO-10 #J1-14 LOC = F24 LOC = G24 LOC = G7 LOC = N19 "DAC2-D8" IO-8 #J1-12 LOC = F23 LOC = J21 LOC = J9 LOC = M20 "DAC2-D9" IO-6 #J1-8 LOC = E24 LOC = K20 LOC = J10 LOC = M19 "DAC2-D10" IO-4 #J1-6 LOC = E23 LOC = K19 LOC = K11 LOC = Y12 "DAC2-D11" IO-2 #J1-4 LOC = D24 LOC = J19 LOC = K12 LOC = L19 ADC-1 "ADC1_D1" IO-82 #J2-46 LOC = V23 LOC = T27 LOC = AD3 LOC = AB24 "ADC1_D2" IO-72 #J2-34 LOC = AA24 LOC = P24 LOC = U3 LOC = AB20 "ADC1_D3" IO-68 #J2-28 LOC = V22 LOC = R24 LOC = AD20 LOC = AB19 "ADC1_D4" IO-59 #J2-15 LOC = U21 LOC = L21 LOC = AE6 LOC = U20 "ADC1_D5" IO-57 #J2-13 LOC = J20 LOC = M21 LOC = AE5 LOC = U19 "ADC1_D6" IO-55 #J2-11 LOC = K20 LOC = M22 LOC = AD6 LOC = V19 "ADC1_D7" IO-53 #J2-7 LOC = L19 LOC = N21 LOC = AC6 LOC = W20 "ADC1_D8" IO-51 #J2-5 LOC = L20 LOC = N22 LOC = AC5 LOC = W19 "ADC1_D9" IO-49 #J2-3 LOC = M19 LOC = P21 LOC = AB6 LOC = Y20 "ADC1_D10" IO-47 #J2-1 LOC = M20 LOC = P22 LOC = AB5 LOC = Y18 "ADC1_D11" IO-50 #J2-6 LOC = P20 LOC = U22 LOC = AC13 LOC = Y12 "ADC1_D12" IO-46 #J2-2 LOC = R20 LOC = V22 LOC = AC12 LOC = Y10 "ADC1_D13" IO-48 #J2-4 LOC = P19 LOC = U21 LOC = AD12 LOC = Y11 "ADC1_D14" IO-62 #J2-22 LOC = W21 LOC = U24 LOC = AC18 LOC = AB17 "ADCCLK1" IO-58 #J2-16 LOC = Y21 LOC = R21 LOC = AD16 LOC = AA15 "OTR1" IO-86 #J2-52 LOC = U24 LOC = N29

LOC = AE3 LOC = AA24

ADC-2 "ADC2_D1" IO-67 #J2-25 LOC = R23 LOC = N23

LOC = AF8 LOC = Y22

"ADC2_D2" IO-69 #J2-27 LOC = P22 LOC = M24 LOC = AE9 LOC = W21 "ADC2_D3" IO-71 #J2-31 LOC = R24 LOC = M23 LOC = AF9 LOC = U21

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NET NAME CONNECTOR PIN NO.

FPGA PIN NO.

VIRTEX-4 PROTOBOARD

SPARTAN-3 5M

PROTBOARD

SPARTAN-3 5M PCI

PROTOBOARD

VIRTEX-5 PROTOBOARD

"ADC2_D4" IO-73 #J2-33 LOC = P23 LOC = L24 LOC = AE10 LOC = U22 "ADC2_D5" IO-75 #J2-35 LOC = P24 LOC = L23 LOC = AE11 LOC = T22 "ADC2_D6" IO-77 #J2-37 LOC = N24 LOC = K24 LOC = AF11 LOC = W23 "ADC2_D7" IO-79 #J2-41 LOC = N23 LOC = J23 LOC = W4 LOC = W24 "ADC2_D8" IO-81 #J2-43 LOC = M24 LOC = P25 LOC = Y3 LOC = V23 "ADC2_D9" IO-83 #J2-45 LOC = M23 LOC = N26 LOC = Y4 LOC = V24 "ADC2_D10" IO-85 #J2-47 LOC = L24 LOC = N25 LOC = AA3 LOC = U24 "ADC2_D11" IO-87 #J2-51 LOC = L23 LOC = M29 LOC = AB4 LOC = T23 "ADC2_D12" IO-89 #J2-53 LOC = K24 LOC = M30 LOC = AG3 LOC = T24 "ADC2_D13" IO-88 #J2-54 LOC = T23 LOC = N30 LOC = AF4 LOC = Y23 "ADC2_D14" IO-63 #J2-21 LOC = T21 LOC = K21 LOC = AE7 LOC = AA22 "ADCCLK2" IO-61 #J2-17 LOC = U22 LOC = K22 LOC = AF6 LOC = T19 "OTR2" IO-65 #J2-23 LOC = T24 LOC = J22 LOC = AE8 LOC = Y21

Table E-1: ADC – DAC Add on Card User Constraint File

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APPENDIX E Video A DC – DA C Add On Card

About this Card: Video ADC- DAC add on card provides an Video interface to the VIRTEX-5, VIRTEX-4 and SPARTAN-3 based development board developed by Bitmapper Integration Technologies PVT Ltd. This interface enables the user to implement design that involve for digitizing of video data for Digital TV, Digital Video, Multimedia, Video Capture, Video Editing and Security Applications. Interface consi sts of th ree channel s Video ADC TLV 7534 and th ree channels Video DAC THS8133b and a SYNC Separator from Texas and supports NTSC and PAL compliant video input. Control of the Video A/D and D/A i s handled by the FPGA through a SAMTEC connector interface provided on mother board and add on card. The supply voltage fo r the Video ADC/DAC interface is al so provided th rough SAMTEC connector. The interface details fo r the ADC and DAC unit with FPGA as described below

FPGA –VIDEO Interface

F.1 Video ADC interface Add on card has a TLV 5734 ADC f rom Texas Instruments. The TLV5734 i s a t riple 8-bit converter with high-preci sion clamp for digitizing video signal s in RGB or YUV color spaces. The device supports pixel rates up to 30 MSPS. The TLV5734 i s powered from a single 3.3-V supply. Separate clamping levels are provided fo r the RGB and YUV analog component video inputs. The clamp timing window is provided by an external pul se. The output-data formatter selects from output formats of 4:4:4, 4:1:1, and 4:2:2. For RGB applications, the 4:4:4 output fo rmats with clamp can be used. For more details on Video ADC refer TLV5734 datasheet.

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As shown in figure R(Y) video input can be applied at SMA connector J7, G(U) video input can be applied at SMA connector J6 and B(V) video input is applied at SMA connector J8. The interface details fo r the Video ADC interface are as described below:

Pin Description for Video ADC Interface Name Pin Description

Mode0, Mode1 Output format mode selector

INIT

Output initialized. The output data is synchronized with the first falling edge of CLK after INIT changes from low to high. INIT is a control terminal that allows the external system to initialize the TLV5734 data conversion cycl

EXTCLP External clamp pulse input (active high)

G/Y Video input mode selector, low for RGB, high for YUV

AD1 – AD8 Data output of ADC A (MSB:AD8, LSB:AD1) (format 1, format 2, format 3)

BD1 – BD8 Data output of ADC B (MSB:BD8, LSB:BD1) (format 2)

CD1 – CD8 Data output of ADC C (MSB:CD8, LSB:CD1) (format 2)

CLK Clock input. The clock frequency is four times the frequency subcarrier (fsc) for most video systems

F.2 VIDEO DAC

The THS8133 is a general-purpose t riple high-speed D/A converter (DAC) optimized for use in video/graphics applications. The device operates f rom a 5-V analog supply and a 3-V to 5-V range digital supply. The T HS8133 has a sampling rate up to 80 MSPS. The device consi sts of three 10-bit D/A converters and additional circuitry fo r bi-level/t ri-level sync and blanking level generation in video applications. The current-steering DACs can be directly terminated in resi stive loads to produce voltage outputs.

Furthermore, the T HS8133 can generate both a t raditional bi-level sync and a t ri-level sync signal, as per the SMPTE standards, via a digital control interface. The sync signal is inserted on one of the analog output channels (sync-on-green/lum inance) or on all output channel s. Also, a blanking control signal sets the outputs to defined level s during the nonactive video window.

DAC output i s available on SMA connector J3, J4 and J5. For more details refer THS8133b Handbook. The interface details fo r the Video DAC interface are as described below:

Pin Description for Video DAC Name Pin Description

DAC0-Pb9 to DAC0-Pb0 Blue or Pb pixel data input bus. Index 0 denotes the least significant bit

DAC0-Pr9 to DAC0-Pr0 Red or Pr pixel data input bus. Index 0 denotes the least significant bit.

DAC0-Y9 to DAC0-Y0 Green or Y pixel data input bus. Index 0 denotes the least significant bit.

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BLANK-0 #

Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY and ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) will result in sync generation.

SYNC -0 #

Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output or ARPr, AGY and ABPb outputs are driven to the sync level, irrespective of the values on the data or BLANK inputs. Consequently, SYNC should remain low for the whole duration of sync, which is in the case of tri-level sync both the negative and positive portion.

SYNC_T0

Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted, a positive sync (higher than blanking level) is generated when SYNC is low. When disabled, a negative sync (lower than blanking level) is generated when SYNC is low. When generating a tri-level (negative-to-positive) sync, a L "H transition on this signal positions the start of the positive transition. See Figure 6 for timing control. The value on SYNC_T is ignored when SYNC is not asserted (high).

CLK –DAC

Clock input. A rising edge on CLK latches RPr0-9, GY0-9, BPb0-9, BLANK, SYNC, and SYNC_T. The M2 input is latched by a rising edge on CLK also, but only when additional conditions are satisfied, as explained in its terminal description.

M1, M2 Used for operational mode configuration.

F.3 SYNC SEPERATOR The EL4583 the Sync Separator extracts timing from video sync in NTSC, PAL, and SECAM systems, and non standard fo rmats, o r from computer g raphics operating at higher scan rates. Timing adjustment is via an external resi stor. Input without valid vertical interval (no serration pulses) produces a default vertical output. Outputs are : composite sync, vertical sync, filter, burst/back porch, horizontal, no signal detect, level, and odd/even output (in interlaced scan fo rmats only). The EL4583 sync slice level is set to the m id-point between sync tip and the blanking level. This 50% point i s determined by two internal sample and hold circuits that t rack sync tip and back porch level s. It provides hum and noi se rejection and compensates for input level s of 0.5V to 2.0VP-P. A built in filter attenuates the chroma signal to prevent color burst from disturbing the 50% sync slice. Cut of f frequency i s set by a resi stor to ground f rom the Filter Cut Off pin. Additionally, the filter can be by-passed and video signal fed directly to the Video Input. The level output pin provides a signal with twice the sync amplitude which may be used to control an external AGC function. A TTL/CMOS compatible No Signal Detect Output flags a loss or reduction in input signal level. A resi stor sets the Set Detect Level.

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Pin Description of the sync separator interface to that of FPGA i s as shown below:

Pin Description for SYNC Separator Interface Name Pin Description

Vertical Sync Output

The vertical sync output is synchronous with the first serration pulse rising edge in the vertical interval of the input signal and ends on the trailing edge of the first equalizing Output pulse after the vertical interval. It will therefore be slightly more than 3H lines wide.

No Signal Detect Output

This is a digital output which goes high when either a) loss of input signal or b) the input signal level falls below a predetermined amplitude as set by RLV on pin 2. There will be several horizontal lines delay before the output is initiated.

Burst/Back Porch Output

The start of back porch output is triggered on the trailing edge of normal H sync, and on the rising edge of serration pulses in the vertical interval. The pulse is timed out internally to produce a one-shot output. The pulse width is a function of RSET. This output can be used for d.c. restore functions where the back porch level is a known reference.

Odd/Even Output

Odd-even output is low for even field and high for odd field. The operation of this circuit has been improved for rejecting spurious noise pulses such as those present in VCR signals.

Horizontal Sync Output

This output produces only true H pulses of nominal width 5µs. The leading edge is triggered from the leading edge of the input H sync, with the same prop. delay as the composite sync. The half line pulses present in the input signal during vertical blanking are eliminated with an internal 2H eliminator circuit.

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F.4 Consolidated UCF for All Mother Boards: Net Name Connector

Pin Number FPGA Pin No.

FPGA Pin No

FPGA Pin No

FPGA Pin No

SP3-5M SP3-PCI VIRTEX-4 VIRTEX-5 DAC INTERFACE

"DAC0Pb<0>" #J1-38 G30 H11 J21 R22 "DAC0Pb<1>" #J1-42 H30 G6 H21 M24 "DAC0Pb<2>" #J1-44 J29 F5 G24 N23 "DAC0Pb<3>" #J1-46 J30 F6 H23 N24 "DAC0Pb<4>" #J1-48 K29 E6 H24 P24 "DAC0Pb<5>" #J1-50 L29 F8 J23 P23 "DAC0Pb<6>" #J1-52 L30 F7 K23 R23 "DAC0Pb<7>" #J1-41 E29 F3 C21 L24 "DAC0Pb<8>" #J1-51 B25 H15 D23 K26 "DAC0Pb<9>" #J1-49 A26 G15 C23 L25 "DAC0Pr<0>" #J1-36 M26 G11 J22 P21 "DAC0Pr<1>" #J1-34 M25 H12 K21 N22 "DAC0Pr<2>" #J1-32 L26 G12 K22 N21 "DAC0Pr<3>" #J1-28 L25 H13 L21 M22 "DAC0Pr<4>" #J1-26 K25 G14 N22 M21 "DAC0Pr<5>" #J1-24 J26 G10 N21 T20 "DAC0Pr<6>" #J1-22 J25 H9 M22 R20 "DAC0Pr<7>" #J1-21 E25 M4 E18 H22 "DAC0-Pr<8>" #J1-17 F24 M3 F17 H21 "DAC0Pr<9>" #J1-15 F23 T3 E17 G22 "DAC0Y<0>" #J1-1 H19 K13 D16 J19 "DAC0Y<1>" #J1-3 G20 J13 C17 J20 "DAC0Y<2>" #J1-5 H20 K14 D17 T25 "DAC0Y<3>" #J1-7 G21 J14 D18 P26 "DAC0Y<4>" #J1-2 K18 J12 C24 K20 "DAC0Y<5>" #J1-4 J19 K12 D24 L19 "DAC0Y<6>" #J1-6 K19 K11 E23 L20 "DAC0Y<7>" #J1-8 K20 J10 E24 M19 "DAC0Y<8>" #J1-12 J21 J9 F23 M20 "DAC0Y<9>" #J1-14 G24 G7 F24 N19 "DAC0_BLANK_BAR" #J1-13 G23 J15 D19 G21 "DAC0_CLK" #J1-16 H23 H8 G23 P20 "DAC0_M1" #J1-45 D29 F9 C22 M26 "DAC0_M2" #J1-47 B26 E9 D22 M25 "DAC0_SYNC_BAR" #J1-11 H22 K15 C19 P25 "DAC0_SYNC_T" #J1-18 H24 G8 M21 P19 SYNC SEPERATOR

"HORSYNC_OP" #J1-35 G29 H4 E22 J23 "NOSIG_OP" #J1-23 F25 L3 F18 J21 "ODDEVEN_OP" #J1-33 H26 H3 E21 H24 "VERTSYNCOP" #J1-37 F29 G3 C20 J24 "BBPORTCH_OP" #J1-31 H25 J4 F20 H23 "COMPSYNC_OP" #J1-39 E30 G4 D20 K23 ADC INTERFACE

"ADCAD<1>" #J2-11 M22 AD6 K20 V19 "ADCAD<2>" #J2-7 N21 AC6 L19 W20 "ADCAD<3>" #J2-5 N22 AC5 L20 W19 "ADCAD<4>" #J2-3 P21 AB6 M19 Y20 "ADCAD<5>" #J2-1 P22 AB5 M20 Y18 "ADCAD<6>" #J2-2 V22 AC12 R20 Y10 "ADCAD<7>" #J2-4 U21 AD12 P19 Y11

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Net Name Connector Pin Number

FPGA Pin No.

FPGA Pin No

FPGA Pin No

FPGA Pin No

SP3-5M SP3-PCI VIRTEX-4 VIRTEX-5 "ADCAD<8>" #J2-6 U22 AC13 P20 Y12 "ADCBD<1>" #J2-31 M23 AF9 R24 U21 "ADCBD<2>" #J2-27 M24 AE9 P22 W21 "ADCBD<3>" #J2-25 N23 AF8 R23 Y22 "ADCBD<4>" #J2-23 J22 AE8 T24 Y21 "ADCBD<5>" #J2-21 K21 AE7 T21 AA22 "ADCBD<6>" #J2-17 K22 AF6 U22 T19 "ADCBD<7>" #J2-15 L21 AE6 U21 U20 "ADCBD<8>" #J2-13 M21 AE5 J20 U19 "ADCCD<1>" #J2-22 U24 AC18 W21 AB17 "ADCCD<2>" #J2-28 R24 AD20 V22 AB19 "ADCCD<3>" #J2-34 P24 U3 AA24 AB20 "ADCCD<4>" #J2-46 T27 AD3 V23 AB24 "ADCCD<5>" #J2-52 N29 AE3 U24 AA24 "ADCCD<6>" #J2-51 M29 AB4 L23 T23 "ADCCD<7>" #J2-47 N25 AA3 L24 U24 "ADCCD<8>" #J2-45 N26 Y4 M23 V24 "CLK_VIDEO1" #J2-41 J23 W4 N23 W24 "EXTCLP" #J2-16 R21 AD16 Y21 AA15 "GY" #J2-43 P25 Y3 M24 V23 "INIT" #J2-37 K24 AF11 N24 W23 “MODE0” #J2-35 L23 AE11 P24 T22 “MODE1” #J2-33 L24 AE10 P23 U22

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