Specification of RTRM08 Transceiver Module Easywave I C · Specification Index 1.01 Project No. 7007 RF-Products, Controller RTRM08 Transceiver Module Easw I2C Page 6 Development

SpecificationIndex 1.01

Project No.

7007

RF-Products, Controller RTRM08 Transceiver Module Easw I2C Page 1DevelopmentProduction S. Schreiber 2007-08-24

Specificationof

RTRM08Transceiver Module

Easywave I2C


Project No.

7007


Revision HistoryIndex Releases

0.90 Initial Release.1.00 Section 1 and section 2.1:

Options for the antenna are mentioned now.

Section 2.3:

Some figures have been corrected. The acknowledge bit A- after the final data byte ofa read transfer is labeled with “1“ now (Figure 4, Figure 5, Figure 7, Figure 8).

It is stated now that the current implementation interrupts any receive attempt ofEasywave telegrams while the persistent storage is written (RX_USERDATA0 andRX_USERDATA1 registers).

It is stated that any bit is cleared in the RX_LN_CHXXX registers when ELDAT ships thetransceiver module RTRM08.

1.01 Section 1, section 2.1, and section 3.2:

The upper limit of the power supply's operational range of 5.5 V has been decreased to5.25 V.


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Table of Contents1 General Description...........................................................................................................................42 Functional Description...................................................................................................................... 4

2.1 Pin Definition.............................................................................................................................42.2 Power up and Reset....................................................................................................................52.3 I2C-bus.......................................................................................................................................5

Signal Lines of the I2C-bus........................................................................................................5 Addressing a Slave and Performing Data Transfer.................................................................... 6 Accessing the Transceiver Module.......................................................................................... 12 Initialization on Reset.............................................................................................................. 19 Receiving of Easywave Telegrams.......................................................................................... 19 Learning of Easywave Telegrams............................................................................................ 21 Delete Learned Easywave Telegrams.......................................................................................21 Transmitting of Easywave Telegrams......................................................................................22

3 Electrical Characteristics................................................................................................................. 233.1 Absolute Maximum Ratings.................................................................................................... 233.2 Operating Conditions...............................................................................................................233.3 Characteristics..........................................................................................................................24

4 Mechanical Specification................................................................................................................ 24

FiguresFigure 1 Component side view of the transceiver module................................................................... 4Figure 2 I2C-bus lines and common conditions................................................................................... 6Figure 3 Write transfer using a 7-bit address........................................................................................7Figure 4 Read transfer using a 7-bit address.........................................................................................7Figure 5 Combined write and read transfer using a 7-bit address........................................................ 8Figure 6 Write transfer using a 10-bit address....................................................................................10Figure 7 Read transfer using a 10-bit address.....................................................................................11Figure 8 Combined write and read transfer using a 10-bit address.................................................... 12Figure 9 Writing into registers of the transceiver module.................................................................. 13Figure 10 Reading out registers of the transceiver module................................................................ 13Figure 11 Sequence when receiving Easywave telegrams..................................................................20Figure 12 Sequence when transmitting Easywave telegrams............................................................. 23Figure 13 Drawing of the transceiver module.................................................................................... 26


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1 General DescriptionFeatures of the RTRM08 transceiver module:

– Sends and receives Easywave at 868.3 MHz, FSK modulation.

– Whip antenna. Other options are available on request: coaxial connectors or an antenna via the module'sconnector.

– High output power of +9 dBm (at 5 V power supply) .

– Each module can transmit 32 different Easywave telegrams which have unique serial numbers.

– Up to 32 Easywave transmitters can be taught in the RTRM08 Easywave module. The RTRM08 stores16-bit user data associated with each Easywave transmitter. Persistent storage (EEPROM).

– I2C-bus, 100 kHz clock rate (Standard Mode), slave only.

– Fixed I2C address, which is 1100010 (7-bit, excluding the R/W-bit).

– A separate request output allows to work without any polling.

– Operational range of power supply: 2.1 V to 5.25 V.

– Power down state with low current consumption when being inactive.

– LEDs indicate transmit and receive operation (optional).

– Approval standards EN 300 220-1 V1.3.1 (2000-09) and EN 300 220-3 V1.1.1 (2000-09).

2 Functional Description

2.1 Pin DefinitionPins are numbered as shown in Figure 1.

1 2 3 4 5 6 7 8 9 10 11 12

LED (receive, green)LED (transmit, yellow)

whip antenna

Figure 1 Component side view of the transceiver module


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Pin number Signal name Signal direction Description1 VCC - Power supply (2.1 V ...5.25 V).2 GND - Ground.3 / RESET in Reset. Active low.4 SDA bidirectional (open-drain) I2C serial data I/O.5 SCL bidirectional (open-drain) I2C synchronous serial clock I/O.6 / REQ out (open-drain) Request output. It indicates whether an

Easywave telegram could be received andwhether a received Easywave telegram isover. Active low.

7 - 12 (NC) - Pins are not allowed to connect to any circuit.

There are options for the antenna available, for example, coaxial connectors or an antenna via the module'sconnector. Please contact ELDAT.

2.2 Power up and ResetThe module's / RESET signal is not allowed to be high until the power supply is in the operational range. Themodule is in inactive state subsequently; it can be controlled via the I2C-bus.

The / REQ output of the module goes to (active) low until the module's rx mode is altered.

The module also can be reset at any time independent from its former state by asserting the / RESET signal.

2.3 I2C-busThe SCL and the SDA pin are the I2C-bus as defined in the “THE I2C-BUS SPECIFICATION VERSION 2.1“(January 2000), document order number 9398 393 40011 by Philips.

A short discussion of the I2C-bus follows in this section. If both this specification of the RTRM08 transceivermodule and the referred “THE I2C-BUS SPECIFICATION VERSION 2.1“ document define a specific detail,the specification of the RTRM08 transceiver module has informational characteristics only.

The I2C clock rate of the transceiver module can be up to 100 kHz (Standard Mode).

Signal Lines of the I2C-busThe I2C-bus is a 2-wire bus; it has a bidirectional serial clock line SCL and a bidirectional serial data line SDA.Both SCL and SDA are combined inputs and open-drain outputs. There must be one pullup-resistor on eachof the SCL and the SDA line. The RTRM08 transceiver module I2C PHY does not include these pullup-resistors.

A device connected to a bus can be either a master or a slave. A master device is able to acquire the I2C-busand initiate a transfer from (read) or to (write) a specified slave. The master generates the clock on the SCLline in order to transfer the serial data bits. The slave can slow down the transfer if it can't transmit or receivedata bytes fast enough (clock stretching, see below). The master has to terminate the transfer and releasethe I2C-bus either successfully or due to a fail.

The SDA line is driven by the device which transmits data bits: it is either a master or a slave.

One or more master devices can be connected to the I2C-bus. This specification covers examples with onemaster only, but the transceiver module also works on I2C-busses with more than one master (multi-master).


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Furthermore, one or more slave devices are connected to the I2C-bus, where each slave device must have aunique I2C-address.

An I2C bus can be free and there are start conditions, repeated start conditions, stop conditions, and bittransfers on an I2C-bus (Figure 2).

Both SCL and SDA are high while the I2C bus is free; all of the SCL and SDA outputs are high. (All open-drainoutputs on a line form a wired-AND.)

The start condition S is a falling edge of the SDA line, when the SCL line is (still) high. The SCL line is pulled tolow subsequently. A start condition S is generated only by a master.

The SCL line is low before a bit transfer (subsequent to a start condition or a bit transfer). The transmittingdevice pulls the SDA line low or releases it to high according to the desired data bit first. At next the mastergenerates a rising edge on the SCL line and a falling edge on SCL subsequently. (When SCL is high betweenthe rising and falling edge, SDA must not change its state, because it would generate a start condition or astop condition.) The SCL line is low again after transmitting the bit. The SCL line is always driven by themaster, but the SDA line is driven by the transmitting device (either the master or the slave which wasaddressed before by the master).

A slave can slow down the transfer by pulling the SCL line to low after the falling edge (clock stretching). Themaster has to realize that the slave pulls the SCL line to low. Since the SCL outputs of the master and theslave form a wired-AND, the SCL line will be low until both the master and the slave are able to continue.

The SCL line is low before a stop condition P (subsequent to a bit transfer). The SDA line is pulled to low if itwas not low before. The SCL line is released to high. A rising edge is generated on the SDA linesubsequently; and the I2C-bus is free. A stop condition P is generated only by a master.

A master also can generate a repeated start condition Sr that starts a new transfer after the bus has beenacquired. The SDA line is released to high if it was not high before. The SCL line is released to high. A fallingedge is generated on the SDA line subsequently. A stop condition P and a start condtion S, which aregenerated by a master, can be replaced by a repeated start condition Sr. A master uses a repeated startcondition Sr in order to start a new transfer, but prevents another master device from acquiring the I2C bus.

startcondition

S

SCL

SDA

freebus

data bit

bittransfer

bittransfer

data bit

another bittransfers

stopcondition

P

freebus


repeated startcondition

Sr


Figure 2 I2C-bus lines and common conditions


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Addressing a Slave and Performing Data TransferEach slave, which is connected to the I2C-bus, must have a unique I2C-address. An I2C-address can be either7 bits wide (legacy 7-bit addressing) or 10 bits wide. Slave devices with 7-bit addressing and 10-bitaddressing can be mixed on an I2C-bus, because 10-bit addressing is upwards-compatible.

7-bit addressing

If a master wants to transfer any data to (write) or from (read) a slave which has a 7-bit address, the mastergenerates a start condition S (or a repeated start condition Sr) to acquire the free bus first (Figure 3). At nextthe master transmits one (address-) byte (8 bits with bit transfers). These 8 bits are the 7-bit address (mostsignificant bit at first), followed by one bit R/W, which specifies the desired direction of the transfer. If theR/W-bit is 0, it is a write transfer (the master transmits data bits; the slave receives them). If the R/W-bit is 1,it is a read transfer (the master receives data bits; the slave transmits them).

Each slave has to recognize the start condition S and has to receive the subsequent address-byte. A slavewill compare the received 7-bit address with its own unique address. If the address matches, a slave isaddressed by the master. Other slaves, which are not addressed, will continue waiting for another startcondition S (or a repeated start condition Sr).

With the nineth bit transfer an acknowledge bit A is transferred from the slave to the master (in the oppositedirection to the transfer of the preceding address-byte). The addressed slave has to transfer a lowacknowledge-bit A+ (means acknowledge). If the master receives a low acknowledge-bit A+, communicationwill proceed; when the acknowledge-bit is high (A-), the master has to generate a stop condition P, and theI2C-bus enters its free state.

free S address A+ data byteRW A+ data byte A P free7-bit 8-bit0 8-bit0 0 0/1

addressing a slave write transfer

from master to slave

from slave to master

S start conditionRW R/W direction bitA+ acknowledge-bit (SDA line is low)A acknowledge-bit (SDA line is low or high)P stop condition

Figure 3 Write transfer using a 7-bit address


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free S address A+ data byteRW A+ data byte A- P free7-bit 8-bit1 8-bit0 0 1

addressing a slave read transfer



S start conditionRW R/W direction bitA+ acknowledge-bit (SDA line is low)A- acknowledge-bit (SDA line is high)P stop condition

Figure 4 Read transfer using a 7-bit address

If it is a write transfer, the master continues transmitting the data bytes which the master wants to write intothe addressed slave (Figure 3). If it is a read transfer, the addressed slave will transmit the data bytessynchronous to the master according to the serial clock which the master generates (Figure 4). If addressingof a slave went successfully, at least one data byte has to be transferred. The master isn't allowed togenerate a stop condition immediately after transferring the desired slave address.

Data bytes (8 bits) are transferred with their most significant bit at first. After each data byte an acknowledge-bit A is transferred from that device, which received the preceding data byte to the device, which transmittedthe data byte before: the acknowledge-bit is transferred in the opposite direction to the preceding transfer ofthe data byte.

If the master receives a low acknowledge-bit A+ (means acknowledge) while a write transfer, the master cancontinue writing into the slave. If the master receives a high acknowledge-bit A- while a write transfer, it willterminate the transfer with a stop condition P.

If the master transmits a low acknowledge-bit A+ to the slave (means acknowledge) while a read transfer, themaster has to continue reading the slave's data. If the master transmits a high acknowledge-bit A- to theslave due to any reason while a read transfer, the master has to terminate the transfer with a stop condition Psubsequently.

Each transfer is terminated by the master, which generates a stop condition P. The master also canterminate a transfer with a repeated start condition Sr which addresses a slave again and initiates a newtransfer. Subsequent to a repeated start condition Sr the sequence is just as after a start condition S.


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Sr address A+ data byteRW A+ data byte A- P free7-bit 8-bit1 8-bit0 0 1

addressing a slave read transfer



S start conditionSr repeated start conditionRW R/W direction bitA+ acknowledge-bit (SDA line is low)A- acknowledge-bit (SDA line is high)A acknowledge-bit (SDA line is low or high)P stop condition

free S address A+ data byteRW A+ data byte A7-bit 8-bit0 8-bit0 0 0/1

addressing a slave write transfer

Figure 5 Combined write and read transfer using a 7-bit address

Often a master wants to perform a read transfer immediately after a write transfer (Figure 5). The master canuse a repeated start condition Sr in place of a separated stop condition P and a start condition S after thewrite transfer and before the read transfer.

Some 7-bit addresses are reserved and are not allowed to be used as slave-address. The 7-bit addresses11110xx (binary) are not allowed to be used as 7-bit slave address, because they initiate 10-bit addressing,see below. (Please refer to Philips' I2C specification for further information about reserved addresses.)

10-bit addressing

If a master wants to transfer any data to (write) or from (read) a slave that has a 10-bit address, the mastergenerates a start condition S (or a repeated start condition Sr) to acquire the free bus first (Figure 6). At nextthe master transmits the bit pattern 11110 and the two most significant bits of the 10-bit address (mostsignificant bit at first), which are followed by one R/W-bit. The R/W-bit must be always 0 (means writetransfer) for compatibility with 7-bit addressing, even though there is a read transfer desired. The mentionedbit pattern, 2 bits of the address, and the R/W-bit are 8 data bits (one byte), which the master transmits.

Each slave has to recognize the start condition S and has to receive the subsequent byte. A slave will checkthe bit pattern 11110, compare the received 2-bit part of the address with its own unique address, and checkthe R/W-bit. If the two address bits match and R/W is 0, a slave continues receiving the addressing of themaster. Other slaves, which are not addressed, will continue waiting for another start condition S (or arepeated start condition Sr) including all slaves which have a 7-bit address. Since the 7-bit address 11110xxis reserved, not any 7-bit slave has a matching address.

With the nineth bit transfer an acknowledge bit A is transferred from a slave to the master (in the oppositedirection to the transfer of the preceding byte). Any addressed slave has to transfer a low acknowledge-bit A+(means acknowledge). If the master receives a low acknowledge-bit A+, communication will proceed; whenthe acknowledge-bit is high (A-), the master has to generate a stop condition P, and the I2C-bus enters itsfree state.


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At next the master generates a repeated start condition Sr and transmits the eight remaining least significantbits of the 10-bit address (most significant bit at first).

Any slave which was addressed by the two most significant address bits will compare the received eight leastsignificant address bits with its own unique address. If the address bits match, a slave is addressed by themaster. Other slaves, which are not addressed, will continue waiting for another start condition S (or arepeated start condition Sr).

With the nineth bit transfer an acknowledge bit A is transferred from a slave to the master again (in theopposite direction to the transfer of the preceding byte). The addressed slave has to transfer a lowacknowledge-bit A+ (means acknowledge). If the master receives a low acknowledge-bit A+, communicationwill proceed; when the acknowledge-bit is high (A-), the master has to generate a stop condition P, and theI2C-bus enters its free state.

If a write transfer is desired, the master continues transmitting the data bytes and will terminate the transferexactly as it is described on 7-bit addressing (Figure 6).

P freedata byte A+ data byte A

11110 Sr address A+8-bit 0

addressing a slave(low part of address)



S start conditionSr repeated start conditionRW R/W direction bitA+ acknowledge-bit (SDA line is low)A acknowledge-bit (SDA line is low or high)P stop condition

free S address A+RW2-bit 0 0

addressing a slave(high part of address)

8-bit 8-bit0 0/1

write transfer

Figure 6 Write transfer using a 10-bit address

If a read transfer is desired, the master generates a repeated start condition Sr after it has addressed a slave(10-bit address) successfully (Figure 7). At next the master transmits the bit pattern 11110, the two mostsignificant bits of the 10-bit address (most significant bit at first), which are followed by one R/W-bit again.The R/W-bit must be 1 now (means read transfer).

The slave which was addressed before the repeated start condition Sr (but not any other slave) will check thebit pattern 11110, compare the received 2-bit part of the address with its own unique address, and check theR/W-bit (must be 1) again. If each bit matches, the considered slave is addressed by the master for a readtransfer. Other slaves, which are not addressed, will continue waiting for another start condition S (or arepeated start condition Sr).

With the nineth bit transfer an acknowledge bit A is transferred again from a slave to the master (in the


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opposite direction to the transfer of the preceding byte). The addressed slave has to transfer a lowacknowledge-bit A+ (means acknowledge). If the master receives a low acknowledge-bit A+, communicationwill proceed; when the acknowledge-bit is high (A-), the master has to generate a stop condition P, and theI2C-bus enters its free state.

The master receives the data bytes from the slave at next and will terminate the transfer exactly as it isdescribed on 7-bit addressing.

11110Sr address A+RW data byte A+ data byte A- P free





S start conditionSr repeated start conditionRW R/W direction bitA+ acknowledge-bit (SDA line is low)A- acknowledge-bit (SDA line is high)P stop condition



2-bit 1 0

addressing the slave for read transfer (high part of address)

8-bit 8-bit0 1

read transfer

Figure 7 Read transfer using a 10-bit address

Often a master wants to perform a read transfer immediately after a write transfer (Figure 8). The master canalso address a slave (10-bit addressing) for a read transfer immediately after a write transfer was performed.


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11110Sr address A+RW data byte A+ data byte A- P free





S start conditionSr repeated start conditionRW R/W direction bitA+ acknowledge-bit (SDA line is low)A- acknowledge-bit (SDA line is high)A acknowledge-bit (SDA line is low or high)P stop condition



2-bit 1 0

addressing the slave for read transfer (high part of address)

8-bit 8-bit0 1

read transfer

data byte A+ data byte A8-bit 8-bit0 0/1

write transfer

Figure 8 Combined write and read transfer using a 10-bit address

Accessing the Transceiver ModuleThe transceiver module is a slave and has a fixed I2C address (7-bit), which is 1100010 (binary, excludingthe R/W-bit). Other fixed I2C addresses (7-bit or 10-bit) are available on request.

The module holds all information in registers which can be written or read via the I2C-interface. Each registeris 8 bits wide (one byte) and has a specific register address. The register address also is 8 bits wide.

The module maintains a register address pointer, which contains the register address of the register that iswritten or read at next.

When a master does a write transfer to the transceiver module, the module takes the first data byte of thetransfer as desired register address: it initializes its register address pointer with the transferred data byte(Figure 9). Each subsequently transferred data byte is written into the register which the current registeraddress pointer specifies. The register address pointer is incremented by one after each write, so the nexttransferred data byte is written into the next register.

When a master does a read transfer from the transceiver module, each data byte is read out of the register


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which the current register address pointer specifies (Figure 10). The register address pointer is incrementedby one after each read, so the next transferred data byte is read out of the next register.

...data byte data bytefree slave address data byte data byte free

addressing the module for write

transferwrite transfers

register address

a

data for register with the register address

a


a+1


a+2

...

from master to module

Figure 9 Writing into registers of the transceiver module

The master can specify a register address with a write transfer of one data byte only: it is the registeraddress. A subsequent read transfer will read out data; it will start with the specified register address (Figure10).

data byte ...data byte data byte

free slave address data byte

data byte free

addressing the module for write

transfer

write transfer

register address

a

data from register with the register address

a+1


a+2


a+3

...slave address

read transfersaddressing the module for read

transfer


a

from master to module

from module to master

Figure 10 Reading out registers of the transceiver module


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After a reset the register address pointer is initialized with 0x00 (specifies the RX_MODE register, see below).

If the register address pointer points beyond the highest defined register address, behavior on read and writeattempts is undetermined.

The transceiver module is always able to process start conditions and I2C addresses on the I2C bus, eventhough it processes any Easywave telegram internally. If the transceiver module is busy, it will slow down orstop the transfer on the I2C-bus for short time intervals after it has been addressed by a master.

The transceiver module's registers are configured as follows:

RegisterAddress

Register Name Description of Register

0x00 RX_MODE Rx Mode register. The RX_MODE register controls the mode of thetransceiver module as long as it does not transmit an Easywave telegram.

The RX_MODE register is a read-write register; a write specifies the desiredRx mode of the module; a read supplies the current Rx mode of themodule.

The module enters the desired Rx mode immediately after the RX_MODEregister has been written.

One of the following values can be read or written:• 0x00 (PWD_RST)

The module is in power down state after a reset. The module'stransceiver is switched off.The / REQ output is asserted.(Please refer to “Initialization on Reset“ on page 19.)

• 0x01 (PWD)The module is in power down state. The module's transceiver isswitched off.The / REQ output is not asserted.(Please refer to “Initialization on Reset“ on page 19.)

• 0x02 (RX_RQ)The module is in Receive Mode. When the module enters the ReceiveMode, it switches on its transceiver and tries receiving Easywavetelegrams.The / REQ output indicates whether the module has received Easywavetelegrams, which can be read out via the I2C-bus subsequently.The / REQ output also indicates whether Easywave telegrams are over.When the module terminates the Receive Mode (because anothervalue than RX_RQ is written into the RX_MODE register), the moduleswitches its transceiver on or off according to the desired mode.(Please refer to “Receiving of Easywave Telegrams“ on page 19.)

• 0x03 (RX_PL)The module is in Receive Mode just as with the RX_RQ mode value, butthe / REQ output always remains inactive. Polling of the RX_STATUSregister is the only way of determining whether the module hasreceived Easywave telegrams, which can be read out via the I2C-bus.When the module terminates the Receive Mode (because anothervalue than RX_PL is written into the RX_MODE register), the moduleswitches its transceiver on or off according to the desired mode.(Please refer to “Receiving of Easywave Telegrams“ on page 19.)


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RegisterAddress


• 0x04 (LN_RQ)The module is in Learn Mode. When the module enters the LearnMode, it switches on its transceiver and tries receiving Easywavetelegrams. The module learns the first Easywave telegram which itreceives.The / REQ output indicates whether the module has received andlearned an Easywave telegram.When the module terminates the Learn Mode (because another valuethan LN_RQ is written into the RX_MODE register), the module switchesits transceiver on or off according to the desired mode.(Please refer to “Learning of Easywave Telegrams“ on page 21.)

• 0x05 (LN_PL)The module is in Learn Mode just as with the LN_RQ mode value, butthe / REQ output always remains inactive. Polling of the RX_STATUSregister is the only way of determining whether the module hasreceived and learned an Easywave telegram.When the module terminates the Learn Mode (because another valuethan LN_PL is written into the RX_MODE register), the module switchesits transceiver on or off according to the desired mode.(Please refer to “Learning of Easywave Telegrams“ on page 21.)

• 0x06 (DELLN)The module's transceiver is switched off. The module deletes a learnedEasywave telegram.The / REQ output is not asserted.(Please refer to “Delete Learned Easywave Telegrams“ on page 22.)

0x01 RX_STATUS Rx Status register. This register indicates received and learned Easywavetelegrams while being in Rx mode or Learn mode.

The RX_STATUS register is a read-only register, a write to the register hasnot any effect.• Bit 7: (RX_TEL_CHANGED)

The RX_TEL_CHANGED bit is set to 1 if the received Easywavetelegram changes while being in Receive Mode: An Easywave telegramhas received or an Easywave telegram has been received which differsfrom the preceding one or there is not any further valid Easywavetelegram received.If the RX_TEL_CHANGED bit is set from 0 to 1, the transceiver modulesets the RX_CHANNEL and RX_BUTTON registers, and theRX_TEL_VALID bit in this Rx Status register according to the receivedEasywave telegram.While the RX_TEL_CHANGED bit is 1, the RX_CHANNEL andRX_BUTTON registers and the RX_TEL_VALID bit in this Rx Statusregister won't change their contents even if another Easywave telegramis received. Reading the RX_ACK register clears the RX_TEL_CHANGED bit.(Please refer to “Receiving of Easywave Telegrams“ on page 19.)


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RegisterAddress


• Bit 6: (RX_TEL_VALID)The RX_TEL_VALID bit is set or cleared if the received Easywavetelegram changes while being in Receive Mode. If an Easywavetelegram has been recived which differs from the preceding one, theRX_TEL_VALID bit is set to 1. If there is not any further validEasywave telegram received, the RX_TEL_VALID bit is set to 0.The RX_TEL_VALID bit is used together with the RX_TEL_CHANGEDbit. (Please refer to “Receiving of Easywave Telegrams“ on page 19.)

0x02 RX_CHANNEL Rx Channel register. It specifies the channel number (0...31) whilereceiving or learning of an Easywave telegram, or while deleting of alearned Easywave telegram.The RX_CHANNEL register changes its content upon receiving of anEasywave telegram. The RX_CHANNEL register also specifies what channel's user data theRX_USERDATA0 and RX_USERDATA1 registers map.

The RX_CHANNEL register is a read-write register.

(Please refer to “Receiving of Easywave Telegrams“ on page 19,“Learning of Easywave Telegrams“ on page 21, and “Delete LearnedEasywave Telegrams“ on page 22.)

0x03 RX_BUTTON Rx Button register. It specifies the button number while receiving orlearning of an Easywave telegram.

The RX_CHANNEL register is a read-write register; a write to theRX_CHANNEL register modifies the register's content, but has not any othereffect.

One of the following values can be read or written:

• 0x00 Easywave Button A (“On“ or “Up“);

• 0x01 Easywave Button B (“Off“ or “Down“);

• 0x02 Easywave Button C (“Stop“);

• 0x03 Easywave Button D (“Stop“)

(Please refer to “Receiving of Easywave Telegrams“ on page 19,“Learning of Easywave Telegrams“ on page 21, and “Delete LearnedEasywave Telegrams“ on page 22.)

0x04 RX_USERDATA0 Rx User Data Byte#0 register. The RX_USERDATA0 register maps anopaque user data byte here which the transceiver module storesassociated with each channel.

The I2C master can store some data here. Since the RX_CHANNEL registercontains the channel number of a received Easywave telegram, theRX_USERDATA0 register automatically maps the user data byte valuewhich is associated with the received Easywave telegram.

The RX_USERDATA0 register is a read-write register.

The transceiver module stores the user data bytes in persistent storage.

Note that the current implementation interrupts any receive attempts ofEasywave telegrams while the persistent storage is written.


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RegisterAddress


0x05 RX_USERDATA1 Rx User Data Byte#1 register.

It works just as the RX_USERDATA0 register, but holds another opaqueuser data byte.

0x06 RX_ACK Acknowledges a change of received Easywave telegrams while being inReceive mode or Learn mode.

A read access to the RX_ACK register clears the RX_TEL_CHANGED bit inthe RX_STATUS register. (Please refer to “Receiving of EasywaveTelegrams“ on page 19.)

A read access to the RX_ACK register supplies 0x00.

A write access to the RX_ACK register has not any effect.

0x10 TX_STATUS Tx Status register. This register indicates transmission of Easywavetelegrams.

The TX_STATUS register is a read-only register, a write to the register hasnot any effect.

• Bit 7: (TX_TRANSMIT)The TX_TRANSMIT bit is set to 1 if the transceiver module transmitsEasywave telegrams. (Please refer to “Transmitting of EasywaveTelegrams“ on page 22.)

0x11 TX_CHANNEL Tx Channel register. It specifies the channel number (0...31) of anEasywave telegram, which the transceiver module should transmit.

The TX_CHANNEL register is a read-write register.

(Please refer to “Transmitting of Easywave Telegrams“ on page 22.)0x12 TX_BUTTON Tx Button register. It specifies the button number of an Easywave

telegram, which the transceiver module should transmit.

The TX_CHANNEL register is a read-write register.

One of the following values can be read or written:

• 0x00 Easywave Button A (“On“ or “Up“);

• 0x01 Easywave Button B (“Off“ or “Down“);

• 0x02 Easywave Button C (“Stop“);

• 0x03 Easywave Button D (“Stop“)

(Please refer to “Transmitting of Easywave Telegrams“ on page 22.)0x13 TX_ACK Acknowledges an Easywave telegram which the transceiver module

should transmit.

A write access to the TX_ACK initiates transmitting of an Easywavetelegram with the channel of the TX_CHANNEL register and the buttonnumber of the TX_BUTTON register. (Please refer to “Transmitting ofEasywave Telegrams“ on page 22.)

A read access to the TX_ACK register supplies 0x00 and has not anyeffect.


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RegisterAddress


0x20 RX_LN_CH0_7 A bit mask that indicates whether a channel has learned an Easywavetelegram (receive).

A bit for the specific channel is set to 1 upon learning an Easywavetelegram (LN_RQ and LN_PL value of the RX_MODE register, please referto “Learning of Easywave Telegrams“ on page 21.)

A specific bit is cleared upon deletion of a learned Easywave telegram(DELLN value of the RX_MODE register, please refer to “Delete LearnedEasywave Telegrams“ on page 22.)

Any bit is cleared when ELDAT ships the transceiver module RTRM08.

• Bit 0: Channel 0 (channel number of the RX_CHANNEL register);







• Bit 7: Channel 7 (channel number of the RX_CHANNEL register)

0x21 RX_LN_CH8_15 Just as the RX_LN_CH0_7 register, but for channels 8 to 15.



















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RegisterAddress











Initialization on ResetAfter a reset the transceiver module is in power down state, and the transceiver is switched off.The / REQ output is low.

The RX_MODE register is set to the PWD_RST value.

The I2C master can set the RX_MODE register to the PWD value; the / REQ output goes high then.

The PWD_RST mode is intended to recognize an occurred reset (due to a malfunction or a power fail) by theasserted / REQ output.

Receiving of Easywave TelegramsThe RX_MODE register must be set to the RX_RQ value or the RX_PL value (Recevive Mode). If the RX_MODEregister is RX_PL, the / REQ output is always inactive (high). If the RX_MODE register is set to RX_RQ, the/ REQ output works as described in the next paragraphs.

The transceiver module maintains learned telegrams. Each learned telegram is associated with a channel.There are 32 channels. A channel can store one learned Easywave telegram (the channel is used) or achannel stores not any learned Easywave telegram (the channel is unused).

There is a bit mask in the RX_LN_CH0_7, RX_LN_CH8_15, RX_LN_CH16_23, and RX_LN_CH24_31registers which indicates usage of each channel (a channel is used or unused).

The transceiver module ignores a received Easywave telegram if it isn't equal to any of the learned Easywavetelegrams.

The / REQ output is high at first, the RX_TEL_CHANGED-bit in the RX_STATUS register is 0 (Figure 11).

The module switches on its transceiver and tries receiving some Easywave telegrams. When the modulereceives an Easywave telegram, it does the following (Figure 11):

• The / REQ output goes low, and the RX_TEL_CHANGED-bit in the RX_STATUS register is set to 1 upon oneof the following conditions:

• The module has started receiving an Easywave telegram which is a learned one (after a pause orafter a preceding Easywave telegram). The RX_TEL_VALID-bit in the RX_STATUS register is setto 1; it indicates the begin of a new Easywave telegram. (For example the user has pushed abutton of a transmitter.) The RX_CHANNEL register and the RX_BUTTON register contain thechannel number (of the learned Easywave telegram) and the button number. The RX_USERDATA0


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and RX_USERDATA1 registers contain the opaque user data which is associated with the channelnumber.

• The module does not receive further valid learned Easywave telegrams. The RX_TEL_VALID-bitin the RX_STATUS register is set to 0 now; it indicates the end of a learned Easywave telegram.(For example, the user has released the button of a transmitter.)

• The I2C master can read out the channel number, the button number, and the opaque user data if theRX_TEL_VALID-bit in the RX_STATUS register is 1.While the RX_TEL_CHANGED bit is 1, the transceiver module won't change the contents of theRX_CHANNEL and RX_BUTTON registers and of the RX_TEL_VALID bit in the RX_STATUS register even ifanother Easywave telegram is received.

• If the I2C master reads the RX_ACK register, the transceiver module drops the channel number and thebutton number of the received telegram. The RX_ACK register also can be read in a single read transferwith the other registers mentioned above. If one of the above conditions has occurred meanwhile, the/ REQ output remains low, and the RX_TEL_CHANGED-bit in the RX_STATUS register remains 1. Otherwisethe transceiver module clears the RX_TEL_CHANGED-bit in the RX_STATUS register and the / REQ outputgoes high. (For example, a user holds down the button of a transmitter or the user does not push anybutton.) If the / REQ output goes high, the transceiver module guarantees that it happens before the I2Cread transfer from the RX_ACK register on the I2C-bus terminates.

The green LED blinks as long as the transceiver module receives any Easywave telegram. (The LED isdrawn on Figure 1 on page 4).

read data:

end of telegr.

read data: begin telegr.

#3


#2

read data:

end of telegr.

receive telegrams #1


#1

RXontransceiver

/REQ output

highlow

RX_TEL_-CHANGED

10

I2C-bus



RXon

RX_TEL_-VALID

10

RXon

Figure 11 Sequence when receiving Easywave telegrams

A master should perfom the following steps if it wants to receive Easywave telegrams subsequent it has setthe RX_MODE-register to the RX_RQ or RX_PL value:

• Wait until the / REQ output goes low (RX_RQ only) or wait until the RX_TEL_CHANGED-bit in the


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RX_STATUS register is 1. Check the RX_MODE register. If the RX_MODE register is PWD_RST, set theRX_MODE register to RX_RQ or RX_PL again, and start with the first bullet.

• Read the RX_TEL_VALID-bit in the RX_STATUS register, the channel number, the button number, and theopaque user data from the RX_CHANNEL, RX_BUTTON, RX_USERDATA0, and RX_USERDATA1 registers ifnecessary.

• Read the RX_ACK register.

• Start with the first step.

Note that the current implementation interrupts any receive attempts of Easywave telegrams while theRX_USERDATA0 and RX_USERDATA1 registers are written.

Learning of Easywave TelegramsThe RX_MODE register must be set to the LN_RQ value or the LN_PL value (Learn Mode). If the RX_MODEregister is LN_PL, the / REQ output is always inactive (high). If the RX_MODE register is set to LN_RQ, the/ REQ output works as described in the next paragraphs.

The Learn Mode works just as the receive mode except that the transceiver module does not modify theRX_CHANNEL register. The I2C master has to set this register appropriately and the transceiver modulelearns the first Easywave telegram which it receives after entering the Learn Mode.

The transceiver module ignores any received Easywave telegram while being in Learn Mode if it is one whichhas been already learned before.

After the transceiver module has learned an Easywave telegram, it ignores further received Easywavetelegrams.

The transceiver module sets the appropriate bit in the bit mask of the RX_LN_CH0_7, RX_LN_CH8_15,RX_LN_CH16_23, and RX_LN_CH24_31 registers to indicate that the channel is used now. If the channelhas been used before, the Easywave telegram which has been learned before will be overwritten.

The green LED blinks as long as the transceiver module receives any Easywave telegram. (The LED isdrawn on Figure 1 on page 4).

A master should perfom the following steps if it wants to learn an Easywave telegram:

• Set the RX_MODE register to the PWD or PWD_RST value. This prevents the transceiver module frommodifying the RX_CHANNEL register.

• Set the RX_CHANNEL register appropriately. The master can determine an unused channel by reading thebit mask from the RX_LN_CH0_7, RX_LN_CH8_15, RX_LN_CH16_23, and RX_LN_CH24_31 registers.The master also can write some user data into the RX_USERDATA0 and RX_USERDATA1 registers.

• Set the RX_MODE register to the LN_RQ or LN_PL value.

• Wait until the / REQ output goes low (LN_RQ only) or wait until the RX_TEL_CHANGED-bit in theRX_STATUS register is 1. Check the RX_MODE register. If the RX_MODE register is PWD_RST, start with thefirst bullet.

• Read the RX_TEL_VALID-bit in the RX_STATUS register, the channel number, the button number fromthe RX_CHANNEL and RX_BUTTON registers if necessary.

• Read the RX_ACK register.

• If the RX_TEL_VALID-bit in the RX_STATUS register was 1 above, the transceiver module has learned anEasywave telegram. If the RX_TEL_VALID-bit in the RX_STATUS register was 0, the master shouldcontinue waiting for an Easywave telegram (fourth bullet).

• The master can write some user data into the RX_USERDATA0, and RX_USERDATA1 registers again ifdesired.


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The master can abort the procedure before an Easywave telegram is learned by setting the RX_MODEregister to any value unequal to the LN_RQ or LN_PL value.

Delete Learned Easywave TelegramsThe RX_MODE register must be set to the DELLN value. The / REQ output is always inactive (high).

When the DELLN value is written into RX_MODE register, the transceiver module immediately deletes thelearned Easywave telegram of the channel which is specified by the RX_CHANNEL register.

The transceiver module clears the appropriate bit in the bit mask of the RX_LN_CH0_7, RX_LN_CH8_15,RX_LN_CH16_23, and RX_LN_CH24_31 registers to indicate that the channel is no longer used. If thechannel was not used before, the entire procedure described in this paragraph has not any effect.

A master should perfom the following steps if it wants to delete a learned Easywave telegram:

• Set the RX_MODE register to the PWD or PWD_RST value. This prevents the transceiver module frommodifying the RX_CHANNEL register.

• Set the RX_CHANNEL register appropriately. The master can determine an used channel by reading the bitmask from the RX_LN_CH0_7, RX_LN_CH8_15, RX_LN_CH16_23, and RX_LN_CH24_31 registers.

• Set the RX_MODE register to the DELLN value.

Transmitting of Easywave TelegramsThe transceiver module has 32 built-in Easywave telegrams which it can transmit.

A write access to the TX_ACK register initiates transmitting of an Easywave telegram with the channel of theTX_CHANNEL register and the button number of the TX_BUTTON register. The TX_ACK register also can bewritten in a single write transfer with the other mentioned registers. The transceiver module does thefollowing:

• The transceiver module switches its transceiver on and transmits a fixed count of Easywave telegramsregardless of the content of the RX_MODE register. The / REQ output and the status bits in the RX_STATUSregister remain on their state. As long as the transceiver transmits, the TX_TRANSMIT-bit in theTX_STATUS register is 1. While the transceiver transmits, further writes into the TX_ACK register have notany effect. The master has to check the TX_TRANSMIT-bit in the TX_STATUS register whether it caninitiate a desired transmission of a further Easywave telegram.

• When the transceiver has finished transmitting of telegrams, it switches its transceiver on (receive) or offaccording to the RX_MODE register and continues operation as specified by the RX_MODE register. TheTX_TRANSMIT-bit in the TX_STATUS register is 0 now.

The yellow LED lights as long as the transceiver transmits. (The LED is drawn on Figure 1 on page 4).


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write data: telegr.

#2

transmit telegrams #2

transmit telegrams #1

write data: telegr.

#1

transceiver

TX_TRANSMIT10

I2C-bus

Figure 12 Sequence when transmitting Easywave telegrams

A master should perfom the following steps if it wants to transmit Easywave telegrams:

• Check the TX_TRANSMIT-bit in the TX_STATUS register and wait until it is cleared.

• Write the desired channel number and button number into the TX_CHANNEL and TX_BUTTON registers.

• Write any value into the TX_ACK register.

• Start with the first step for the next Easywave telegram.

3 Electrical Characteristics

3.1 Absolute Maximum RatingsAbsolute Maximum Ratings Min Max Units

Voltage VCC on VCC pin with respect to GND -0.3 5.8 V

Voltage on any pin with respect to GND -0.3 VCC + 0.3 V

Input clamp current and output clamp current - +/-20 mAMaximum output current by any output - +/-25 mAAmbient temperature under bias -40 85 °CStorage temperature -40 125 °C

3.2 Operating ConditionsOperating Conditions Min Max Units Conditions

Supply voltage VCC 2.1 5.25 V


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Operating Conditions Min Max Units ConditionsInput low voltage 0 0.8 V 4.5 V <= VCC

<= 5.25 V0 0.2 • VCC V for entire VCC

rangeInput high voltage 2.0 VCC V 4.5 V <= VCC

<= 5.25 V0.8 • VCC VCC V for entire VCC

range

I2C start condition setup time (time between SCL hasbecome high and the falling edge on SDA)

4.7 - µs

I2C start condition hold time (time between the falling edgeof SDA and SCL can alter its state)

4.0 - µs

I2C stop condition setup time (time between SCL hasbecome high and the rising edge on SDA)

4.7 - µs

I2C stop condition hold time (time between the rising edgeof SDA and SCL can alter its state)

4.0 - µs

I2C data input setup time (time between SDA has changedits state and the rising edge on SCL)

250 - ns

I2C Data input hold time (time between the falling edge ofSCL and SDA changes its state)

0 - ns

I2C SCL high time (time between rising and falling edge ofSCL)

4.0 - µs

I2C SCL low time (time between falling and rising edge ofSCL)

4.7 - µs

Ambient temperature -20 70 °C

3.3 CharacteristicsCharacteristics Min Typ Max Units Conditions

Supply current while transmit operation - 16.9 mA VCC = 3 V

- 25.5 mA VCC = 5 V

Supply current while transmit operationif LEDs are not equipped

- 13.9 mA VCC = 3 V

- 17.3 mA VCC = 5 V

Supply current while receive operation - 14.0 mA VCC = 3 V

- 20.4 mA VCC = 5 V

Supply current while receive operationif LEDs are not equipped

- 11.0 mA VCC = 3 V

- 12.2 mA VCC = 5 V


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Characteristics Min Typ Max Units ConditionsSupply current while powered down - 2.2 µA 25°C,

VCC = 3 V

- 3.4 µA 25°C,VCC = 5 V

- 7.5 µA 85°C,VCC = 3 V

- 10.8 µA 85°C,VCC = 5 V

Supply current while powered down when a startcondition and an I2C-address is on the I2C-bus

- 1.0 mA VCC = 3 V

- 1.7 mA VCC = 5 V

Frequency of carrier 868.3 MHz +/- 50 kHzOutput power (whip antenna) +2

+5

dBm

dBm

VCC = 2.1 V

VCC = 3 V

+9 dBm VCC = 5 V

Receiver sensitivity (whip antenna) -105 dBmApproval standards EN 300 220-1 V1.3.1 (2000-09)

EN 300 220-3 V1.1.1 (2000-09)Use thetransceivermodule withthe suppliedantenna.

4 Mechanical SpecificationPlease refer to Figure 13.


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2.54

30.48

39

17.9

6

21.7

61.6

3.5 max

equipped components

Figure 13 Drawing of the transceiver module

Documents

Specification of RTRM08 Transceiver Module Easywave I C · Specification Index 1.01 Project No. 7007 RF-Products, Controller RTRM08 Transceiver Module Easw I2C Page 6 Development