SpW-10X Router ASICTesting and Performance

Steve Parkes, Chris McClements, Space Technology Centre, University of Dundee

Gerald Kempf, Christian Gleiss,Austrian Aerospace

Stephan Fischer, EADS Astrium GmbHPierre Fabry, ESA

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Contents

SpW-10X Overview Team Testing Performance Availability and Support

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33

SpW-10X

SpW-10X Overview

RoutingSwitch

SpW Port 1

SpW Port 2

SpW Port 3

SpW Port 4

SpW Port 5

SpW Port 6

SpW Port 7

SpW Port 8

Time-CodeInterface

ConfigurationPort 0

RoutingTable

Router Features

Single chip SpaceWire router– Includes LVDS drivers and receivers

Path and logical addressing Group adaptive routing Priority arbitration Start on Request Disable on Silence Watchdog timers

pp44p4

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Team ESA

– Funding and Management

University of Dundee– Design and Testing

Austrian Aerospace – Independent VHDL Test Bench– Transfer to ASIC technology

Astrium GmbH– Functional Testing

Atmel– ASIC Manufacture

STAR-Dundee– Support and Test Equipment

Pre ASIC Implementation Testing

VHDL test bench for initial testing by UoD Router IP in STAR-Dundee devices

– Widely used by many organisations.

Independent test bench by AAE– Extensive tests– Identified several issues with the initial VHDL code.

SpW-10X implemented in Xilinx FPGA– Design kept as close as possible to final ASIC design.– SpW-10X FPGA extensively tested by Astrium GmbH.

SpW-10X FPGA mezzanine board SpW-10X ASIC mezzanine board Testing with SpaceWire Conformance Tester

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Post ASIC Implementation Testing

Functional validation by EADS Astrium, Performance testing by University of Dundee, Characterisation by Austrian Aerospace.

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SpW-10X Verification

VHDL Testbench with self-checking scenarios

RTL and Netlist (FPGA and ASIC) verified with the test bench

Code coverage checked for RTL simulations Analysis of requirements which were not

possible to simulate Timing of ASIC verified with static timing

analysis

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SpW-10X Verification Results

All functions checked – No errors Simulation and analysis used for verification FPGA and ASIC netlist verification Showed implementation correct

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SpW-10X Validation Results

Validation covered all requirements of the SpW Router Specification

All tests passed

Two clarifications of Router Specification– Path addressing with different priority levels not required

– Exact value for the Output Port Timeout Interval

ASIC Validation was performed successfully– Atmel LVDS I/O cells disable rather than tristate

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SpW-10X Network Testing

Extensive testing of the SpW-10X ASIC In various network configurations No anomalies found in ASIC device

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SpW-10X FPGA Testing

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SpW-10X ASIC Testing

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SpW-10X ASIC Testing

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Performance

SpW data rate configurable up to 200Mbps Single supply voltage of 3.3V (3.0 to 3.6V) Temperature:

– Operational ambient temperature -55°C to +125°C– Maximum junction temperature +175°C– Maximum lead temperature (soldering 10 sec) +300°C– Storage temperature -65°C to +150°C

Radiation– Total dose 300Krad(Si)– No latchup up to 70 MeV/mg/cm2

– Package MQFP 196 with 25 mil pin spacing

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Performance

Power consumption (max):– Static Pst: 1W– OFF condition Poff: 1.6W– Total operational all SpW IF active Pop:

3.7W @ 200Mbps, 3.0W @ 100Mbps, 2.4W @ 10Mbps– Deactivated (Clk and LVDS buffer) SpW link: reduction of

power by (Pop - Poff) × 0.1 + 0.06; E.g. with two SpW links deactivated operating at 200Mbps the power consumption is 3.16W

– Data flow has very little influence on power consumption– For lower supply voltage (<3.6V):

resistive model can be used, e.g. 69.4% of power at 3.0V

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Availability and Support

Available now as engineering samples– Atmel AT7910E

2Q09 Flight parts

Front-line support from Atmel– www.atmel.com

Technical support from STAR-Dundee– www.star-dundee.com

Extensive user manual available– Includes schematic and PCB layout info

Evaluation kit from STAR-Dundee

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SpW-10X Evaluation Kit

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SpW-10X Evaluation Kit

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SpW-10X ASIC Mezzanine Board

2020