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Frank Sill, SSTA
11/16/2005 page 2
Institute of Applied Microelectronics and Computer Engineering
University of Rostock
Statistical Static Timing Analysis and Statistical Static Timing Analysis and Modeling of Parameter Variations Modeling of Parameter Variations
Frank Sill14th November 2005
11/16/2005 page 3
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
OutlineOutline
1) Parameter Variations in Upcoming Technologies 2) Static Timing Analysis (STA)3) Statistical Static Timing Analysis (SSTA)4) MVT and SSTA5) Summary
11/16/2005 page 4
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Parameter Variations IncreaseParameter Variations Increase
from: S. Brokar, VLSI‘05
from: ITRS’03
130nm~1000 samples
30%
5X0.9
1.0
1.1
1.2
1.3
1.4
1 2 3 4 5Normalized Leakage (Isb)
Nor
mal
ized
Fre
quen
cy
11/16/2005 page 5
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Sources of Variability (1)Sources of Variability (1)
Power4 Server Chipfrom: Devgan, ICCAD’03
Temperature Variations + Hot spots
11/16/2005 page 6
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
2.32.22.12.01.91.8
50100
150
020
4060
Line
Wid
th [n
m]
Wafer Y Wafer Y0 Spanos, UCB
Varying Line Width
x10-7
Sources of Variability (2)Sources of Variability (2)
11/16/2005 page 7
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Sources of Variability (3)Sources of Variability (3)Field-dependent aberrations
),(A_CELL),(A_CELL),(A_CELL 220011 YXYXYX ≠≠
Center: Minimal
Aberrations
Edge: High Aberrations
Tow
ards
Len
s
Wafer Plane
Lens
R. Pack, Cadence
11/16/2005 page 8
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
OutlineOutline
1) Parameter Variations in Upcoming Technologies
2) Static Timing Analysis (STA)• Basics• Design Corners
3) Statistical Static Timing Analysis (SSTA)4) MVT and SSTA5) Summary
11/16/2005 page 9
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Static Timing Analysis (1)Static Timing Analysis (1)
0.05 0.01
0.01
0.1
wire / interconnect delay (td,wire)
00
1
arrival time
2
2
2
1
gate delay (td,gate)
Delay
11/16/2005 page 10
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Static Timing Analysis (2)Static Timing Analysis (2)0.05 0.01
0.01
0.100
1
2
2
2
1wAB
C
y
zx
F
A
B
C
w
y
xz F
1
0
0 2
22
10.05
0.1
0.01
0.01
11/16/2005 page 11
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Static Timing Analysis (3)Static Timing Analysis (3)
11/16/2005 page 12
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Static Timing Analysis (4)Static Timing Analysis (4)
00
1
2
2
1
2
0 2 4 6 time
11/16/2005 page 13
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
How affect Variations the Timing?
Gate delay: td,gate => function of: temperature, Tox, W , L , Vth,
doping, VDD, ...
Wire/Interconnect delay:td,wire => function of: temperature, Cpara., W, …
Each parameter can vary!
11/16/2005 page 14
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Until now: Design Corners• Design Corners = Processing + Environmental Variations• Box surrounding guaranteed
circuit performance• STA for all cases (usually 5)• Typically 3 varying Parameters
(Temp., VDD, Process)
nMOSpM
OS
fastslowsl
owfa
st
nTpT
nFpF
nSpSnFpS
nSpF
too less for DSM-Technologies(Deep Sub-Micron, Leff < 100nm)
11/16/2005 page 15
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Design Corners in DSM (1)
nTpT
nFpF
nSpSnFpS
nSpF
nFpF nSpS
nMOS
pMO
S
fastslow
slow
fast
nMOS
pMO
S
fastslow
slow
fast
nTpT
delay-Δx1 x -Δx1
nFpF
nSpSnFpS
nSpF
nFpF nSpS
-Δx2 -Δx2
3 varying parameters10+x varying parameters
11/16/2005 page 16
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Design Corners in DSM (2)
Problem: predicted delay very high => maximum allowed frequency is very low
1CLKfrequency
max( Delay )=
Solution: Probabilistic determination of timing behavior
Delay
11/16/2005 page 17
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
OutlineOutline
1) Parameter Variations in Upcoming Technologies2) Static Timing Analysis (STA)
3) Statistical Static Timing Analysis (SSTA)• Basics• SSTA at Multi-Input Gates• Delay Extraction
4) MVT and SSTA5) Summary
11/16/2005 page 18
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Gaussian Distribution
Most variations can be described as Gaussian Distribution
µ - mean value, σ – standard deviation
( )2
21
22xy( x ) exp μσσ π
⎛ ⎞−= ⋅ −⎜ ⎟
⎝ ⎠
-3σ -2σ -1σ µ,σ=0 1σ 2σ 3σ Copyright by wikipedia.com
11/16/2005 page 19
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Deterministic vs. Statistical STA
-3σ
Gaussian Distribution
99,8% of all cases
+3σ
Worst Case
Best Case
Wasted by conservative approach!
#10k Monte-Carlo simulations of NAND2 (Variation of NDEP, Leff, Weff, Temp, Vth)
11/16/2005 page 20
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Statistical Static Timing AnalysisStatistical Static Timing Analysis
0 2 4 6time
Deterministic STA:(Worst Case Analysis)
time0 2 4 6
Statistical STA:
11/16/2005 page 21
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Concept
Library with Gaussian distribution
of gate delays
Statistical Static Timing Analysis (SSTA)
New Approach for SSTA on gates
with multiple inputs
Gate-Netlist
11/16/2005 page 22
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Modeling of Gate DelayP
roba
bilit
y
Gate Delay
Pro
babi
lity
Gate Delay
( )2
2
1( ) exp22
xPDF x
μσσ π
⎛ ⎞−= ⋅ −⎜ ⎟⎜ ⎟
⎝ ⎠
Probability Density Function (PDF)
Probability that gate delay has value x
Cumulative probability Distribution Function (CDF)
Probability that gate delay is lower than x
( )2
20 0
1( ) ( ) exp22
x x tCDF x PDF t dt dt
μσσ π
⎛ ⎞−= = ⋅ −⎜ ⎟⎜ ⎟
⎝ ⎠∫ ∫
11/16/2005 page 23
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
SSTA on Multi-Input Gates
BA Y ?
Established Approach:
all but one input are ignored
accurate function for output signal
function for output signal at established approach
Error!
11/16/2005 page 24
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
SSTA on Multi-Input Gates cont’dNew Approach: As function of output signal results from multiplication of all input CDFs
CDF is approximated as straight line
=> new CDF results from multiplication of all approximated straight lines of input signals
accurate function for output signalnew approach
(
)
σ
μσ
⋅+
−⋅
⋅⋅
=
5.1)
5.12(
1)
(
x
xs
11/16/2005 page 25
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Delay - Extraction
0,00
0,02
0,04
0,06
0,08
0,10
0,12
45,00 49,00 53,00 57,00 61,00 65,00 69,00 73,00
max. delay [ps]
Prob
abili
ty
Monte-Carlo Simulation
NAND2 in predictive 65nm BPTM technology
11/16/2005 page 26
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Delay - Extraction
0,00
0,02
0,04
0,06
0,08
0,10
0,12
45,00 49,00 53,00 57,00 61,00 65,00 69,00 73,00
max. delay [ps]
Prob
abili
ty• Evaluated delay if one
parameter is described with Gaussian distribution (here Leff)
• Normally used
NAND2 in predictive 65nm BPTM technology
11/16/2005 page 27
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Delay - Extraction
0,00
0,02
0,04
0,06
0,08
0,10
0,12
45,00 49,00 53,00 57,00 61,00 65,00 69,00 73,00
max. delay [ps]
Prob
abili
ty• Gaussian description of
gate delay
• Extracted from Monte-Carlo Spice Simulation
• Set of parameters described with Gaussian distribution
NAND2 in predictive 65nm BPTM technology
11/16/2005 page 28
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
OutlineOutline
1) Parameter Variations in Upcoming Technologies 2) Static Timing Analysis (STA)3) Statistical Static Timing Analysis (SSTA)
4) MVT and SSTA• Idea of MVT• Improvements in delay and leakage
5) Summary
11/16/2005 page 29
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Idea of MVT approachIdea of MVT approach
use different types of Gates:
LVT: fast, high leakage
MVT: medium speed, medium leakage
HVT: slow, low leakage
Goal: maximum count of MVT / HVT gates at constant delay
11/16/2005 page 30
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
SSTA and MVT
Two improvements possible:
1. Increased Performanceor
2. Reduced Leakage
11/16/2005 page 31
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
SSTA & MVT: Increased PerformanceSSTA & MVT: Increased Performance
For a chosen reliability R => all critical paths are faster than a specific delay
FF FF
critical pathdelay
Probability distribution of delay of output signal
For a reliability R, delay is lower than x on every chip
x
Example: for R = 100 % the delay is always lower than 1400 ps (worst case)for R = 99,8 % the delay is always lower than 1200 psfor R = 95 % the delay is always lower than 1000 ps
11/16/2005 page 32
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Results: Delay ReductionResults: Delay Reduction
0,0%
5,0%
10,0%
15,0%
20,0%
25,0%
c432 c499 c880 c1335 c1908 c2610 c3540 c5315 c6288 c7552
Red
uctio
n of
Del
ay
SSTA with 99.8% reliability SSTA with 95% reliability
21%
19%
11/16/2005 page 33
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
SSTA & MVT: Reduced LeakageSSTA & MVT: Reduced Leakage• Estimation of worst case delay (100% reliability)• SSTA at allocation of HVT / MVT gates
Delay stays the same for a chosen reliability R, but count of low leakage gates increases
FF
FF
FF
FF
critical path
FF FF
LVT
MVT
HVT
FF
FF
FF
FF
critical path
FF FF
11/16/2005 page 34
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
Results: Leakage Reduction compared Results: Leakage Reduction compared to MVTto MVT--optimized Circuitsoptimized Circuits
0,0%
10,0%
20,0%
30,0%
40,0%
50,0%
60,0%
c432 c499 c880 c1335 c1908 c2610 c3540 c5315 c6288 c7552
Leak
age
Red
uctio
n
SSTA with 99.8% reliability SSTA with 95% reliability
27%25%
11/16/2005 page 35
Frank Sill, SSTAInstitute of Applied Microelectronics and Computer Engineering
University of Rostock
SummarySummary
• Parameter variations, which affect gate behavior, increase in upcoming technologies
• Low performance at 100% reliability
• Statistical Analysis (SSTA) allows higher performance at small decrease of reliability
• SSTA combined with MVT can reduce leakage or can increase performance