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Stop-and-Go Gate Drive Minimizing Test Cost to Find Optimum Gate Driving Vectors in Digital Gate
Drivers
Toru Sai The University of Tokyo
Tokyo, Japan [email protected]
Tomoyuki Mannen Tokyo Metropolitan University
Tokyo, Japan [email protected]
Takayasu Sakurai The University of Tokyo
Tokyo, Japan [email protected]
Koutaro Miyazaki The University of Tokyo
Tokyo, Japan [email protected]
Keiji Wada Tokyo Metropolitan University
Tokyo, Japan [email protected]
Makoto Takamiya The University of Tokyo
Tokyo, Japan [email protected]
Hidemine Obara Yokohama National University
Kanagawa Japan [email protected]
Ichiro Omura Kyusyu Institute of Technology
Fukuoka, Japan [email protected]
Abstract— An active gate driving is effective to solve the trade-off between the switching loss and the current/voltage overshoot of power transistors. The test cost in the conventional digital gate drivers with four variables, however, is high, because more than 2000 measurements are required to find an optimum gate driving vector out of 644 (~1.7 x 107) combinations [1]. To minimize the test cost, a stop-and-go gate drive with only one variable is proposed. The switching loss and the current/voltage overshoot in turn-on/off state of IGBT of the conventional gate drive [1] and the proposed stop-and-go gate drive are measured by using a 6-bit programmable digital gate driver IC across nine conditions including different load currents (20 A, 50 A, and 80 A) and temperatures (25 °C, 75 °C, and 125 °C), and they are compared. The performance degradation of the switching loss and the current/voltage overshoot in the proposed stop-and-go gate drive over the conventional gate drive with four variables [1] is less than 8 % and 25 % across the nine conditions in turn-on/off state respectively.
Keywords—Gate driver, IGBT, Test cost, Load current, Temperature
I. INTRODUCTION
Digital gate drivers [1-15] are useful for the active gate driving, because the gate driving current is programmable with gate driving vectors using a software. However the test cost to find optimum gate driving vectors in the conventional digital gate drivers is high, because the number of variables is large (4 [1], 30 [3], and 88 [4]), the number of combinations of variables is huge, and it takes time to find the optimum vectors through trial-and-error measurements. For example, in a 6-bit programmable digital gate drivers with four variables, more than 2000 measurements are required to find an optimum gate driving vector out of 644 (~1.7 x 107) combinations using a simulated annealing algorithm [1]. In [3], the number of combinations is 6430 (~1.5 x 1054). To make matters worse, a load current (ILOAD) and temperature dependent optimization of the gate driving vectors is required [2], because an optimum vector at a particular ILOAD and temperature does not often work at different conditions, which further increases the test cost. In the proposed stop-and-go gate drive, the test cost is less than 1/200 of the conventional gate drive with four variables [1],
because the required number of measurements is less than ten.
II. PROPOSED STOP-AND-GO GATE DRIVE
A. Measurement Setup for Stop-and-Go Gate Driver
Fig. 1 shows a circuit schematic of the measurement setup for the double pulse test for turn-on and turn-off of IGBT (2MBI100VA-060-50, 600 V, 100 A) at 300 V. In order to realize a programmable 63-level drivability in the programmable gate driver, 63 parallel transistors are connected to the gate of IGBT and a 6-bit control signal is applied to specify the number of activated PMOS (NMOS) transistors, nPMOS (nNMOS) [1], respectively. In [2] shown in Fig. 2 (a), the gate driving vector is (n1, n2, n3, n4) with four 160-ns time steps in turn-on state and four 400-ns steps in turn-off state, where n1, n2, n3, and n4 are integers from 0 to 63. (n1, n2, n3, n4) means four variables. In contrast, in the proposed stop-and-go gate drive shown in Fig. 2 (b), the gate driving vector is only n1, which means one variable. In turn-on state, nPMOS is n1 for t1, and nPMOS is 0 for t2, followed by nPMOS is 63 (maximum). t1 and t2 are decided in advance based on the data sheet of power devices and fixed in the measurement. In the measurement, t1 = 320 ns and t2 = 160 ns in turn-on state, while t1 = t2 = 800 ns in turn-off state.
IC
VGE
63 PMOSs
63 NMOSs
15V
Co
ntr
ol s
ign
als:
n NM
OS
and
nP
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S
I LOA
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300V
VCE
Digital gate driver IC IGBT module
Fig. 1. Circuit schematic of measurement setup.
978-1-7281-4829-8/20/$31.00 ©2020 IEEE 3096
Fig. 3 shows a gate charge dependence of gate-emitter voltage (VGE) of IGBT shown in the data sheet. n1 in turn-on state is estimated by the gate current of Q1 / t1, where Q1 is the gate charge at threshold voltage (VTH). Similarly, n1 in turn-off state is estimated by the gate current of Q2 / t1.
B. How to Set t1, t2, and n1 in Turn-on and Turn-off
In turn-on state for example when Q1 = 50 nC from the data sheet and set t1 = 320 ns, the necessity of turn-on current is determined by Q1 / t1 = 50 nC / 320 ns = 156 mA. Where Q1 is the amount of the gate charge when VGE reach from 0V to VTH as shown Fig. 2. In order to flow 156 mA by nPMOS driver, the strength of nPMOS driving number set to about n1 = 27 as shown following calculation, (156mA / 370mA) x 63 = 27. Because the full scale current of nPMOS driver, that is n1 = 63, is 370 mA by the driver IC in this measurement setup. Also the time slot t2 is set to over the reverse recovery time trr of the body diode D1 in Fig. 1 In turn-off state the necessity of current of turn-off is determined by Q2 / t1. Here Q2 is the difference of the gate charge between the turn-on state and the edge of plateau as
shown Fig. 2. For example, when Q2 = 250 nC from the data sheet and set t1 = 800 ns, the necessity of turn-off current is determined by Q2 / t1 = 250 nC / 800 ns = 313 mA. Therefore the strength of nNMOS set to about n1 = 40. Because the full scale current of nNMOS, that is n1 = 63, is 495mA by the driver IC setting in this measurement setup. the number of n1 is calculated as follow, (313mA / 495mA) x 63 = 40. And the time slot t2 has to hold 0 until the corrector current IC settle to about 0A. Otherwise the large overshoot voltage occurred in VCE. Although the full scale current of nPMOS and nNMOS set to about 370mA and 495mA in this setup, it can arbitrarily change by bias voltage for the driver IC. The time slot t1 should be determined to meet require current under the n1 of nNMOS and nPMOS is less than 63.
III. MEASURED RESULTS
A. Measured ELOSS vs. IOVERSHOOT and VOVERSHOOT
In order to comprehensively compare three gate drives including the conventional single-step gate drive, the conventional digital gate drive with four variables [1], and the proposed stop-and-go gate drive, ELOSS and the current overshoot (IOVERSHOOT) of IGBT is measured across nine conditions including different ILOAD (20 A, 50 A, and 80 A) and temperatures (25 °C, 75 °C, and 125 °C). Fig. 4 shows the measured ELOSS vs. IOVERSHOOT in turn-on state while Fig. 5 shows the measured ELOSS vs. VOVERSHOOT in turn-off state. The black curves show the trade-off curves using the conventional single-step gate driving waveforms with varied nPMOS from 5 to 63. The red squares show the results of the optimized vectors in the conventional digital gate drive with four variables using a simulated annealing algorithm [1]. The blue curves show the results of the proposed stop-and-go gate drive with varied n1 from 1 to 63. The turn-on object function (fOBJ_ON) and turn-off object function (fOBJ_OFF) are defined as
t2
(800ns)
nNMOS
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ICVCE
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n1n2n3n4
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Fig. 2 Gate charge dependence of VGE Gate driving vector and waveforms. (a) Conventional [1]. (b) Proposed stop-and-go gate drive.
0Gate charge
Q1
VG
E[V
] 15
VTH
Q2
0
Fig. 3. Gate charge dependence of VGE.
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2
MAX OVERSHOOT,
OVERSHOOT
2
MAX LOSS,
LOSSOBJ_ON
+
=
I
I
E
Ef (1)
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MAX OVERSHOOT,
OVERSHOOT
2
MAX LOSS,
LOSSOBJ_OFF
+
=
V
V
E
Ef (2)
where the subscript MAX signifies the maximum of the corresponding quantity. The dotted concentric curves in Fig. 4 show the contour of fOBJ defined in Eq. (1). The smaller fOBJ is preferred. In Fig. 4 the smallest value fOBJ of the blue line is close to the optimized point in each nine conditions. For example, in the 25 °C with 50A condition the minimum fOBJ of the blue line is obtained at n1 = 28 and it is close to the value of the optimized point as indicated red square. The minimum fOBJ
of the other blue lines are also close the optimized red squares. It means that the effect of proposed stop-and-go vectors are comparable to the ideal vectors. In the 25 °C with 50A in Fig. 5, the minimum fOBJ is obtained at n1 = 47 and it is also close the optimized point. In addition, the proposed stop-and-go vector has good performance in other eights conditions in turn-off state.
B. Optimum Gate Driving Vectors n1
Fig. 6 shows optimum n1 at each ILOAD and temperature. The optimum n1 is different across ILOAD and temperature variations. Fig. 6 (a) shows optimum n1 in turn-on and Fig. 6 (b) shows that in turn-off. The number of vectors is only one variable vectors for each nine conditions. According the load current increase, the vector strength become lager in both turn-on and turn-off. Also same as temperature increasing.
I LOAD
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n1=28n1=26
n1=33
Fig. 4 Measured ELOSS vs. IOVERSHOOT of three gate drives in turn-on state. Black curves: trade-off curves using the conventional single-step gate driving waveforms with varied nPMOS from 5 to 63. Red squares: the results of the optimized vectors in the conventional digital gate drive with four variables using a simulated annealing algorithm [1]. Blue curves: the results of the proposed stop-and-go gate drive with varied n1 from 1 to 63.
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C. Minimum fOBJ of Three Gate Drives at Nine Conditions
Fig. 7 show the minimum fOBJ of the three gate drives at nine conditions. The fOBJ of the proposed stop-and-go vector is close to the that of optimum vectors and it performs drastically reduces fOBJ compare to the conventional single step. Quantitatively, the difference of fOBJ between the conventional digital gate drive with four variables and the proposed stop-and-go gate drive of turn on is less than 8 %, and that of turn off is less than 25% which indicates that the performance of the proposed stop-and-go gate drive is quite good.
D. Stop-and-Go Gate Driving Vectors and measured Waveforms
Figs. 8 (a), (b), and (c) show the stop-and-go gate driving vectors and measured waveforms at 50 A, 25 °C in turn-on state at n1 = 28 (optimum value), n1 = 26 (optimum value − 2), and n1 = 33 (optimum value + 5), respectively. The corresponding ELOSS and IOVERSHOOT are shown in Fig. 4. In Figs. 8 (b) and (c), larger IOVERSHOOT is observed, while, in Fig. 8 (a), IOVERSHOOT is minimized. In Fig. 8 (b) the strength n1 is weaker than Fig. 8 (a), so the current IC rise time is slightly slow, and the IOVERSHOOT
occurred because the slot time t2 cannot absorb the reverse recovery time trr. within 160n. And after that the n1 = 63 vector is applied before the reverse recovery current IRR settle 0A. It results in IRR rides on the IC. then IOVERSHOOT appeared on IC. Also, the weak drive strength makes ELOSS as shown in Fig. (b). In Fig. (c) the strength n1 is stronger than Fig. (a), so the IOVERSHOOT is occurred because of the reverse recovery current IRR of D1.
125°C
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AX
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n1=49
Fig. 5 Measured ELOSS vs. VOVERSHOOT of three gate drives in turn-on state. Black curves: trade-off curves using the conventional single-step gate drivingwaveforms with varied nPMOS from 5 to 63. Red squares: the results of the optimized vectors in the conventional digital gate drive with four variables using asimulated annealing algorithm [1]. Blue curves: the results of the proposed stop-and-go gate drive with varied n1 from 1 to 63.
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Figs. 9 (a), (b), and (c) show the stop-and-go gate driving vectors and measured waveforms at 50 A, 25 °C in turn-off state at n1 = 47 (optimum value), n1 =46 (optimum value − 1), and n1 = 49 (optimum value + 2), respectively. The corresponding ELOSS and VOVERSHOOT are shown in Fig. 5. In
Figs. 9 (b) and (c), larger VOVERSHOOT is observed, while, in Fig. 9 (a), VOVERSHOOT is minimized. In Fig. 9 (b) the strength n1 is weaker than Fig. 9 (a), so the voltage VCE rise time is slightly slow, therefore there are no overshoot at rising edge of VCE. But the large VOVERSHOOT
f OB
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J
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Turn-offTurn-on
(a)
Fig. 7 Minimum fOBJ of three gate drives at nine conditions. (a) Turn-on. (b) Turn-off
20A 50A 80A
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ILOADT
emp
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ure
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Fig. 6 Optimum gate driving vectors n1 across nine conditions including different ILOAD (20 A, 50 A, and 80 A) and temperatures (25 °C, 75 °C, and 125 °C). (a) Turn-on. (b) Turn-off.
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Fig. 8 Stop-and-go gate driving vectors and measured waveforms at 50 A, 25 °C in turn-on state. (a) n1 = 28 (optimum value). (b) n1 = 26 (optimum value − 2). (c) n1 = 33 (optimum value + 5)
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occurred when vector applied to 63. Because the 63 level vector is applied to the gate of IGBT before the IC reach to about 0A. Also, the weak drive strength makes ELOSS as shown in Fig. 9 (b). In Fig. 9 (c) the strength n1 is stronger than Fig. 9 (a), so the voltage VCE rise time is faster than Fig. 9 (a), as a result a large amount of VOVERSHOOT is appeared at the rise edge of VCE.
IV. CONCLUSIONS
To minimize the test cost to find optimum gate driving vectors in the conventional digital gate drivers, the stop-and-go gate drive with only one variable (n1) is proposed. Compared with the conventional digital gate drive with four variables [1], the required number of measurements is reduced from 2000 to 9, while the fOBJ degradation is less than 8 % and 25 % across the nine conditions in turn-on/off state respectively. Therefore, the proposed stop-and-go gate drive with the minimized test cost is a practical method for the digital gate drivers.
ACKNOWLEDGMENT
This work was partly supported by the New Energy and Industrial Technology Development Organization (NEDO) of Japan. The assistance given by Kazuki Okawara of Toshiba Development & Engineering Corporation is appreciated.
REFERENCES
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and T. Sakurai, "General-Purpose Clocked Gate Driver IC With Programmable 63-Level Drivability to Optimize Overshoot and Energy Loss in Switching by a Simulated Annealing Algorithm," IEEE Transactions on Industry Applications, Vol.53, No.3, pp. 2350 - 2357, May/June 2017.
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[5] T. Sai, K. Miyazaki, H. Obara, T. Mannen, K. Wada, I. Omura, M. Takamiya, and T. Sakurai, " Robust Gate Driving Vectors to Load Current and Temperature Variations for Digital Gate Drivers," IEEE International Energy Electronics Conference (IFEEC), pp. 1 - 6, Nov. 2019. (to be presented)
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[7] L. Dang, H. Kuhn, and A.Mertens, “Digital adaptive driving strategies for high-voltage IGBTs,” in Proc. IEEE Energy Conversion Congress and Exposition, Sep. 2011, pp. 2993–2999.
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[9] M. Blank, T. Glück, A. Kugi, and H.-P. Kreuter, “Slew rate control strategies for smart power ICs based on iterative learning control,” in Proc. IEEE Appl. Power Electron. Conf. Expo., Mar. 2014, pp. 2860-2866.
[10] M. Takamiya, K. Miyazaki, H. Obara, T. Sai, K. Wada, and T. Sakurai, “Power electronics 2.0: IoT-connected and AI-controlled power electronics operating optimally for each user,” in Proc. IEEE 29th International Symposium on Power Semiconductor Devices and ICs, May 2017, pp. 29 -32.
[11] J. Dalton, J. Wang, H. Dymond, D. Liu, D. Pamunuwa, B. Stark, N. McNeill, and S. Hollis, “Shaping switching waveforms in a 650 V GaN FET bridge-leg using 6.7 GHz active gate drivers,” in Proc. IEEE Appl. Power Electron. Conf. Expo., Mar. 2017, pp. 1983-1989.
[12] D. Colin, and N. Rouger “High speed digital optical signal transferforpower transistor gate driver applications,” in Proc. IEEE 29th International Symposium on Power Semiconductor Devices and ICs, June 2017, pp. 37-40.
[13] H. Obara, K. Wada, K. Miyazaki, M. Takamiya, and T. Sakurai, “Active gate control in half-bridge inverters using programmable gate driver ICs to improve both surge voltage and converter efficiency,” IEEE Trans. on Industry Applications, vol. 54, issue 5, pp. 4603-4611, Mar. 2018.
[14] Y. Cheng, T. Mannen, K. Wada, K. Miyazaki, M. Takamiya, and T. Sakurai, “Optimization platform to find a switching pattern of digital active gate drive for full-bridge inverter circuit,” in Proc. IEEE Energy Conversion Congress and Exposition, Sep. 2018, pp. 6441-6443.
[15] Y. Cheng, T. Mannen, K. Wada, K. Miyazaki, M. Takamiya, T. Sakurai, "“High-Speed searching of optimum switching pattern for digital active gate grive circuit of full bridge inverter circuit,” in Proc. IEEE Appl. Power Electron. Conf. Expo., Mar. 2019, pp. 2740-2019.
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800ns
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Fig. 9 Stop-and-go gate driving vectors and measured waveforms at 50 A, 25 °C in turn-off state. (a) n1 = 47 (optimum value). (b) n1 = 46 (optimum value −1). (c) n1 = 49 (optimum value + 2).
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