Switch Cap01

8/18/2019 Switch Cap01

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Switched Capacitor Circuits (10/11/00) Page 1

ECE4430 Analog Integrated Circuit Design

SWITCHED CAPACITOR CIRCUITS INTRODUCTION

Object ive

The objective of these notes is to provide an elementary background about switched capacitorcircuits.

Outline

• Introduction

• Resistance emulation

• Switches

• Amplifiers

• Integrators

• First-order circuits

• Summary


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RESISTORS RESISTOR EMULATION

Switched Capacitors are Not New

James Clerk Maxwell used switches and a capacitor to measure the equivalent resistance of agalvanometer in the 1860’s.

Parallel Switched Capacitor Equivalent Resistor:

i (t) i (t)2

v (t)1 v (t)2

1 R

(b.)

Figure 9.1-1 (a.) Parallel switched capacitor equivalent resistor.

(b.) Continuous time resistor of value R.

(a.)

i (t) i (t)2

C v (t)1 v (t)2

1 1 2

v (t)C

Two-Phase, Nonoverlapping Clock:

t

t

1

0

1

00 T/ 2 T 3T/ 2 2T

2

1

Figure 9.1-2 - Waveforms of a typical two-phase, nonoverlapping clock scheme.


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EQUIVALENT RESISTANCE OF A SWITCHED CAPACITOR CIRCUIT

Assume that v1(t ) and v2(t ) are changing slowly with respect to the clock period.

The average current is,

i1(average) =1

T⌡⌠ 0

T

i1(t)dt =1

T⌡⌠ 0

T/2

i1(t)dt

Charge and current are related as,

i1(t) = dq1(t)dt Substituting this in the above gives,

i1(average) =1

T⌡⌠ 0

T /2

dq1(t ) =q1(T /2)-q1(0)

T =

CvC (T /2)-CvC (0)

T

However, vC (T /2) = v1(T /2) and vC (0) = v2(0). Therefore,

i1(average) = C [v1(T /2)-v2(0)]

T ≈ C [V 1-V 2]T

For the continuous time circuit:

⇒ i1(average) =V 1-V 2 R

∴ R ≈ T

C

For v1(t ) ≈ V 1 and v2(t ) ≈ V 2, the signal frequency must be much less than f c.

i (t) i (t)2

C v (t)1 v (t)2

1 1 2

v (t)C

i (t) i (t)2

v (t)1 v (t)2

1 R


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EXAMPLE 9.1 - DESIGN OF A PARALLEL SWITCHED CAPACITOR RESISTOR EMULATION

If the clock frequency of parallel switched capacitor equivalent resistor is 100kHz, find thevalue of the capacitor C that will emulate a 1MΩ resistor.

Solution

The period of a 100kHz clock waveform is 10µsec. Therefore, using the previousrelationship, we get that

C =T

R =

10-5

106 = 10pF

We know from previous considerations that the area required for 10pF capacitor is much less thanfor a 1MΩ resistor when implemented in CMOS technology.


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POWER DISSIPATION IN THE RESISTANCE EMULATION

If the switched capacitor circuit is an equivalent resistance, how is the power dissipated?

i (t) i (t)2

v (t)1 v (t)2

1 R

(b.)Figure 9.1-1 (a.) Parallel switched capacitor equivalent resistor.

(b.) Continuous time resistor of value R.

(a.)

i (t) i (t)2

C v (t)1 v (t)2

1 1 2

v (t)C

Continuous Time Resistor:

Power =(V 1 - V 2)

2

R

Discrete Time Resistor Emulation:

Assume the switches have an ON resistance of Ron. The power dissipated per clock cycle is,

Power = i1(aver.)(V 1-V 2) where i1 (aver.) =(V 1 -V 2)

RonT ⌡⌠ 0

T

e -t /( RonC )dt

∴ Power =(V

1-V

2)2

TRon ⌡⌠ 0

T

e -t /( RonC )dt =(V

1-V

2)2

(T/C ) [ ]-e -T /( RonC ) + 1 ≈

(V 1-V

2)2

(T/C ) if T >> RonC

Thus, if R = T/C , then the power dissipation is identical in the continuous time and discrete timerealizations.


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OTHER SWITCHED CAPACITOR EQUIVALENT RESISTANCE CIRCUITS

Series

i (t)2

v (t)1 v (t)2

i (t)1 1 2

1S 2S

C

v (t)C

Series-Parallel

i (t)2

C v (t)1 v (t)2

i (t)1 1 2

1S 2S 1

C 2v (t)C1 v (t)C2 1

1S i (t)2

v (t) v (t)2

i (t)1

1 2

2S C

12

1S 2S

Bilinear

v (t)C

Series-Parallel:The current, i1(t ), that flows during both the φ 1 and φ 2 clocks is:

i1(average) =1

T⌡⌠ 0

T

i1(t )dt =1

T

⌡⌠ 0

T /2

i1(t )dt + ⌡⌠ T /2

T

i1(t )dt =q1(T /2)-q1(0)

T +

q1(T )-q1(T /2)

T

Therefore, i1(average) can be written as,

i1(average) = C 2 [vC 2(T /2)-vC 2(0)]

T +

C 1 [vC 1(T )-vC 1(T /2)]T

The sequence of switches cause,vC 2(0) = V 2 , vC 2(T/2) = V 1 , vC 1(T/2) = 0, and vC 1(T) = V 1 - V 2.Applying these results gives

i1(average) = C 2[V 1-V 2]

T +

C 1[V 1-V 2- 0]

T =

(C 1+C 2)(V 1-V 2)

T

Equating the average current to the continuous time circuit gives: R =T

C 1 + C 2


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EXAMPLE 9.1-2 - DESIGN OF A SERIES-PARALLEL SWITCHED CAPACITOR

RESISTOR EMULATION

If C 1 = C 2 = C , find the value of C that will emulate a 1MΩ resistor if the clock frequency is250kHz.

Solution

The period of the clock waveform is 4µsec. Using above relationship we find that C is givenas,

2C =T

R =

4x10-6

106 = 4pF

Therefore, C 1 = C 2 = C = 2pF.


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SUMMARY OF THE FOUR SWITCHED CAPACITOR RESISTANCE CIRCUITS

Switched Capacitor Resistor

Emulation Circuit Schematic Equivalent Resistance

Parallel C v (t)1 v (t)2

1 2

T

C

Series v (t)1 v (t)2

1 2

C T

C

Series-Parallel

C v (t)1 v (t)2

1 2

1 C 2

T

C 1 + C 2

Bilinear

1v (t) v (t)2

1 2

C

2 1

T 4C


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ACCURACY OF SWITCHED CAPACITOR CIRCUITS

Consider the following continuous time, first-order, low pass circuit:

R1

C 21v v2

The transfer function of this simple circuit is,

H ( jω ) =V 2( jω )

V 1( jω ) =

1

jω R1C 2 + 1 =

1

jωτ 1 + 1

where τ 1 = R1C 2 is the time constant of the circuit and determines the accuracy.

Continuous Time Accuracy

Let τ 1

= τ C . The accuracy of τ

C can be expressed as,

d τ C τ C

= dR1 R1

+dC 2C 2

⇒ 5% to 20% depending on the size of the components Discrete Time Accuracy

Let τ 1 = τ D =

T

C 1 C 2 =

1

f cC 1 C 2. The accuracy of τ D can be expressed as,

d τ Dτ D =

dC 2C 2 -

dC 1C 1 -

df c f c ⇒ 0.1% to 1% depending on the size of components

The above is the primary reason for the success of switched capacitor circuits in CMOS technology.


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SWITCHED CAPACITOR CIRCUITS - kT/C NOISE

Switched capacitors generate an inherent thermal noise given by kT/C . This noise is verified asfollows.

An equivalent circuit for a switched capacitor:

C vout vin

+

-

+

-C vout vin

+

-

+

-

Ron

(a.) (b.)

Figure 9.3-11 - (a.) Simple switched capacitor circuit. (b.) Approximation of (a.).

The noise voltage spectral density of Fig. 9.3-11b is given as

e 2 Ron

= 4kTRon Volts2 /Hz =2kTR

onπ Volt

2 /Rad./sec. (1)

The rms noise voltage is found by integrating this spectral density from 0 to ∞ to give

v2

Ron

=2kTRon

π ⌡⌠

0

∞

ω 12d ω

ω 12+ω 2

=2kTRon

π

π ω1

2 =

kT

C Volts(rms)2 (2)

where ω 1 = 1/( RonC ). Note that the switch has an effective noise bandwidth of

f sw =1

4 RonC Hz (3)

which is found by dividing Eq. (2) by Eq. (1).


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SWITCHES

MOS TRANSISTOR AS A SWITCH

SymbolBulk

A B

(S/D) (D/S)

C (G)

A B

Fig4.1-2

On Characteristics of a MOS Switch

Assume operation in active region (vDS < vGS - VT) and vDS small.

iD =µCoxW

L

(vGS - VT) -vD S

2vDS ≈

µCoxW

L (vGS - VT)vDS

Thus, RON ≈ vD S

iD =

1

µCoxWL

(vGS - VT)

OFF Characteristics of a MOS Switch

If vGS < VT, then iD = IOFF = 0 when vDS ≈ 0V.

If vDS > 0, then

RO N ≈ 1

iDλ =

1

IOFFλ ≈ ∞


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MOS SWITCH VOLTAGE RANGES

If a MOS switch is used to connect two circuits that can have analog signal that vary from 0 to5V, what must be the value of the bulk and gate voltages for the switch to work properly?

Circuit

1

Circuit

2

(0 to 5V)

(S/D)

(0 to 5V)

(D/S)

Bulk

GateFig.4.1-3

• To insure that the bulk-source and bulk-drain pn junctions are reverse biased, the bulk voltagemust be less than the minimum analog signal for a NMOS switch.

• To insure that the switch is on, the gate voltage must be greater than the maximum analog signalplus the threshold for a NMOS switch.

Therefore:

V Bulk ≤ 0V

and

V Gate > 5V + V T

Also, V Gate(off) ≤ 0VUnfortunately, the large value of reverse bias bulk voltage causes the threshold voltage to increase.


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CURRENT-VOLTAGE CHARACTERISTICS OF A NMOS SWITCH

The following simulated output characteristics correspond to triode operation of the MOSFET.

100µA

60µA

20µA

-20µA

-60µA

-100µA-1V -0.6V -0.2V 0.2V 0.6V 1V

VGS=2V

VGS=3V

VGS=4V

VGS=5V

VGS=10V

VGS=9V

VGS=8V

VGS=7V

VGS=6V

Fig. 4.1-3

SPICE Input File:

MOS Switch On CharacteristicsM1 1 2 0 3 MNMOS W=3U L=3U.MODEL MNMOS NMOS VTO=0.75, KP=25U,+LAMBDA=0.01, GAMMA=0.8 PHI=0.6VDS 1 0 DC 0.0

VGS 2 0 DC 0.0VBS 3 0 DC -5.0.DC VDS -1 1 0.1 VGS 2 10 1.PRINT DC ID(M1).PROBE.END


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MOS SWITCH ON RESISTANCE AS A FUNCTION OF GATE-SOURCE VOLTAGE

100k Ω

10k Ω

1k Ω

100Ω1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

W/L = 1

W/L = 5

W/L = 10

W/L = 50

M O S S w i t c h O n R e s i

s t a n c e

Gate-Source Voltage Fig. 4.1-5

SPICE Input File:

MOS Switch On Resistance as a f(W/L)M1 1 2 0 0 MNMOS W=3U L=3UM2 1 2 0 0 MNMOS W=15U L=3UM3 1 2 0 0 MNMOS W=30U L=3UM4 1 2 0 0 MNMOS W=150U L=3U.MODEL MNMOS NMOS VTO=0.75, KP=25U,

+LAMBDA=0.01, GAMMA=0.8, PHI=0.6

VDS 1 0 DC 0.001VVGS 2 0 DC 0.0.DC VGS 1 5 0.1.PRINT DC ID(M1) ID(M2) ID(M3) ID(M4).PROBE.END


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INFLUENCE OF THE ON RESISTANCE ON MOS SWITCHES

Finite ON Resistance:

vin=2.5VV GateC

vC (0) = 0-+

vin>0C

vC -+

RON

Fig. 4.1-6

Example

Initially assume the capacitor is uncharged. If V Gate(ON) is 5V and is high for 0.1µs, find theW/L of the MOSFET switch that will charge a capacitance of 10pF in five time constants

(K N ’=110µA/V2 and V TN = 0.7V).

Solution

The time constant must be equal to100ns

5 = 20ns. Therefore RON must be less than

20ns

10pF = 2k Ω.

The on resistance of the MOSFET (for small v DS ) is

RON =1

K N ’(W / L)(V GS -V T ) ⇒

W

L =

1

RON ·K N ’(V GS -V T ) =

1

2k Ω·110µA/V2·4.3 = 1.06

Comments:

• It is relatively easy to charge on-chip capacitors with minimum size switches.

• Switch resistance is really not constant during switching and the problem is more complex thanabove.


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INCLUDING THE INFLUENCE OF THE VARYING ON RESISTANCE

Gate-source Constant

gON (t ) =K’W

L (vGS (t )-V T ) -v DS (t )

gON (aver.) =1

r ON (aver.) ≈

gON (0) + gON (∞)2

= K’W 2 L (V GS -V T ) -K’WV

DS (0)

2 L + K’W 2 L (V GS -V T )

=K’W

L(V GS -V T ) -

K’WV DS (0)

2 L

Gate-source Varying

V GS =5V

V GS =5V-v IN

V DS

I D t =0

t =∞

gON (0)

gON

(∞)

Fig. 4.1-8v DS (0)v DS (∞)

V Gate

C vC (0) = 0-

+

+

-

vGS (t )

v IN

gON =K’W

2 L [V GS (0)-V T ] -

K’WV DS (0)

2 L +

K’W

2 L [V GS (∞)-v IN -V T ]

V GS =5V

V DS

I D t =0

t =∞

gON (0)

gON (∞)

Fig. 4.1-7v DS (0)v DS (∞)


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SWITCH ON RESISTANCE EXAMPLE

Assume that at t = 0, the gate of the switch shown is taken to 5V. Design the W/L value of theswitch to discharge the C 1 capacitor to within 1% of its initial charge in 10ns. Use the MOSFET

parameters of Table 3.1-2.

+

-+

5V-

0V

5V

C 1 =

10pF

C 2 = 10pF

+ -0V

Fig.4.1-9

vout (t )

Solution

Note that the source of the NMOS is on the right and is always at ground potential so there isno bulk effect as long as the voltage across C 1 is positive. The voltage across C 1 can be expressed as

vC 1(t ) = 5exp

-t RON C 1

At 10ns, vC 1 is 5/100 or 0.05V. Therefore,

0.05 = 5exp

-10-8

RON 10-11

= 5exp

-103

RON ⇒ exp(GON 103) = 100 ⇒ GON =

ln(100)

103 =

0.0046S

∴ 0.0046 =K’W

L(V GS -V T ) -

K’WV DS

2 L =

110x10-6·4.3 -110x10-6·5

2 W

L = 198x10-6

W

L

Thus,W

L =

0.0046

198x10-6 = 23.2 ≈ 23


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INFLUENCE OF THE OFF STATE ON MOS SWITCHES

The OFF state influence is primarily in any current that flows from the terminals of the switch toground.

An example might be:

vinvout

C H

+

- R Bulk +

-vCH

Fig. 4.1-10

Typically, no problems occur unless capacitance voltages are held for a long time. For example,

vout (t ) = vCH [1 - e-t /(R Bulk C H )]

If R Bulk ≈ 109Ω and C H = 10pF, the time constant is 109·10-11 = 0.01seconds


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INFLUENCE OF PARASITIC CAPACITANCES

The parasitic capacitors have two influences:

• Parasitics to ground at the switch terminals (C BD and C BS ) add to the value of the desired

capacitors.

This problem is solved by the use of stray-insensitive switched capacitor circuits

• Parasitics from gate to source and drain cause charge injection onto or off the desired capacitors.

This problem can be minimized but not eliminated.

Model for studying charge injection:

1

V S

+

-

C L

vCL V S

+

-

C L

vCL

C channel

CGS0 CGD0

Rchannel

V S

+

-

C L

vCL

C channel

CGS0 CGD0

Rchannel

2

C channel

2

1 1

Fig. 4.1-11

A simple switch circuit useful

for studying charge injection.

A distributed model of

the transistor switch.

A lumped model of

the transistor switch.


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CHARGE INJECTION (CLOCK FEEDTHROUGH, CHARGE FEEDTHROUGH)

Charge injection is a complex analysis which is better suited for computer analysis. Here wewill attempt to develop an understanding sufficient to show ways of reducing the effect of chargeinjection.

What is Charge Injection?

1.) When the voltages change across the gate-drain and gate-source

capacitors, a current will flow because i = C

dv

dt .

2.) When the switch is off, charge injection will appear on the externalcapacitors (C L) connected to the switch terminals causing their voltages

to change.

There are two cases of charge injection depending upon the transition rate when the switch turns off.

1.) Slow transition time.

2.) Fast transition time.

Fig. 4.1-12


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SLOW TRANSITION TIME

Consider the following switch circuit:

vin+V T

Switch ONA

B

C

C Lvin

Fig. 4.1-13

vin+V T Switch OFF

A

B

C

C Lvin

Charge

injection

1.) During the on-to-off transition time from A to B, the charge injection is absorbed by the lowimpedance source, vin.

2.) The switch turns off when the gate voltage is vin+V T (point B).

3.) From B to C the switch is off but the gate voltage is changing. As a result charge injectionoccurs to C L.


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FAST TRANSITION TIME

For the fast transition time, the rate of transition is faster than the channel time constant so that someof the charge during the region from point A to point B is injected onto C L even though the

transistor switch has not yet turned off.

vin+V T

Switch ONA

B

C

C Lvin

Fig. 4.1-14

vin+V T Switch OFF

A

B

C

C Lvin

Charge

injection

Charge

injection


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APPROXIMATE ANALYSIS OF FEEDTHROUGH

The model for this case is given as:

Fig. 4.1-16

V S +V T Switch OFF

A

B

C

C Lvin ≈V S ≈V D

Charge

injection

C OLC OL

V S +V T

C OL

C L

+

-

vCL

V L

V S

V T

V LCircuit at the

instant gate

reaches V S +V T

The switch decrease from B to C is modeled as a negative step of magnitude V S +V T - V L.

The output voltage on the capacitor after opening the switch is,

vCL =

C L

C OL+C LV S -

C OL

C OL+C LV T -(V S + V T -V L)

C OL

COL+C L ≈ V S - (V S + 2V T -V L)

C OL

C L

if C OL < C L.

Therefore, the error voltage is

V error ≈ -(V S + 2V T - V L)

C OLC L = -(vin + 2V T - V L)

C OLC L


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SOLUTIONS TO CHARGE INJECTION

1.) Use minimum size switches to reduce the overlap capacitances and/or increaseC L.

2.) Use a dummy compensating transistor.

φ1 φ1

M1 MD

W 1 L1

W D L D

=W 12 L1

Fig. 4.1-19

• Requires complementary clocks

• Complete cancellation is difficult and may in fact may make the feedthrough worse

3.) Use complementary switches (transmission gates)

4.) Use differential implementation of switched capacitor circuits (probably the best solution)


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INPUT-DEPENDENT CHARGE INJECTION

Examination of the error voltage reveals that,

Error voltage = Component independent of the input + Component dependent on the input

This only occurs for switches that are floating and is due to the fact that the input influences thevoltage at which the transistor switches (vin ≈ V S ≈ V D). Leads to spurious responses and otherundesired results.

Solution:Use delayed clocks to remove the input-dependence by breaking the current path for injection

from the floating switches.

C i

φ1

φ2φ1d

φ2

CsVin

LC

VoutS1

S2 S3

S4

φ1

φ2

φ1d

Clock Delay

t

t

t

Fig. 4.1-20

Assume that C s is charged to V in (both φ 1 and φ 1d are high):

1.) φ 1 opens, no input-dependent feedthrough because switch terminals (S3) are at ground potential.

2.) φ 1d opens, no feedthrough occurs because there is no current path (except through small

parasitic capacitors).

S i h d C i Ci i (10/11/00) P 26


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CMOS SWITCHES (TRANSMISSION GATE)

V DD

Clock

Clock

A B

Fig. 4.1-21

B A

Clock

Clock

Advantages:

• Feedthrough somewhat diminished

• Larger dynamic range

• Lower ON resistance

Disadvantages:

• Requires a complementary clock

• Requires more area

S it h d C it Ci it (10/11/00) P 27


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DYNAMIC RANGE OF THE CMOS SWITCH

The dynamic range of a switch is the range of voltages at the switch terminals (V A ≈ V B = V A,B)over which the ON resistance stays reasonably small.

V DD

A B

V DD

M1

M2

1µAV A,B

Fig. 4.1-22

Spice File:Simulation of the resistance of a CMOS

transmission switch

M1 1 3 2 0 MNMOS L=2U W=50U

M2 1 0 2 3 MPMOS L=2U W=50U

.MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5

.MODEL MPMOS PMOS VTO=-0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5

VDD 3 0

VAB 1 0

IA 2 0 DC 1U

.DC VAB 0 5 0.02 VDD 4 5 0.5

.PRINT DC V(1,2)

.END

Result:Low on resistance over a wide voltage range becomes very difficult as the power supply

decreases.

0k Ω

0.5k Ω

1k Ω

1.5k Ω

2k Ω

2.5k Ω

3k Ω

S w i t c h O n R e s i s t a n c e

0V 1V 2V 3V 4V 5V

VDD = 5V

VDD = 4.5V

VDD = 4V

A,B (Common mode voltage)V



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CMOS SWITCH WITH TWIN-WELL SWITCHING

VDD

VSS

M1

M2

M3

M4 M5

Analog

SignalInput

Analog

Signal

Output

VControl

VControl

Circuit when V Control is in its high state. Circuit when V Control is in its low state.

M1

M2

High State

Low State

Analog

SignalOutput

Analog

SignalInput

M1

M2

High State

Low State

Analog

Signal

Output

Analog

Signal

Input VDD

VSS



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CHARGE PUMPS FOR SWITCHES WITH LOW POWER SUPPLY VOLTAGES

As power supply voltages decrease below 3V, it becomes difficult to keep the switch on at alow value of on-resistance over the range of the power supply. Consequently, charge pumps areused.

Charge pump circuit:

0V

3.3V

C1 C2

VDD

= 3.3V

Vsub_hi

CL

0V

0V

Vhi

To asingleNMOSswitch

M1

(Prevents latchup)

≈ 5V

Vhi = 2VDD·C2

Cgate,NMOS switch + C2 + CL



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CHARGE PUMP - CONTINUED

High voltage generator for the well of M1:

C1 C2

VDD = 3.3V

Vsub_hi

CStorage

0V

0V

3.3V

6.6V

Prevents latch-up of M1 by providing a high bulk bias (6.6V).

Use a separate clock driver for each switch to avoid crosstalk through the gate clock lines.

Area for layout can be small.



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Sw tc ed Capac to C cu ts ( 0/ /00) age 3


SIMULATION OF THE CHARGE PUMP CIRCUIT

Circuit:

V DD

C 1

V SS

M1 CLK_out

CLK_in

M2M3

M4

Fig. 4.1-23

CLK_outM5

M6

C 1

Simulation:3.0

2.0

1.0

0.0

-1.00.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

V o l t s

Time (µs)

Input

Output

Fig. 4.1-24



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p ( ) g


SUMMARY OF MOS SWITCHES

• Symmetrical switching characteristics

• High OFF resistance

• Moderate ON resistance (OK for most applications)

• Clock feedthrough is proportional to size of switch (W) and inversely proportional to

switching capacitors.

• Output offset due to clock feedthrough has 3 components:

Ideal

Input dependent

Input independent

• Complementary switches help increase dynamic range.

• As power supply reduces, switches become more difficult to fully turn on.



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AMPLIFIERS

CONTINUOUS TIME AMPLIFIERS

+

-

v IN

OUT v R1 R2

+

-

v IN R1 R2OUT v

Noninverting Amplifier Inverting Amplifier

Gain and GB = ∞:V out V in

= R1+ R2

R1

V out V in

= - R2 R1

Gain ≠ ∞, GB = ∞:

V out V in

= Avd (0)

1 + A vd (0) R 1

R1+ R2

=

R1+ R2

R1

A vd (0) R1

R1+ R2

1 + A vd (0) R 1

R1+ R2

V out V in

=

-R2 Avd (0)

R1+ R2

1 + A vd (0) R 1

R1+ R2

= -

R2

R1

R1 Avd (0)

R1+ R2

1 + A vd (0) R 1

R1+ R2

Gain ≠ ∞, GB ≠ ∞:

V out (s)

V in(s) =

R1+ R2 R1

GB·R1 R1+ R2

s +GB·R 1 R1+ R2

=

R1+ R2 R1

ω H s+ω H

V out (s)

V in(s) =

-

R 2 R1

GB·R1 R1+ R2

s +GB·R1 R1+ R2

=

-

R 2 R1

ω H s+ω H



34/60


EXAMPLE 9.2-1- ACCURACY LIMITATION OF VOLTAGE AMPLIFIERS DUE TO

A FINITE VOLTAGE GAINAssume that the noninverting and inverting voltage amplifiers have been designed for avoltage gain of +10 and -10. If Avd (0) is 1000, find the actual voltage gains for each amplifier.Solution

For the noninverting amplifier, the ratio of R2 / R1 is 9.

Avd (0) R1 /( R1+ R2) =1000

1+9= 100.

∴ V out V in = 10

100

101 = 9.901 rather than 10.

For the inverting amplifier, the ratio of R2 / R1 is 10. Avd (0) R1

R1+ R2 =

1000

1+10 = 90.909

∴ V out

V in = -(10)

90.909

1+90.909

= - 9.891 rather than -10.



35/60


EXAMPLE 9.2-2 - - 3 dB FREQUENCY OF VOLTAGE AMPLIFIERS DUE TO FINITE

UNITY-GAINBANDWIDTHAssume that the noninverting and inverting voltage amplifiers have been designed for a

voltage gain of +1 and -1. If the unity-gainbandwidth, GB, of the op amps are 2πMrads/sec, findthe upper -3dB frequency for each amplifier.

Solution

In both cases, the upper -3dB frequency is given by

ω H =GB·R1 R1+ R2

For the noninverting amplifier with an ideal gain of +1, the value of R2 / R1 is zero.

∴ ω H = GB = 2π Mrads/sec (1MHz)

For the inverting amplifier with an ideal gain of -1, the value of R2 / R1 is one.

∴ ω H =GB·11+1

=GB2

= π Mrads/sec (500kHz)



36/60


CHARGE AMPLIFIERS

+

-

v IN

OUT vC 1 C 2

Noninverting Charge Amplifier

+

-

v IN OUT v

Inverting Charge Amplifier

C 1 C 2

Gain and GB = ∞:V out V in

=C 1+C 2

C 2

V out V in

= -C 1C 2

Gain ≠ ∞, GB = ∞:

V out V in =

C 1+C 2C 2

Avd (0)C 2C

1+C

2

1 + Avd (0)C 2

C 1+C 2

V out V in =

-C 1C 2

Avd (0)C 2C

1+C

2

1 + Avd (0)C 2

C 1+C 2Gain ≠ ∞, GB ≠ ∞:

V out

V in =

C 1+C 2

C 2

GB·C 2C 1+C 2

s + GB·C 2C 1+C 2

V out

V in =

-C 1

C 2

GB·C 2C 1+C 2

s + GB·C 2C 1+C 2



37/60


SWITCHED CAPACITOR AMPLIFIERS

Parallel Switched Capacitor Amplifier:

1 2

+

-

1 2

vout inv

C 1

2C

Inverting Switched Capacitor Amplifier

+

-

vC 1

vC 2

+

-

1 2

+

-

1

2C

C 1

vout inv

Modification to prevent open-loop operation

vC 1

vC 2

+

-

+-

Analysis:

Assume that the switching frequency (clock frequency, f c = 1/ T ) is much greater than the

signal bandwidth. Then,

V out

V in = -

“ R2”

“ R1” ≈ -

T/C 2

T/C 1 = -

C 1

C 2If the oversampling assumption is not made, then the transfer function becomes,

V out V in

= - C 1C 2

z-1



38/60


FREQUENCY RESPONSE OF SWITCHED CAPACITOR AMPLIFIERS

Replace z by e jω T .

H ( jω ) =V out (e

jω T )

V in(e jω T )

= -

C 1

C 2 e-jω T/2

and

H ( jω ) =

V out (e jω T )

V in(e jω T ) = -

C

1C 2 e

-jω T

If C 1 / C 2 is equal to R2 / R1, then the magnitude response is identical to inverting unity gain amplifier.

However, the phase shift of H oe(e jω T ) is

Arg[ H (e jω T )] = ±180° - ω T /2

and the phase shift of H oe

(e jω T

) isArg[ H (e jω T )] = ±180° - ω T .

Comments:

• The phase shift of the switched capacitor inverting amplifier has an excess linear phase delay.

• When the frequency is equal to 0.5 f c, this delay is 90°.

• One must be careful when using switched capacitor circuits in a feedback loop because of theexcess phase delay.



39/60


POSITIVE AND NEGATIVE TRANSRESISTANCE EQUIVALENT CIRCUITS

Transresistance circuits are two-port networks where the voltage across one port controls thecurrent flowing between the ports. Typically, one of the ports is at zero potential (virtual ground).

Circuits:

Positive Transresistance Realization.

1

2 2

1

C

vC (t )

v1(t )

i1(t ) i2(t )

C P C P

Negative Transresistance Realization.

1

2

2

1

C

vC (t )

v1(t )

i1(t ) i2(t )

C P C P

Analysis (Negative transresistance realization):

RT =v1(t )

i2(t ) =

v1i2(average)

If we assumev1(t ) is approximately constant over one period of the clock, then we can write

i2(average) =1

T ⌡⌠ T /2

T

i2(t )dt =q2(T ) - q2(T /2)

T =

CvC (T ) - CvC (T /2)

T =

-Cv1T

Substituting this expression into the one above shows that

R

T = -T / C

Similarly, it can be shown that the positive transresistance is T / C .

Comments:

• These results are only valid when f c >> f .

• These circuits are insensitive to the parasitic capacitances shown as dotted capacitors.



40/60


INVERTING STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER

Inverting Switched Capacitor Voltage Amplifier.

1

2

+

-

1

2C

vout inv v

C 2+-

1

2

vC1(t )vC1(t )

1C

vC1(t )

Analysis:



V out

V in = -

“ R2”

“ R1” ≈ -

T/C 2

T/C 1 = -

C 1

C 2



41/60


NONVERTING STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER

Use the negative transresistor switched capacitor circuit at the input to get,

Noninverting Switched Capacitor Voltage Amplifier.

1 2

+

-

1

2C

vout invvC 2

+-

121C

vC1(t )

Analysis:



V out

V in = -

“ R2”

“ R1” ≈ -

T/C 2

-T/C 1 = +

C 1

C 2



42/60


EXAMPLE 9.2-3 - DESIGN OF A SWITCHED CAPACITOR SUMMING AMPLIFIER

Design a switched capacitor summing amplifier using the circuits in stray insensitivetransresistance circuits which gives the output voltage during the φ 2 phase period that is equal to10v1 - 5v2, where v1 and v2 are held constant during a φ 2-φ 1 period and then resampled for the nextperiod.

Solution

Based on the previous examples, a solution is proposed below.

1 2

+

-

1

vo12

v1

1

2

1

2v2

C

10C

5C

It easy to show that if the oversampling assumption is true that,

V o ≈ 10V 1 - 5V 2



43/60


NONIDEAL OP AMPS - FINITE GAIN

Consider the inverting switched capacitor amplifier during φ 2:

inv

+

-

2C C 1

+

-

(n-1)T

vout (n-1/2)T e

ovout (n-1/2)T

e

Avd (0)

+- Op amp with finite

value of Avd (0)Fig. 9.2-11

The output during φ 2 can be written as,

ve

out (n -1/2)T =

C 1

C 2 v

o

in(n -1)T +

C 1+C 2

C 2 v

e

out (n -1/2)T

Avd (0)

Converting this to the z-domain and solving for the H oe( z) transfer function gives

H oe( z) =V

e

out ( z)

V o

in( z) =

C 1

C 2 z-1/2

1

1 -C 1 + C 2

Avd (0)C 2

.

Comments:• The phase response is unaffected by the finite gain

• A gain of 1000 gives a magnitude of 0.998 rather than 1.0.



44/60


NONIDEAL OP AMPS - FINITE BANDWIDTH AND SLEW RATE

Finite GB:• In general the analysis is complicated. (We will provide more detail for integrators.)

• The clock period, T , should be equal to or less that 10/ GB.

• The settling time of the op amp must be less that T /2.

Slew Rate:

• The slew rate of the op amp should be large enough so that the op amp can make a fullswing within T /2.



45/60


CONTINUOUS TIME INTEGRATORS

- R1 C 2 R R V out V in

(a.)

+

-

+

-

Inverter

(b.)

R1 C 2V in V out

+

-

(a.) Noninverting and (b.) inverting continuous time integrators.

Ideal Performance:

Noninverting- Inverting-

V out ( jω )

V in( jω ) =

1

jω R 1C 2 =

ω I jω

=- jω I ω

V out ( jω )

V in( jω ) =

-1

jω R 1C 2 =

-ω I jω

= jω I ω

Frequency Response:

90°

0°

Arg[V out ( jω)/ V in( jω)]

ω I log10

ω

|V out ( jω)/ V in( jω)|

ω I ω I ω I 100 10

10ω I 100ω I log10ω

40 dB

20 dB

0 dB

-20 dB

-40 dB

(a.) (b.)



46/60


NONINVERTING SWITCHED CAPACITOR INTEGRATOR

Approximate analysis: Assume that the switching frequency (clock frequency,

f c = 1/ T ) is much greater than the signal bandwidth. Then,

V out

V in = -

1/ sC 2

“ R1” ≈ -

1 /sC 2

-T/C 1 = +

C 1

sTC 2 =

ω I s

where

ω I =C I

TC 2

Exact analysis:V out ( z) V in( z)

=

C 1

C 2 z-1

1- z-1 =

C 1

C 2

1

z-1

Exact frequency response (replace z by e jω T ) to get,

V out (e jω T )

V in(e jω T )

=

C 1

C 2

e-jωΤ/ 2

j2 sin(ω T /2)

ω T

ω T =

C 1

jω TC 2

ω T /2

sin(ω T /2) ( )e

-jωΤ/ 2

= (Ideal)x(Magnitude error)x(Phase error) where ω I =C 1

TC 2 ⇒ Ideal =

ω I

jω

Noninverting, stray insensitive integrator.

1 2

2C

vout invvC 2

+-

12

1C

vC1(t )

+

-

+ -S 1

S 2 S 3

S 4



47/60


EXAMPLE 9.3-2 - COMPARISON OF A CONTINUOUS TIME AND SWITCHED

CAPACITOR INTEGRATORAssume that ω I is equal to 0.1ω c and plot the magnitude and phase response of the

noninverting continuous time and switched capacitor integrator from 0 to ω I .

Solution

Letting ω I be 0.1ω c gives

H ( jω ) =1

10 jω / ω c and H oo(e jωΤ ) =

1

10 jω / ω c

πω /ω c

sin(πω /ω c) ( )e

-jπω /ω c

Plots:

0

1

2

3

4

5

0 0.2 0.4 0.6 0.8 1

Magnitude

|Hoo

(e jωT

)|

|H(jω)|ωI

ω/ω c

-300

-250

-200

-150

-100

-50

0

0 0.2 0.4 0.6 0.8 1

Phase Shift (Degrees)

Arg[Hoo(e jωT)]

Arg[H(jω)]

ωI ω/ω c



48/60


INVERTING SWITCHED CAPACITOR INTEGRATOR

Analysis:Approximate analysis:

Assume that the switching frequency (clock frequency, f c = 1/ T ) is much greater than the signal

bandwidth. Then,

V out V in

= - 1/ sC 2 “ R1”

≈ - 1 /sC 2T/C 1

= - C 1sTC 2

= - ω I s

where

ω I =C I

TC 2

Exact analysis:

H ( z) = V out ( z)

V in( z) = -

C 1

C 2 11- z-1

= -

C 1

C 2 z z-1

Exact frequency response (replace z by e jω T ) to get,

V out (e jω T )

V in(e jω T

)

=

C 1

C 2

e-jωΤ/ 2

j2 sin(ω T /2)

ω T

ω T = -

C 1

jω TC 2

ω T /2

sin(ω T /2) ( )e

jωΤ/ 2

Same as noninverting integrator except for phase error.

Consequently, the magnitude response is identical but the phase response is given as

Arg[ H (e jωΤ )] =π

2 +

ωΤ

2 .

Inverting, stray insensitive integrator.

1

2

2C

vout invvC 2

+-

1

2

1C

vC1(t )

+

-S 1

S 2 S 3

S 4



49/60


A SIGN MULTIPLEXER

A circuit that changes the φ 1 and φ 2 of the leftmost switches of the stray insensitive, switchedcapacitor integrator.

1 2

V C

x

y

To switch connected

to the input signal (S 1).

To the left most switch

connected to ground (S 2).

V C

0

1

x y

1

12

2

Fig. 9.3-8

This circuit steers the φ 1 and φ 2 clocks to the input switch (S 1) and the leftmost switch connected to

ground (S 2) as a function of whether V c is high or low.



50/60


FIRST-ORDER, SWITCHED CAPACITOR CIRCUITS

GENERAL, FIRST-ORDER TRANSFER FUNCTIONSA general first-order transfer function in the s-domain:

H (s) =sa1 ± a0s + b0

a1 = 0 ⇒ Low pass, a0 = 0 ⇒ High Pass, a0 ≠ 0 and a1 ≠ 0 ⇒ All pass

Note that the zero can be in the RHP or LHP.

The following continuous time circuit is capable of realizing most of the various forms above:

+

-

R1 R2

C 1 C 2

V in V out

Fig.9.5-0

V out

V in = -

R2

R1 sR1C 1+1

sR2C 2+1



51/60


NONINVERTING, FIRST-ORDER, LOW PASS CIRCUIT

+

-

vi(t )

φ1

φ1φ2

φ2

φ2

vo(t)

C 1

(a.) (b.)Figure 9.5-1 - (a.) Noninverting, first-order low pass circuit. (b.) Equivalent circuit of Fig. 9.5-1a.

φ1 φ1 φ2

+

-

vi(t )

φ1

φ1φ2

φ2

φ2

vo(t)

φ2

φ1φ1vo(t )

α1C 1

α2C 1

α2C 1

α1C 1

C 1

Transfer function:

Noting that C 1 of the general circuit is zero gives,

V out

V in = -

“ R2”

” R1”

1

s” R2”C 2+1 ≈ -

α 1

α 2

1

sT/ α 2 +1 =

-α 1

sT + α 2 =

-α 1 / T

s + α 2 / T

Equating the above to the H(s) of the general first-order transfer function gives,

α 1 = a0T =a0

f c and α 2 = b0T =

b0

f c



52/60


INVERTING, FIRST-ORDER, LOW PASS CIRCUIT

An inverting low pass circuit can be obtained by reversing the phases of the leftmost two switches inFig. 9.5-1a.

+

-

vi(t )

φ2

φ1φ1

φ2

φ2

vo(t)

C 1

Inverting, first-order low pass circuit. Equivalent circuit.

φ1 φ1 φ2

+

-

vi(t )

φ2

φ1φ1

φ2

φ2

vo(t)

φ2

φ1φ1vo(t )

α1C 1

α2C 1

α2C 1

α1C 1

C 1

It can be shown that,

V out

V in =

“ R2”

” R1”

1

s” R2”C 2+1 ≈

α 1

α 2

1

sT/ α 2 +1 =

α 1

sT + α 2 =

α 1 / T

s + α 2 / T

Equating the above to the H(s) of a general first order transfer function gives the design equations as

α 1 = a0T =a0


b0

f c



53/60


EXAMPLE 9.5-1 - DESIGN OF A SWITCHED CAPACITOR FIRST-ORDER CIRCUIT

Design a switched capacitor first-order circuit that has a low frequency gain of +10 and a -3dB frequency of 1kHz. Give the value of the capacitor ratios α 1 and α 2. Use a clock frequency of

100kHz.

Solution

Assume that the clock frequency, f c, is much larger than the -3dB frequency. In this example,

the clock frequency is 100 times larger so this assumption should be valid. Therefore we can write,V out (s)

V in

(s) ≈

α 1α 2 + s T

=α 1 / α 2

1 + s(T / α 2)

Setting this equation equal to the specifications gives α 1 = 10α 2 and α 2 =ω -3dB f c

∴ α 2 = 6283/100,000 = 0.0628 and α 1 = 0.6283The above represent capacitor ratios and should preferably be close to unity for small area.



54/60


FIRST-ORDER, HIGH PASS CIRCUIT

+

-

vi(t )

φ2

vo(t)α1C

C

φ1 φ1 φ2α2C

+

-

vi(t )

φ2

φ2

vo(t)

C

φ1 φ1 φ2

(a.) (b.)

Figure 9.5-3 - (a.) Switched-capacitor, high pass circuit. (b.) Version of Fig. 9.5-3a

that constrains the charging of C 1 to the φ2 phase.

α1C

α2C

Transfer function:

It can be shown that,

V out V in

= -s“ R2”C 1

s” R2”C 2+1 ≈ - sT α 1C/ α 2C

sTC/ α 2C +1 = -

sT α 1 / α 2sT/ α 2 +1

= -sT α 1

sT + α 2 = -

sα 1s + α 2 / T

Equating the above to the general first-order H(s) gives the design equations as

a1 = α 1 and α 2 / T = b0

Solving for α 1 and α 2 gives

α 1 = a1 and α 2 =b0T =b0

f c



55/60


FIRST-ORDER, ALLPASS CIRCUIT

+

-

vi(t )

φ1

φ1φ2

φ2

φ2

vo(t)

C

(b.)

φ1 φ1 φ2

φ2

+

-

vi(t )

φ1

φ1φ2

φ2

φ2

vo(t)

α1C C

(a.)

φ1 φ1 φ2α3C

Figure 9.5-5 - (a.) High or low frequency boost circuit. (b.) Modification of (a.) to simplify

the z-domain modeling

α2C α3C α2C

α1C

Transfer function:

Summing the currents flowing into the inverting input of the op amp gives

V out

V in = -

“ R2”

“ R1”

s“ R1”C 1+1

s“ R2”C 2+1 = -

α 1

α 2 sT α 3 / α 1+1

sT/ α 2+1 = -

α 3s + α 1 / T

s + α 2 / T

Therefore,

α 3 = a1, α 1 / T = a0 and α 2 / T = b0

or

a1 = α 3, α 1 = a0T =a0


b0

f c



56/60


EXAMPLE 9.5-2 - DESIGN OF A SWITCHED CAPACITOR BASS BOOST CIRCUIT

Find the values of the capacitor ratiosα 1, α 2, and α 3 using a 100kHz clock for Fig. 9.5-5 that willrealize the asymptotic frequency response shown in Fig. 9.5-7.

dB

20

01kHz 10kHz10Hz 100Hz

FrequencyFigure 9.5-7 - Bass boost response for Ex. 9.5-2.

Solution

From the previous results, we can write the all-pass transfer function approximately as,

H (s) ≈ -sT α 3 + α 1sT + α 2

= -α 1α 2

sT α 3 / α 1 - 1

sT/ α 2 + 1

From Fig. 9.5-7, we see that the desired response has a dc gain of 10, a right-half plane zero at 2πkHz and a pole at -200π Hz. Thus, we see that the following relationships must hold.

α 1α 2

= 10 ,α 1

T α 3 = 2000π , and

α 2T

= 200π

From these relationships we get the desired values as

α 1 =2000π

f c, α 2 =

2 0 0π f c

, a n d α 3 = 1



57/60


PRACTICAL IMPLEMENTATIONS OF THE FIRST-ORDER CIRCUITS

Most practical implementations of switched capacitor circuits are fully differential as shown below.

+

-

vi(t )

φ1

φ1φ2

φ2

φ2

vo(t)C 1

C

(a.) (b.)

Figure 9.5-8 - Differential implementations of (a.) Fig. 9.5-1, (b.) Fig. 9.5-3, and (c.) Fig. 9.5-5.

φ1 φ1

φ2α2C

vo(t )

+

-

C

φ1 φ1

φ2 φ2

φ1 φ2

+

-

+

-

vi(t )

φ2

φ2

vo(t)

C

φ1 φ1

φ2

vo(t )

+

-

C

φ1 φ1

φ2 φ2

φ2

+

-

+

-

vi(t )

φ1

φ1φ2

φ2

φ2

vo(t)

C

(c.)

φ1 φ1φ2

vo(t )

+

-

C

φ1 φ1

φ2 φ2

φ1 φ2

+

-

φ2

φ2α2C

α1C

α1C

α2C

α2C

α1C

α1C

α2C

α2C

α1C

α1C

α3C

α3C

Comments:

• Differential operation reduces clock feedthrough, common mode noise sources and enhances thesignal swing.

• Differential operation requires op amps or OTAs with differential outputs which in turnrequires a means of stabilizing the output common mode voltage.



58/60


ANTI-ALIASING IN SWITCHED CAPACITOR FILTERS

A characteristic of circuits that sample the signal (switched capacitor circuits) is that the signalpassbands occur at each harmonic of the clock frequency including the fundamental.

T(jω)

T(j0)T(jωPB)

ωPB00

ω

Figure 9.7-28 - Spectrum of a discrete-time filter and a continuous-time

anti-aliasing filter.

-ωPB ωc 2ωc

ωc+ωPBωc-ωPB 2ωc-ωPB 2ωc+ωPB

Anti-Aliasing Filter

Baseband

The primary problem of aliasing is that there are undesired passbands that contribute to thenoise in the desired baseband.



59/60


NOISE ALIASING IN SWITCHED CAPACITOR CIRCUITS

In all switched capacitor circuits, a noise aliasing occurs from the passbands that occur at theclock frequency and each harmonic of the clock frequency.

, ,

, ,

f 0.5 f c f c f B f sw-f B

f c-f sw

f c+f B f c-f B

f c+f

sw

Magnitude

0

Noise Aliasing

,

,

From higher bands

Baseband

Figure 9.7-31 - Illustration of noise aliasing in switched capacitor circuits.

It can be shown that the aliasing enhances the baseband noise voltage spectral density by a factor of 2 f sw / f c. Therefore, the baseband noise voltage spectral density is

e BN 2 = kT/C f sw

x

2 f

sw f c

= 2kT f cC volts2 /Hz

Multiplying this equation by 2 f B gives the baseband noise voltage in volts(rms)2. Therefore, the

baseband noise voltage is

v BN 2 =

2kT

f cC

( )2 f B =2kT

C

2 f B

f c

=2kT / C

OSR volts(rms)2

where OSR is the oversampling ratio.



60/60


SUMMARY

• Switched capacitor circuits have reached maturity in CMOS technology.

• The switched capacitor circuit concept was a pivotal step in the implementation of analog signalprocessing circuits in CMOS technology.

• The accuracy of the signal processing is proportional to capacitor ratios.

• Switched capacitor circuits have been developed for:

AmplificationIntegration

Differentiation

Summation

Filtering

Comparing

Analog-digital conversion

• Approaches to switched capacitor circuit design:

Oversampled approach - clock frequency is much greater than the signal frequency

z-domain approach - specifications converted to the z-domain and directly realized, canoperate to within half of the clock frequency (not covered in the above notes)

• Clock feedthrough and kT/C noise represent the lower limit of the dynamic range of switchedcapacitor circuits.

Documents

Switch Cap01