Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems

G. Berry, VLSI'2004 synchronous tutorial, 3 - 1© Esterel Technologies, 2003

Chief Scientist

www.esterel-technologies.comGerard.Berry@esterel-technologies.com

Gérard Berry

Part 3: semantics and synthesis

Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems


Agenda - Part 3Semantics and Synthesis

• The Esterel kernel

• Mathematical semantics

• Circuit synthesis

• Sequential optimization

• Software synthesis









nothing empty statement

pause wait next tick

emit S emit S for this instant

if S then p else q end test S at this instant

suspend p when S stall p for the instant if S

p ; q start q when p terminates

loop p end restart p when terminated

p || q run p and q concurrently

trap T in p end declare exit label T in p

exit T exit trap T construct

signal S in p end declare S local in p

The Pure Esterel Kernel


trap T in ; if S then exit T end

end

await S

=loop pauseend

halt

= loop pause end

Bootstraping of other statements


loop

end

loop p each S

=

Synthesis algorithms may choose to mapstatements to circuits directly (for optimization)

abort p; loop pause endwhen S

Bootstraping of other statements









nothingpauseemit Spresent S then p else q endsuspend p when Sp; qloop p endp || qtrap T in p endexit Tsignal S in p end

The Pure Esterel Kernel

01! ss ? p, qs pp; qpp | q{p} pk, k > 1p \ s

U

*


• Behavioral Semantics: logical consistency A signal is present if and only if it is emitted Reactivity and determinism required

• Constructive Semantics: logical constructiveness Explain why signals are present or absent Reactivity and determinism implied

• Operational Semantics: microsteps

Constructive = Operational < Behavioral

Mathematical Semantics


pE

E’ kp’

received signals

emitted signals completion code

Broadcasting : E’ EU

0 : termination1 : waiting2 : exiting one trap level3 : exiting two trap levels

k

The Behavioral Semantics


!sE

{s} 00

kE

0 k 0

(for k=0, k=1, k>1)


s ? p, qE

E’ k p’

s E pE

E’ kp’

s ? p, qE

F’ l q’

s E qE

F’ lq’


pE

E’ 0p’

E’ 0s p U 0 E

E

E' ks p U s p' U

pE

E’ kp’ k = 0

with s p' = {( s ? 1 , 2) } ; s p' U U*


pE

E’ 0p’ q

E

F’ lq’

p ; qE’ U F’ l

q’E

pE

E’ kp’ k = 0

p ; qE’ k

p ’ ; qE


pE

E’ kp’ q

E

F’ lq’

p | qE

E’ U F’ max(k,l) p’ | q’

pE

E’ kp’ k = 0

pE’ k

p’ ; pE* *


{p}E

E’ 00

pE

E’ kp’ k = 0 or k = 2

{p}E

E’ k{p’}

pE

E’ kp’ k = 1 or k > 2

k = 1 if k=1, k-1 if k>2


E

pE

E’ kp’

E’ k p p'

0 = 0 1 = 1 k = k+1 if k >1


p \ sE

E’ k p’ \ s

pE U {s}

E’ U {s} kp’

p \ sE

E’ k p’ \ s

EE’ k

p’s E s E' p

Unique solution => determinismBut no solution or several solutions possible!









Initiated by J. Vuillemin and P. Bertin (DEC)

Esterel v4 (1992) - acyclic circuits Limited causality - users complain!

Esterel v5 (1996) - cyclic circuits Constructive causality

Almost structural but reincarnation difficult

Translation into Boolean Circuits


Basic syntax directed translation scheme

Each statement p corresponds to a box:

GO

RES

SUSP

KILL

SEL

K0

K1

K2...

E E'

p

Exclusive relation:GO # RES # SUSP

– E and E’: signals received and emitted– GO: start p (first cycle)– RES: continue from the previous state– SUSP: freeze for a cycle (keep registers)– KILL : reset registers– SEL: at least one register set = statement

alive– Ki : 1-hot encoded completion code

• K0: normal terminate• K1: pause for a cycle• K2,K3,… - exit enclosing traps


KILL

RES

K0SUSP

GO K1

SEL

Circuit for 1 (pause)


Circuit for abort p when s

GO

RES

SUSP

KILL

SEL

K0

K1

K2

...

E E'

RES

SUSP

s

K0

GO

KILL

SEL

K1

K2

E E'

p


GO

RES

SUSP

KILL

SEL

K0

K1

K2

...

E E'

P

GO

RES

SUSP

KILL

SEL

K0

K1

K2

...

E E'

Q

E'

SEL

K1

K2

GO

RES

SUSP

KILL

K0

E

Circuit for sequencing P; Q


GO

RES

SUSP

KILL

SEL

K0

K1

K2

E E'

K3

...

P

GO

RES

SUSP

KILL

SEL

K0

K1

K2

E E'

K3

...

Q

LEM

L0

L1

L2

L3

IN_KILL

REM

R0

R1

R2

R3

KILL

K0

K1

K2

K3

S Y N C H R O N I Z E R

E'

K0

K1

K2

K3

SEL

GO

GO

GO

RES

SUSP

E

KILL

Circuit for P||Q


LEM

REM

L0

R0 R1

L1 L2

R2

L3

R3

K0 K1 K2 K3

IN_KILLKILL

The parallel synchronizer


Circuit for abort p when s

GO

RES

SUSP

KILL

SEL

K0

K1

K2

...

E E'

RES

SUSP

s

K0

GO

KILL

SEL

K1

K2

E E'

p


Syntax directed translation by example

GO

RES

Addr

SEL

K0

loop

abort

{await Addr || await Data} ;

call Write (?Addr, ?Data) ;

await Latency times tick

when Replay

end loop


GO

RES

Addr

Data

loop

abort



await Latency tick

when Replay

end loop



GO

RES

Addr

SEL

K0

Data Write(…)

loop

abort



await Latency tick

when Replay

end loop



GO

RES

Addr

SEL

Data Write(…)

C:=LatencyDSZ C

K0



Replay

Addr

Data Write(…)

C:=LatencyDSZ C

0 1










• Build the netlist good start, but too fat

• Remove redundant registers not too many, just the fat syntactic don’t care (group-hot) reachable states

• Optimize the logic depth for hardware area for software

Implementation : SIS 1.3 + TiGeR

Sequential Optimization Scheme


Lots of registers, lots of gates…...

B

Automata to circuits, bad solution 1 one-hot encoding


• for n states, log(n) registers are enough

• but combinational logic needs to encode / decode states

2log(n) = n combinational gates worst case

+ very sensitive to the actual encoding of states

only n! permutations to check...

no good heuristics….

Automata to circuits, bad solution 2 dense encoding


R

I Ocombinational logic

state registers


Structural State Encoding

• 1-hot encoding : n regs. does not scale - register explosion

• Minimal encoding : log n regs. does not scale - logic explosion

• Structural encoding from Esterel one register per explicit delay does scale good register / logic compromize easy to optimize


• Detect registers that are always equal or opposite

• Detect registers that are functions of other registers for all reachable states => logic

• Multiplex registers that are exclusive over time

On large hierarchical FSMsvery good register / logic ratio

Sequential optimization algorithms


Esterel : Write Things Once

loop [ await A || await B ] ; emit Oeach R

One register per explicit delay


loop [ await A || await B ] ; emit Oeach R

0 1 0A? B?

O!

R?

Concurrent threads => independent groupssequencing => group-hot1-hot: 4bitsLog: 2bitsgroup-hot: 3bits - scales best.

1 1 0

1 0 0

0 0 1

1

1

1

0

Group-hot state encoding


F

R0 = 0

R1 = R0 U F(R0)

R2 = R1 U F(R1)

....

RSS = U Ri

compute using BDDs

but.... BDD(F) explodes!

key: use Ri as a simplifier for BDD(F)

(Madre, Coudert, Touati)

Efficient calculation of reachable states


BDD simplification by care sets

ED

F

Ri

Gsmaller BDD

G = F on Ri

Ri+1 = Ri U F(Ri)

Ri+1 = Ri U G(Ri)


Logic simplification by care sets

ED

F

RSS

Gsmaller, faster

G = F on RSS


Functional redundancy elimination

Register Ri is cheaply redundant if it can be replaced by a small function of the other registers

Necessary and sufficient condition:

RSS(Ri0) RSS(Ri 1)

Replacement function :

either RSS(Ri0) or RSS(Ri 1)

Good if either function is small


Optimization using SIS

WRISTWATCH pi= 8 po=92 nodes=462 latches=35lits(sop)= 990 lits(fac)= 990Total number of levels = 29

initial

speed optimization

WRISTWATCH pi= 8 po=92 nodes= 97 latches=12lits(sop)= 406 lits(fac)= 366Total number of levels = 3

WRISTWATCH pi= 8 po=92 nodes= 98 latches=11lits(sop)= 195 lits(fac)= 195Total number of levels = 15

area optimization


Exclusive Latches Multiplexing1

#

||

||

#

#

can replace RSS by ORSS(over-approximation)

computed from group-hotserial / parallel structure


Multiplexing registers

|| ||

#

not necessarily a good idea....

demultiplexer









Software Compilers• Automata based

– Esterel program specifies a finite state machine– Code this FSM in C– Esterel V3 compiler (INRIA/CMA, 1992)– The fastest code, but does not scale

• Netlist based– Esterel program can be mapped to logic netlist– Sort the netlist and print as C code: one cycle

computation require one pass through the netlist – Esterel v5 compiler – Scales well (linear from the program size), but

relatively slow since computes all equations even if not needed in a cycle

– V7 extends to arrays with mapping to for loops


Very fast C code generation

• S. Edward’s (Synopsys), D. Weil-E. Closse (France Télécom) D. Potop (CMA) fancy static scheduling of concurrency graphs (CCFGs)


Hierarchical encoding translation

Columbia University compiler

1


loop abort await A ; emit X; pause; emit Y; await B || await C ; emit Z ; pause when D ; pause; emit Q; await Eend loop

;

|| Epause

A pause B

; ;

C pause


s0

|| Epause

A pause B

s1

s2

C pause

• Sequential thread encoding group “si”• Degrees of freedom

– Encoding for each group (log, 1-hot, group-hot, etc)– Sharing between sequential groups– Sequential bits for terminals vs for other nodes

Hierarchical encoding translation


Challenges in code generation

• Better mapping of circuits to C codecan we get better than CCFG-base techniques?

• Language evolution : Esterel Studio v4.0

combining data flow and control flow

different compiling / optimization techniques

bit arrays and number encoders

non-trivial for C code (scheduling - Halbwachs et. al.)

non-trivial for optimization

• Better C generation from combinationally cyclic programsoccur naturally, conceptually efficient


Software Compilers• Discrete-Event Based

– Partition Esterel program into basic blocks – Dispatch them by a fixed scheduler– Much faster than netlist based, since run only those blocks that

contributes to a cycle computation– SAXO-RT [Weil et al. 2000]

• Program dependency graph based– Translate Esterel program to a concurrent control-flow graph– Analyze static data dependencies and schedule– Generate sequential CFG based on the schedule and translate to C– Somewhat faster than discrete-event, but could not handle false

combinational cycles [ Edwards, 2000, Synopsys ]– [Potop-Butucaru, 2003] optimized based on a different internal

representation and static analysis


Challenges of implementing v7 • Array / replication handling : 2 modes

– compile-time expansion to element-level (bit, int, etc)

expensive, but can be deeply optimized– no expansion, generates arrays and loops in C/HDL

much more tricky, but keeps object code size linear

• Numbers / bitvectors handling (ongoing)– all arithmetic operations fully exact, no bits dropped– arbitrary precision, full control on implementation size– multiple numbering systems (binary, onehot, Gray, user-

defined), semantics encoding-independent– Completely identical behavior in C and HDL


Conclusion of part 3

• Semantics is the key - cannot be compromized

• Current semantics technology OK for Esterel

• Synthesis / compilation follows directly

from semantics

• Other issues: traceability, etc.: see demos

Documents

Synchronous Methodology for Hardware, Software, and Mixed Embedded Systems