System-Level Design MethodsSystem-Level Design Methodsfor Low-Energy Architectures for Low-Energy Architectures

Containing Containing Variable Voltage ProcessorsVariable Voltage Processors

Lund Institute of Technology

Flavius Gruian

<Flavius.Gruian@cs.lth.se>

Embedded Systems DesignLaboratory

04/19/23 PACS2000 2(13)

Presentation OutlinePresentation Outline

• Problem Description• Our view of an energy efficient

system-level design flow • Two Approaches:

– Speed-up and Stretch– Eye-on-Energy

• Experiments• Conclusion

04/19/23 PACS2000 3(13)

Energy vs. Delay Energy vs. Delay on Variable Supply Voltage on Variable Supply Voltage

ProcessorsProcessors

Task Energy

Task Execution Time

The task executes all its N cycles at V1:E = NEV1

The task executes all its N cycles at V1:E = NEV1

The task executes partly at V2 and partly at V3:E = xEV2 + (N-x)EV3

The task executes partly at V2 and partly at V3:E = xEV2 + (N-x)EV3

0

0.2

0.4

0.6

0.8

1

Cycle Energy Cycle Length

norm

alize

d v

alu

es

V1 V2 V3

Sample characteristics fora three supply voltage

processor

04/19/23 PACS2000 4(13)

Scheduling Scheduling on Variable Supply Voltage on Variable Supply Voltage

ProcessorsProcessors

P1

P2

bus

P1P2

Task-graph

P1

P2

bus

Single Vdd

Ideal case

P1

P2

bus

Dual Vdd case

Design problem: minimize E while

keeping the deadline

04/19/23 PACS2000 5(13)

Specification(task-graph)

Constraints(deadline)

ResourcePool

Assigned & Scheduled Task-Graph

System-Level Design Flow for Low System-Level Design Flow for Low EnergyEnergy

• minimize energy under time and resource constraints

Evaluate

satisfactory

Focu

s o

n L

ow

En

erg

y

explore

Schedule

Generate Assignment[Simulated Annealing]

• tightly coupled assignment and scheduling

04/19/23 PACS2000 6(13)

Simulated Annealing for AssignmentSimulated Annealing for Assignment

Why SA?– classic heuristic, easy to implement– highly tunable

Implementation issues:– neighborhood:

random(task).processor = random(processor)

– cost:• quality measure of the final step solutions• fast to compute (ms)

04/19/23 PACS2000 7(13)

The “Speed-up and Stretch” Design The “Speed-up and Stretch” Design FlowFlow

• ad hoc method• minimize the schedule length

in the assignment step• list-scheduling with critical-

path priority as a core scheduling technique

• the schedule is scaled in the final step

Schedule andStretch

Generate AssignmentSA

Cost function:Schedule length

List-SchedulingPriority: CP

conventional design algorithms no information about the energy until the end!

04/19/23 PACS2000 8(13)

LEneS: Low-Energy SchedulingLEneS: Low-Energy Scheduling

• list-scheduling• energy consumption as priority• dynamic priority recalculation• loose deadlines: scales the tightest schedule• tight deadlines: stretches tasks from the non-

critical path whenever possible

uses energy informationtoo slow to be used in a SA loop

04/19/23 PACS2000 9(13)

The “Eye-on-Energy” Design FlowThe “Eye-on-Energy” Design Flow

uses estimated energy as feedback

not much more time consuming than S&S

indirect feedback - estimates

special scheduling method

Generate AssignmentSA

Cost function:Estimated Energy

ScaledLEneS

Tune the Estimator

Schedule

04/19/23 PACS2000 10(13)

Eest = a(Emax/Pr)(Tmin/Treq)2 + bE + c

Processor Energy Load

Deadline Load

Processor Energy Mean Deviation

EonE: The Energy EonE: The Energy EstimatorEstimator

• a, b, and c: – task-graph dependent– tuned by regression

• fast evaluation (slowest is Tmin)

• under 10% avg. deviation from E final values

04/19/23 PACS2000 11(13)

Experiments: EonE vs. S&SExperiments: EonE vs. S&S

• hundred random graphs (20 nodes)• max four processors (four supply voltages)

-10

0

10

20

30

40

50

0 25 50 75 100

deadline extension in %

Energ

y s

aved b

y E

onE v

s. S

&S in %

EonE gets in average ~15% lower energy

04/19/23 PACS2000 12(13)

Experiments: OFDExperiments: OFD

• 32 tasks on DSPs with four Vdd• 12.5Hz, 78x120 pixels

0

50

100

2

6.25 Hz3 4 2

8.33Hz3 4Processors

En

erg

y co

nsu

mp

tio

n

Rate

Single Vdd S&S EonE

• >50% energy at half rate (6.25Hz)

• higher parallelism allows lower energy consumption

04/19/23 PACS2000 13(13)

ConclusionsConclusions

• Two design approaches for low-energy systems containing variable Vdd processors– Speed-up and Stretch (simple, but efficient)– Eye-on-Energy (most efficient)

• Schedule-driven assignment (using SA)• Experiments:

– up to 50% energy savings for 50% deadline extension

– performance vs. low-energy trade-off– cost (processor number) vs. low-energy trade-off