Technology and characterization of GaN-HEMT devices: high

UNIVERSIDAD POLITÉCNICA DE MADRID

ESCUELA TÉCNICA SUPERIOR DE

INGENIEROS DE TELECOMUNICACIÓN

Technology and characterization of

GaN-HEMT devices: high

temperature and trapping effects

AUTHOR: Sara Martín Horcajo

Electronic engineer

SUPERVISOR: Fernando Calle Gómez

2014

sm14603

Text Box

s

TESIS DOCTORAL: Technology and characterization of GaN-HEMT devices: high

temperature and trapping e�ects

AUTORA: Dña. Sara Martín Horcajo

DIRECTOR: Prof. Dr. Fernando Calle Gómez

El tribunal nombrado por el Mgfco. y Excmo. Sr. Rector de la Universidad

Politécnica de Madrid, el día ......... de ........................... de 2015, para juzgar la

Tesis arriba indicada, compuesto por los siguientes doctores:

Dr. ........................................................................................(PRESIDENTE)

Dr. .........................................................................................(VOCAL)

Dr. .........................................................................................(VOCAL)

Dr. ..........................................................................................(VOCAL)

Dr. ..........................................................................................(SECRETARIO)

Realizado el acto de lectura y defensa de la Tesis el día .......... de ...........................

de 2015 en ............... acuerda otorgarle la cali�cación de: ............................

El Presidente:

El Secretario:

Los Vocales:

sm14603

Text Box

s

A mis padres y hermanos.

A mi abuelo Abilio y a mi sobrina Valeria.

A Nanin.

i

Acknowledgments

Esta sección está dedicada a todas aquellas personas que han contribuido al desarro-

llo de esta tesis, muchas gracias por vuestra ayuda y apoyo. Me gustaría agradecer a

mi director de tesis, Prof. Fernando Calle, por brindarme la oportunidad de realizar

la tesis en el ISOM y de colaborar en varios proyectos de investigación. Querría dar

las gracias a todas las personas con las que he trabajado en los proyectos RUE y

AEGaN, en especial a la gente del CNM, la Universidad de Valencia y el CEI de

la Universidad Politécnica de Madrid, gracias por vuestro buen hacer y por todo

lo que he aprendido durante nuestra colaboración. Mi agradecimiento al grupo de

HEMTs del ISOM, en especial a Roberto Cuerdo y Dra. Mª Fátima Romero, que

me iniciaron en el procesado y caracterización de dichos dispositivos; a Dr. Marko

Tadjer por realizar el procesado de los dispositivos en el NRL; y a Dr. Ashu Wang,

por mejorar la calidad de mis experimentos con sus simulaciones.

Me gustaría dar las gracias a la gente que forma el departamento de Ingeniería

Electrónica de la ETSI de Telecomunicación, en especial a Mariano, que siempre

me atendió con una sonrisa, y a Luis García, por preocuparse de que en el despacho

C-206 todo funcionara correctamente. Especial mención se merecen los técnicos del

ISOM, Óscar y Fernando, gracias por prestarme vuestra ayuda de manera incon-

dicional, independientemente de cual fuera la temática, y por soportar mis quejas

sobre la temperatura de la sala de eléctricos; Alicia y David, por vuestro apoyo en

el procesado de los transistores; pero sobre todo a Maika, que siempre ha puesto su

máxima dedicación y empeño en esta difícil tarea. Agradecer también a Montse y

a Isidoro por ayudarme con el papeleo y resolver mis dudas.

Gracias a mis compañeros del ISOM. En primer lugar gracias a los doctoran-

dos por compartir conmigo estos años en los que hemos vivido momentos compli-

cados en los que parecía que no avanzábamos y nos hemos apoyado unos a otros, a

Steven, a Antonio, a Johanna y su carácter argentino, a Víctor por nuestras con-

versaciones sobre fútbol y Juego de Tronos, a Ana pequeña por su sonrisa y porque

ambas sabemos lo que signi�ca �al mal tiempo buena cara�. Algunos ya marcharon

pero siguen en mi memoria, Miguel Montes y su humor ingenioso, Sergio, Juan

Pereiro, Fernando González Posadas, Álvaro, Eugenio y Raquel, etc. A los doctores

Ana Bengoechea, Zarko, Jorge, Gonzalo y Javi y a los más senior, Adrián, Álvaro

de Guzmán, Mar, y Marco Maicas. Mis agradecimientos a las personas del grupo de

los magnéticos, principalmente a la Dra. Rocío Ranchal y a Manuel Abuin por las

ii

horas compartidas en la sala de eléctricos mientras medíamos. Especial mención a

mis compañeros de despacho, a Manu por su chispa, mis chicas del C-206 Mariajo

y Gmitic, Verónica y Ashu, la zona internacional del despacho, a Alberto, gracias

por escucharme y ayudarme con el arreglo y la puesta a punto de los equipos, y a

Tommaso, por todas las conversaciones en las que intentábamos arreglar el mundo.

Debo agradecer también a Juan G, juntos nos embarcamos en esta y en otras

muchas aventuras, y junto a Maika y Francesca hemos compartido muchas comidas,

problemas y alegrías, gracias a los tres por convivir conmigo durante gran parte de

estos años, y gracias Maika por tu apoyo y cariño en esta última etapa de mi tesis.

Gracias a Prof. Martin Kuball que me ha dado la oportunidad de realizar

un post-doc en Bristol, lo cual me ha servido de motivación para darle el último

empujón a la tesis; y a Tommaso y Noemí por acogerme en su casa en Bristol, donde

terminé de escribir la memoria de la tesis; y a mis compañeros de piso Hussein

y Spiros, que me han animado durante la preparación de la presentación de la

misma. Mi agradecimiento a Tommaso y Salva por sus comentarios, los cuales me

han ayudado a mejorar la versión �nal de la memoria; y a Alberto y Maika por

ayudarme con los trámites de la defensa de la tesis.

Quiero agradecer a la familia de mi novio, a MariJose y Mariano, a la tía

Esther y en especial a la abuela Paquis, por cuidarme y mimarme como una nieta

más. Mil gracias a mis amigos por sus buenas palabras de ánimos, aunque a veces

formularan esas temidas preguntas: ¾tesis, qué es eso de la tesis?, ¾y cuándo acabas

la tesis?. Especial recuerdo a mi amigo Ibán que nos dejó de una manera repentina

y triste en el primer año de tesis.

Mis últimas palabras son para las personas más importantes, para mi familia

y mi novio. Para mi abuela María que nos dejó en el verano del 2010 y mi abuelo

Valeriano. Para mi abuela Petra, aún resuena en mi memoria la frase que me decía:

�estudia Sarita, estudia�. Para mi abuelo Abilio que nos dejó en Junio del 2011,

recuerdo cuando me veía leyendo algún artículo y me preguntaba: �¾y esto que

estudias no se acaba nunca?�, pues abuelo, esta etapa está a punto de terminar.

A mis padres y hermanos, porque todo lo que soy os lo debo a vosotros. Gracias

Nanin, por crecer juntos, por apoyarme y por hacer de mis sueños y mis metas tus

sueños y metas. Y mil gracias a mi sobrina y ahijada Valeria, y a sus padres, a mi

hermano Alfonso y mi cuñada María, por darme este pedacito de felicidad, porque

la sonrisa de mi niña me ha dado la fuerza que necesitaba para cerrar esta etapa de

mi vida.

iii

Abstract

GaN-based high electron mobility transistors have been under extensive research

due to the excellent electrical properties of GaN and its related alloys (high carrier

concentration, high mobility, and high critical electric �eld). Although these devices

have been recently included in commercial applications, some performance and reli-

ability issues need to be addressed for their expansion in the market. Some of these

relevant aspects have been studied during this thesis; for instance, the fabrication

of enhancement mode HEMTs, the device performance at high temperature, the

self-heating and the charge trapping.

Enhancement mode HEMTs have become more attractive mainly because

their use leads to a signi�cant reduction of the power consumption during the

stand-by state. Moreover, they enable the fabrication of simpler power ampli�er

circuits and high-power switches because they allow the elimination of negative-

polarity voltage supply, reducing signi�cantly the circuit complexity and system

cost. In this thesis, di�erent techniques for the fabrication of these devices have

been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices

and two di�erent �uorine-based treatments (CF4 plasma and F implantation). Re-

garding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN

grown on di�erent substrates: Si, sapphire, and SiC. The total recess of the barrier

was achieved after 3 min of etching in devices grown on Si substrate. This suggests

that the etch rate can critically depend on the dislocations present in the structure,

since the Si exhibits the highest mismatch to GaN. Concerning the �uorine-based

treatments, a post-gate thermal annealing was required to recover the damages

caused to the structure during the �uorine-treatments. The study of the threshold

voltage as a function of this annealing time has revealed that in the case of the

plasma-treated devices it become more negative with the time increase. On the

contrary, the threshold voltage of implanted HEMTs showed a positive shift when

the annealing time was increased, which is attributed to the deep F implantation

pro�le. Plasma-treated HEMTs have exhibited better DC performance at room

temperature than the implanted devices. Their study at high temperature has re-

vealed that their performance decreases with temperature. The initial performance

measured at room temperature was recovered after the thermal cycle regardless of

the �uorine treatment; therefore, the thermal e�ects were reversible.

Thermal issues related to the device performance at di�erent temperature

iv

have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with

di�erent cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed

from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the

device performance since HEMTs with this cap layer have exhibited the highest

drain current and transconductance values, the lowest on-resistance, as well as the

best o�-state characteristics. Moreover, the evaluation of thermal stress impact on

the device performance has con�rmed the robustness of devices with in situ cap.

Secondly, the high temperature performance of InAlN/GaN HEMTs with dif-

ferent layouts and geometries have been assessed. The devices under study have

exhibited an almost linear reduction of the main DC parameters operating in a

temperature range from room temperature to 225°C. This was mainly due to the

thermal dependence of the electron mobility, and secondly to the drift velocity de-

crease with temperature. Moreover, HEMTs with large gate length values have

exhibited a great reduction of the device performance. This was attributed to the

greater decrease of the drift velocity for low electric �elds. Similarly, the increase of

the gate-to-drain distance led to a greater reduction of drain current and transcon-

ductance values. Therefore, this thermal performance degradation has been found

to be dependent on both the gate length and the gate-to-drain distance.

It was observed that the very high power density in the active region of

these transistors leads to Joule self-heating, resulting in an increase of the device

temperature, which can degrade the device performance and reliability. A simple

electrical method have been developed during this work to determine the channel

temperature. Furthermore, the application of this technique together with the

performance of electro-thermal simulations have enabled the evaluation of di�erent

aspects related to the self-heating. For instance, the in�uence of the substrate have

been con�rmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs

grown on SiC substrate have been con�rmed to exhibit the lowest self-heating e�ects

thanks to its highest thermal conductivity. In addition to this, the distribution of

the generated heat in the channel has been demonstrated to be dependent on the

gate-to-drain distance. Besides the substrate and the geometry of the device, the

ambient temperature has also been found to be relevant for the self-heating e�ects,

mainly due to the temperature-dependent thermal conductivity of the layers and

the substrate.

Trapping e�ects have been evaluated by means of pulsed measurements in

AlGaN and InAlN barrier devices. AlGaN barrier HEMTs have exhibited a de-

v

crease in drain current and transconductance without measurable threshold voltage

change, suggesting the location of the traps in the gate-to-drain access region. On

the contrary, InAlN barrier devices have showed a drain current associated with

a positive shift of threshold voltage, which indicated that the traps were possibly

located under the gate region. Moreover, a signi�cant increase of the ON-resistance

as well as a transconductance reduction were observed, revealing the presence of

traps on the gate-drain access region. On the other hand, the assessment of devices

with di�erent geometries have demonstrated that the trapping e�ects are more no-

ticeable in devices with either short gate length or the gate-to-drain distance. This

can be attributed to the fact that the length and the trap density of the virtual

gate are independent on the device geometry.

Finally, it can be deduced that besides the �nal application requirements, the

in�uence of the device geometry on the performance at high temperature, on the

self-heating, as well as on the trapping e�ects need to be taken into account during

the device design stage to achieve the optimal layout.

vi

Resumen

Los transistores de alta movilidad electrónica basados en GaN han sido objeto

de una extensa investigación ya que tanto el GaN como sus aleaciones presentan

unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de

portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido

en algunas aplicaciones comerciales, su expansión en el mercado está condicionada

a la mejora de varios asuntos relacionados con su rendimiento y �abilidad. Durante

esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la

fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura,

el autocalentamiento y el atrapamiento de carga.

Los HEMTs normalmente apagado o enhancement mode han atraído la aten-

ción de la comunidad cientí�ca dedicada al desarrollo de circuitos ampli�cadores y

conmutadores de potencia, ya que su utilización disminuiría signi�cativamente el

consumo de potencia; además de requerir solamente una tensión de alimentación

negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han

evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ata-

que húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN;

y tratamientos basados en �úor (plasma CF4 e implantación de F) de la zona de-

bajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de

InAl(Ga)N crecidas sobre sustratos de Si, SiC y za�ro. El ataque completo de la

barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se

puede deducir que la velocidad de ataque depende de la densidad de dislocaciones

presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red

con el GaN. En relación a los tratamientos basados en �úor, se ha comprobado que

es necesario realizar un recocido térmico después de la fabricación de la puerta para

recuperar la heteroestructura de los daños causados durante dichos tratamientos.

Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido

ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más

negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de

los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye

a la introducción de iones de �úor a niveles más profundos de la heterostructura. Los

transistores fabricados con plasma presentaron mejor funcionamiento en DC a tem-

peratura ambiente que los implantados. Su estudio a alta temperatura ha revelado

una reducción del funcionamiento de todos los dispositivos con la temperatura. Los

vii

valores iniciales de corriente de drenador y de transconductancia medidos a tempe-

ratura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que

dichos efectos térmicos son reversibles.

Se han estudiado varios aspectos relacionados con el funcionamiento de los

HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones

de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in

situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ

SiN presentaron los valores más altos de corriente drenador, transconductancia, y

los valores más bajos de resistencia-ON, así como las mejores características en

corte. Además, se ha con�rmado que dichos dispositivos presentan gran robustez

frente al estrés térmico.

En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN

con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción

casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta

225°C. Esto se debe principalmente a la dependencia térmica de la movilidad elec-

trónica, y también a la reducción de la drift velocity con la temperatura. Además,

los transistores con mayores longitudes de puerta mostraron una mayor reducción

de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más

considerablemente con la temperatura cuando el campo eléctrico es pequeño. De

manera similar, al aumentar la distancia entre la puerta y el drenador, el funciona-

miento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto,

se puede deducir que la degradación del funcionamiento de los HEMTs causada por

el aumento de la temperatura depende tanto de la longitud de la puerta como de

la distancia entre la puerta y el drenador.

Por otra parte, la alta densidad de potencia generada en la región activa de

estos transistores conlleva el autocalentamiento de los mismos por efecto Joule, lo

cual puede degradar su funcionamiento y �abilidad. Durante esta tesis se ha de-

sarrollado un simple método para la determinación de la temperatura del canal

basado en medidas eléctricas. La aplicación de dicha técnica junto con la realiza-

ción de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos

relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en

dispositivos sobre Si, SiC, y za�ro. Los transistores sobre SiC han mostrado menores

efectos gracias a la mayor conductividad térmica del SiC, lo cual con�rma el papel

clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la

geometría del dispositivo tiene cierta in�uencia en dichos efectos, destacando que la

viii

distribución del calor generado en la zona del canal depende de la distancia entre la

puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene

un considerable impacto en el autocalentamiento, lo que se atribuye principalmente

a la dependencia térmica de la conductividad térmica de las capas y sustrato que

forman la heterostructura.

Por último, se han realizado numerosas medidas en pulsado para estudiar el

atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y

de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han

presentado una disminución de la corriente de drenador y de la transconductancia

sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que

la posible localización de las trampas es la región de acceso entre la puerta y el

drenador. Por el contrario, la reducción de la corriente de drenador observada en

los dispositivos con barrera de InAlN llevaba asociado un cambio signi�cativo en la

tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo

de la puerta. Además, el signi�cativo aumento del valor de la resistencia-ON y la

degradación de la transconductancia revelan la presencia de trampas en la zona de

acceso entre la puerta y el drenador.

La evaluación de los efectos del atrapamiento de carga en dispositivos con di-

ferentes geometrías ha demostrado que dichos efectos son menos notables en aque-

llos transistores con mayor longitud de puerta o mayor distancia entre puerta y

drenador. Esta dependencia con la geometría se puede explicar considerando que

la longitud y densidad de trampas de la puerta virtual son independientes de las

dimensiones del dispositivo.

Finalmente se puede deducir que para conseguir el diseño óptimo durante la

fase de diseño no sólo hay que tener en cuenta la aplicación �nal sino también la in-

�uencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento

a alta temperatura, autocalentamiento, y atrapamiento de carga).

Contents

Acknowledgments i

Abstract iii

Resumen vi

Contents ix

List of Figures xiii

List of Tables xxv

1 Introduction 1

1.1 State of the art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 GaN-based heterostructures and applications . . . . . . . . . 2

1.1.2 High electron mobility transistors . . . . . . . . . . . . . . . . 11

1.1.3 Reliability and failure mechanisms . . . . . . . . . . . . . . . 19

1.2 Framework: RUE and AEGaN projects . . . . . . . . . . . . . . . . 28

1.2.1 RUE project . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.2.2 AEGaN project . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.3 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . . . 35

1.4 Dissertation organization . . . . . . . . . . . . . . . . . . . . . . . . . 36

2 Experimental techniques 39

2.1 Epitaxial growth and samples . . . . . . . . . . . . . . . . . . . . . . 39

2.2 Device fabrication and testing . . . . . . . . . . . . . . . . . . . . . . 41

2.2.1 Device layouts . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.2.2 Fabrication technology . . . . . . . . . . . . . . . . . . . . . . 43

ix

x CONTENTS

2.2.3 Checking of the processing steps . . . . . . . . . . . . . . . . 61

2.3 Electrical characterization . . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.1 Hall measurements . . . . . . . . . . . . . . . . . . . . . . . . 66

2.3.2 Capacitance-voltage . . . . . . . . . . . . . . . . . . . . . . . 67

2.3.3 DC characterization of HEMTs . . . . . . . . . . . . . . . . . 69

2.3.4 Pulsed characterization of HEMTs . . . . . . . . . . . . . . . 71

3 Contribution to the technology of enhancement-mode HEMTs 79

3.1 Introduction to E-mode devices . . . . . . . . . . . . . . . . . . . . . 79

3.2 Wet etching in InAl(Ga)N/GaN heterostructures . . . . . . . . . . . 82

3.2.1 Characterization of as-grown structures . . . . . . . . . . . . 83

3.2.2 Etching and post-characterization of structures . . . . . . . . 85

3.3 E-mode AlGaN/GaN HEMTs fabricated by �uorination . . . . . . . 89

3.3.1 Processing based on �uorine-based treatments . . . . . . . . . 89

3.3.2 Performance at high temperature . . . . . . . . . . . . . . . . 89

3.3.3 Thermal and time dependence of VTH . . . . . . . . . . . . . 96

3.4 Summary and conclusions . . . . . . . . . . . . . . . . . . . . . . . . 98

4 Performance of (InAl)GaN HEMTs at di�erent ambient temper-

atures 101

4.1 E�ect of di�erent cap layers: GaN, in situ SiN, and in situ SiN/GaN 101

4.1.1 Experimental details . . . . . . . . . . . . . . . . . . . . . . . 103

4.1.2 Characterization at di�erent Tamb . . . . . . . . . . . . . . . 104

4.1.3 Thermal stress . . . . . . . . . . . . . . . . . . . . . . . . . . 112

4.2 E�ect of di�erent layouts and geometries . . . . . . . . . . . . . . . . 117


4.2.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.2.3 Gate length, LG . . . . . . . . . . . . . . . . . . . . . . . . . 119

4.2.4 Gate-to-drain distance, LGD . . . . . . . . . . . . . . . . . . . 122


5 Self-heating 127

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.2 In�uence of the substrate . . . . . . . . . . . . . . . . . . . . . . . . 128

5.3 Electrical method proposed for Tchannel estimation . . . . . . . . . . 132

5.3.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

CONTENTS xi

5.3.2 Accuracy and Reproducibility . . . . . . . . . . . . . . . . . . 138

5.3.3 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.4 Device geometry in�uence . . . . . . . . . . . . . . . . . . . . . . . . 141

5.4.1 Gate width, WG . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.4.2 Gate length, LG . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.4.3 Gate-to-drain distance, LGD . . . . . . . . . . . . . . . . . . . 148


6 Trapping e�ects 155

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

6.2 Di�erent cap layers: GaN, in situ SiN, and in situ SiN/GaN . . . . . 157


6.2.2 Trapping e�ects at di�erent Tamb . . . . . . . . . . . . . . . . 158

6.2.3 Trapping e�ects after thermal stress . . . . . . . . . . . . . . 160

6.3 AlGaN and InAlN barrier devices on SiC . . . . . . . . . . . . . . . . 161


6.3.2 Assessment of trapping e�ects . . . . . . . . . . . . . . . . . . 165

6.3.3 Characterization of traps . . . . . . . . . . . . . . . . . . . . 168

6.3.4 Impact of LG and LGD . . . . . . . . . . . . . . . . . . . . . . 176


7 Conclusions and future work 185

7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

A Instrumentation developed 193

A.1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

A.1.1 Agilent 81150A . . . . . . . . . . . . . . . . . . . . . . . . . . 194

A.1.2 Yokogawa DLM2000 . . . . . . . . . . . . . . . . . . . . . . . 195

A.1.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

A.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

A.2.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

A.2.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

A.2.3 Flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

A.3 Assessment procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 200

xii CONTENTS

B Device summary 205

C List of contributions and collaborations 213

C.1 Peer reviewed articles . . . . . . . . . . . . . . . . . . . . . . . . . . 213

C.2 Conferences attended . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

C.3 Collaborations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Bibliography 219

List of Figures

1.1 The main applications of GaN-based materials [Mwr14]. . . . . . . . . . 2

1.2 Potential militar (black) and commercial (grey) application of GaN-

based HEMTs [Mis02]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 The distribution of atoms in zincblende and wurtzite structure [Wan06]. 6

1.4 The directions of spontaneous polarization in the N-face and Ga-Face

GaN wurtzite structure [Wan06]. . . . . . . . . . . . . . . . . . . . . . . 6

1.5 (a) Lattice constant di�erences for the (Al, Ga, In, N) system and the

resulting AlGaN/GaN structure [Mis02]. (b) Bandgap and piezoelectric

polarization versus the lattice constant for (Al, Ga, In, N) system [Wan06]. 8

1.6 (a) Total polarizations and (b) their e�ects on the 2DEG concentration

in AlGaN/GaN HEMT [Sac01]. . . . . . . . . . . . . . . . . . . . . . . . 10

1.7 Bandgap over the lattice constant of InN, AlN, GaN pointing out that

lattice-matched InAlN is obtained for an In content of 17% [Bah12]. . . 12

1.8 Scheme of a standard HEMT. . . . . . . . . . . . . . . . . . . . . . . . . 14

1.9 Band diagram of HEMT when (a) VGS= 0 V and (b) VGS ≤ VTH. . . 14

1.10 Output I-V characteristics of an ideal HEMT. ID.max corresponds to the

maximum ID at VGS= 0 V whereas VBD is the minimum VDS which

causes an anomalous device performance. The black dash line points

out the transition from linear to saturation region. . . . . . . . . . . . . 15

1.11 Transfer characteristics of E-mode devices and D-mode devices, used as

reference [Pal06a]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.12 Normally-o� AlGaN/GaN transistors fabricated by: (a) �uorine-treatment,

(b) p-type gate technology, (c) thinner barrier, and (d) gate-recess tech-

nology [Lu13]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

xiii

xiv List of Figures

1.13 Schematic cross section of an AlGaN/GaN HEMT, identifying the crit-

ical areas where the degradation can occur [Men08]. . . . . . . . . . . . 22

1.14 Dispersion in I-V characteristics of GaN-based HEMT under DC and

RF conditions due to the presence of traps [Alo12]. . . . . . . . . . . . . 23

1.15 Current collapse in GaN HEMTs I-V output characteristics (i) before

and (ii) after the application of VDS = 20 V [Kha04b]. . . . . . . . . . . 24

1.16 Output characteristics illustrating current collapse and the ID recovery

under illumination conditions for GaN MESFET [Bin97]. . . . . . . . . 25

1.17 Dependency of ID recovery on the light wavelength [Bin97]. . . . . . . . 25

1.18 (a) Location of the virtual gate in the device and (b) schematic repre-

sentation of the device including the virtual gate [Vet01]. . . . . . . . . . 26

1.19 I-V output characteristics of a device. ID decreases in the saturation

region as consequence of self-heating [McA09]. . . . . . . . . . . . . . . . 28

1.20 General purpose of RUE project [Mil11]. . . . . . . . . . . . . . . . . . . 33

1.21 The RUE proposal [Rue14]. . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.22 Diagram of the potential operating conditions (voltage, frequency, and

temperature) of the wide bandgap semiconductor devices involved in the

RUE project [Rue14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.1 Simpli�ed scheme of one cell of the PCM mask. . . . . . . . . . . . . . . 43

2.2 Scheme of one cell corresponding to the ISOM2010 mask. . . . . . . . . 44

2.3 Scheme of one cell corresponding to the NRL mask. . . . . . . . . . . . . 45

2.4 Flow chart of a standard device fabrication. . . . . . . . . . . . . . . . . 46

2.5 Surface cleaning procedure. . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.6 Electrical isolation procedure. (a) Optical lithography, (b) result of de-

veloping the pattern, and (c) structure after the dry etching. . . . . . . 47

2.7 Karl Suss KG UV photolithography system. . . . . . . . . . . . . . . . . 48

2.8 Schematics of (a) RIE and (b) ICP systems. . . . . . . . . . . . . . . . . 50

2.9 Procedure of ohmic contact formation. (a) Photolithography, (b) pho-

toresist developing, (c) metallization, (d) lift-o�, and (e) ohmic contact

after thermal annealing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.10 (a) E-beam evaporation system used at the ISOM facilites and (b)

scheme of an e-beam evaporation [Eng14]. . . . . . . . . . . . . . . . . . 55

2.11 (a) RTA system and (b) scheme of the two-steps thermal annealing. . . 55

2.12 Pictures of fabricated devices with (a) one and (b) two �ngers. . . . . . 56

List of Figures xv

2.13 Steps of Schottky contact fabrication: (a) Photolithography, (b) pho-

toresist developing, (c) metal evaporation, and (d) the result after lift-o�. 58

2.14 Scheme of the passivation step: (a) Passivation layer deposition, (b)

photolithography, (c) developing and (d) the resulting device after the

etching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2.15 Schematic of PECVD and (b) system used at ISOM. . . . . . . . . . . . 60

2.16 (a) Scheme and (b) picture of the electrical isolation test structure. . . . 61

2.17 I-V measurements setup: (a) Karl SussDC probe station and (b) Agilent

HP 4156C parameter semiconductor analyzer. . . . . . . . . . . . . . . . 62

2.18 (a) Scheme and (b) picture of a TLM. . . . . . . . . . . . . . . . . . . . 63

2.19 (a) Resistances involved, (b) Scheme of I-V and (c) equivalent circuit

for TLM measurements [Che14]. . . . . . . . . . . . . . . . . . . . . . . 64

2.20 (a) Illustration of RT and (b) representation of its measured values. . . . 64

2.21 (a) Scheme and (b) picture of a Schottky diode. . . . . . . . . . . . . . . 65

2.22 I-V curve of a Schottky diode. . . . . . . . . . . . . . . . . . . . . . . . . 65

2.23 (a) Scheme and (b) picture of a van der Pauw structure. . . . . . . . . . 66

2.24 Schematic diagram of the measurements performed in the van der Pauw

geometry for the ns and μH extraction. . . . . . . . . . . . . . . . . . . . 67

2.25 Setup for Hall measurements: (a) Creative Devices Inc. probe station

and (b) Agilent HP4145B semiconductor paramter analyzer. . . . . . . . 68

2.26 LCR meter used for the capacitance-voltage measurements. . . . . . . . 68

2.27 Janis high/low temperature probe station. . . . . . . . . . . . . . . . . . 69

2.28 Extraction of RON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.29 (a) Transfer characteristics and (b) transconductance for VDS = (0.1 V:

4.9 V: 9.9 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

2.30 Extraction of VTH from the transconductance plot. . . . . . . . . . . . . 71

2.31 (a) schematic and (b) illustration of the pulsed characterization system

developed during this dissertation. . . . . . . . . . . . . . . . . . . . . . 73

2.32 Pulse conditions for gate lag measurements. . . . . . . . . . . . . . . . . 74

2.33 (a) I-V output characteristics obtained under DC conditions and pulsing

the gate. (b) Comparison of I-V output characteristics varying τON[Men04]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2.34 Pulse conditions for the assessment of self-heating. . . . . . . . . . . . . 75

xvi List of Figures

2.35 Pulsed conditions for the assessment of trapping e�ects. The Q points

lead to the stress of the device applying (a) a very negative VGS(lower

than VTH) and (b) a very negative VGS together with a very high

VDS(typically ≤ 20 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

2.36 Conditions for transient measurements. . . . . . . . . . . . . . . . . . . 77

3.1 Conduction band schematic diagrams for (a) conventional D-mode Al-

GaN/GaN HEMT and (b) E-mode with �uorine-based treatment [Wan08].

81

3.2 Heterostructure of the InAl(Ga)N samples used in this experiment. . . . 83

3.3 Quaternary map which shows the composition of the three samples de-

termined by RBS. The black dash line indicates the LM compositions

[Bra14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.4 C-V pro�les obtained in the three as-grown samples which were mea-

sured at 10 KHz with an AC signal amplitude of 0.1 V [Bra14]. For

sample speci�cation refer to table 3.1. . . . . . . . . . . . . . . . . . . . 85

3.5 ns versus depth extracted from C-V measurements. In the case of sample

C no density of 2DEG was probed after 3 min-etching. As shown in the

inset, the revealed charge can possibly be due to inner defects [Bra14]. . 87

3.6 Illustration of the e�ect of the etching on the measured thickness by

XRD and C-V measurements. . . . . . . . . . . . . . . . . . . . . . . . . 88

3.7 Schematic of the processing of E-mode HEMTs: (a) mesa and ohmic con-

tacts formation; (b) gate area de�nition and F-treatment; (c) Schottky

contact formation; and (d) passivation by means of a SiN layer. . . . . . 90

3.8 ID and gm recovery after thermal annealing. Solid and empty symbols

correspond to before and after annealing, respectively. . . . . . . . . . . 91

3.9 Transfer characteristics and transconductance at VDS = 8 V for E-mode

devices fabricated by both �uorine-based treatment and D-mode HEMT

taken as reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.10 ID.max dependence on temperature for E-mode and D-mode devices when

VGS = VTH + 3.5 V. Solid and empty symbols correspond to the values

during and after TC, respectively. . . . . . . . . . . . . . . . . . . . . . . 93

3.11 Thermal dependence of gm.max for E-mode and D-mode devices when

VDS = 10 V. Solid and empty symbols correspond to the values during

and after TC, respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . 94

List of Figures xvii

3.12 IG dependence on temperature for E-mode and D-mode devices when

VDS = 20 V and VGS ≈ VTH - 2.5 V (approximately -6 V, and -3 V for

D-mode and E-mode devices, respectively). Solid and empty symbols

correspond to the values during and after TC, respectively. . . . . . . . 95

3.13 Thermal dependence of RON calculated as the inverse of the slope of the

ID vs VDS in the linear region when VGS = VTH + 3.5 V. Solid and

empty symbols correspond to the values during and after TC, respectively. 95

3.14 SIMS pro�les of three control HEMT samples implanted with 19F+ with

a 5·1012 cm-2 and 10-50 KeV energies [Tad11]. . . . . . . . . . . . . . . . 97

3.15 VTH of CF4-plasma and F implanted HEMTs as a function of annealing

time [Tad11]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.16 VTH as a function Tamb for research grade E-mode devices fabricated

by means of a CF4 plasma or a F ion implantation as well as for a

commercial EPC device. . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.1 Simpli�ed schemes of the device structures under study. . . . . . . . . . 103

4.2 I-V curves measured at di�erent Tamb in diodes fabricated on heterostruc-

tures with (a) GaN, (b) in situ SiN, and (c) in situ SiN/GaN cap layer. 105

4.3 I-V curves measured at RT during (line) and after (symbols) the thermal

cycle in diodes fabricated on heterostructures with: (a) GaN cap, (b) in

situ SiN, and (c) in situ SiN/GaN cap layer. . . . . . . . . . . . . . . . . 106

4.4 C-V curves measured at di�erent Tamb in diodes fabricated on het-

erostructures with: (a) GaN cap, (b) in situ SiN, and (c) in situ SiN/GaN

cap layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.5 C-V curves measured at RT during (line) and after (symbols) the ther-

mal cycle in diodes fabricated on heterostructures with: (a) GaN cap,

(b) in situ SiN, and (c) in situ SiN/GaN cap layer. . . . . . . . . . . . . 108

4.6 (a) ID.max and gm.max and (b) RON as a function of Tamb for devices

with di�erent cap layers: GaN, in situ SiN, and in situ SiN/GaN (LG= 3 μm, LGD = 2.5 μm, and WG = 100 μm). ID.max corresponds to the

maximum ID value at VGS = 0 V. RON was extracted from the ID - VDS

curve at VGS = 0 V. gm.max is the maximum gm value at VDS = 9.9 V. . 110

4.7 Thermal dependence of mobility [Zha11]. . . . . . . . . . . . . . . . . . 111

xviii List of Figures

4.8 ID.o� and IG.o� as a function of Tamb for devices with di�erent cap layers:

GaN, in situ SiN, and in situ SiN/GaN (LG = 3 μm, LGD = 2.5 μm,

and WG = 100 μm). ID.o� and IG.o� correspond to the values of ID and

IG, respectively, when the devices were biased in o�-state at VGS = -6

V and VDS = 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.9 (a) Idiode.invnormalized and (b) ΔVFB after di�erent thermal stress in de-

vices with di�erent cap layer: GaN, in situ SiN, and in situ SiN/GaN. . 113

4.10 (a) ID.maxnormalized, (b) RON

normalized, and (c) gm.maxnormalized calculated

after di�erent stress times for devices with di�erent cap layers: GaN, in

situ SiN, and in situ SiN/GaN. . . . . . . . . . . . . . . . . . . . . . . . 115

4.11 (a) ID.o�normalized and (b) IG.o�normalized after di�erent thermal stress in

devices with di�erent cap layer: GaN, in situ SiN, and in situ SiN/GaN. 116

4.12 Device heterostructures used for the assessment of the InAlN/GaN de-

vice performance at high temperature. . . . . . . . . . . . . . . . . . . 119

4.13 Multi�nger device performance at high temperature: (a) ID.max obtained

at VGS = 0 V; (b) gm.max measured at VDS = 9.9 V; and (c) RON

extracted from the ID - VDS curve at VGS = 0 V. Solid and empty

symbols correspond to the values obtained during the thermal cycle and

at RT after the thermal cycle, respectively. . . . . . . . . . . . . . . . . 120

4.14 Device performance at high temperature for devices with LGD = 15 µm,

WG = 100 µm, and variable LG: (a) ID.max obtained at VGS = 0 V; (b)

gm.max measured at VDS = 9.9 V; and (c) RON extracted from the ID -

VDS curve at VGS = 0 V. Solid and empty symbols correspond to the

values obtained during the thermal cycle and at RT after the thermal

cycle, respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.15 ID.max (square symbols) and gm.max (circular symbols) at 225°C normal-

ized by their values at RT as a function of LG. . . . . . . . . . . . . . . 122

4.16 Device performance at high temperature for devices with LG = 3 µm,

WG = 100 µm, and variable LGD: (a) ID.max obtained at VGS = 0 V; (b)

gm.max measured at VDS = 9.9 V; and (c) RON extracted from the ID -

VDS curve at VGS = 0 V. Solid and empty symbols correspond to the

values obtained during the thermal cycle and at RT after the thermal

cycle, respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.17 ID.max (square symbols) and gm.max (circular symbols) at 225°C normal-

ized by their values at RT, as a function of LGD. . . . . . . . . . . . . . 124

List of Figures xix

5.1 Device heterostructures grown on (a) sapphire, (b) Si, and (c) SiC. . . . 129

5.2 ID.max values for VGS = 0 V (solid symbols) and gm.max values for VDS

= 9.9 V (empty symbols) as a function of Tamb for devices grown on the

three di�erent substrates. Both magnitudes showed linear dependence

on Tamb (dot lines). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.3 (dID/dVDS)sat as a function of Tamb for devices grown on the three

di�erent substrates. (dID/dVDS)sat was calculated as the linear �t slope

of ID in the saturation region for VGS = 0 V. . . . . . . . . . . . . . . . 131

5.4 Normalized ID.max and (dID/dVDS)sat as a function of τON for devices

grown on the three substrates. (dID/dVDS)sat was calculated as the

linear �t slope of ID in the saturation region for VGS = 0.7 V. . . . . . . 132

5.5 Calibration step for a device grown on SiC. (a) ID versus VDS measured

under pulsed conditions when VGS = 0.7 V at di�erent Tamb. (b) The

corresponding ID versus Tamb for VGS = 0.7 V and VDS = 7.5 V. . . . . 133

5.6 Measurement step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.7 DC and pulsed I-V comparison for devices grown on (a) SiC, (b) Si, and

(c) sapphire at di�erent Tamb. Solid symbols correspond to the pulsed

conditions (VGS.Q = VDS.Q = 0 V) and empty symbols correspond to DC.136

5.8 Tchannel as a function of PD for devices grown on (a) SiC, (b) Si, and

(c) sapphire at di�erent Tamb. The solid star corresponds to simulated

maximum Tchannel values, the line corresponds to the simulated average

Tchannel and the empty square are the values obtained experimentally. . 137

5.9 Comparison of Tchannel versus PD simulated maximum values, obtained

applying the proposed technique and the one reported in [Kuz02b]. . . . 140

5.10 Simpli�ed scheme of the one �nger devices. . . . . . . . . . . . . . . . . 142

5.11 Tchannel as a function of PD for devices grown on sapphire with LG = 3 μm,

LGD = 15 μm, and (a) WG= 300 μm, (b) WG = 200 μm, and (c) WG = 100

μm. The empty symbols correspond to the experimental results and the lines

to the simulations. The inset of �gure 5.11 shows the pulsed (line) and DC

(solid symbols) for the device with LG = 3 μm, LGD = 15 μm, and WG = 300

μm, as an example of I-V characteristics measured for the applications of the

experimental technique for Tchannel extraction. . . . . . . . . . . . . . . . . . 144

xx List of Figures

5.12 (a) Tchannel for PD = 1 Wmm-1 and (b) RTH for devices grown on sap-

phire with LG = 3 μm and LGD = 15 μm as a function of WG. The

empty symbols correspond to the experimental results and the curves to

the simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.13 Tchannel versus PD for devices grown on sapphire with WG = 100 μm,

LGD = 15 μm, and (a) LG = 1.5 μm, (b) LG = 2 μm, (c) LG = 3 μm,

(d) LG = 4 μm, and (e) LG = 5 μm. The empty symbols correspond to

the experimental results and the lines to the simulations. . . . . . . . . . 147

5.14 (a) Tchannel for PD = 2.5 Wmm-1 and (b) RTH for devices grown on

sapphire with LGD = 15 μm and WG = 100 μm as a function of LG. The

empty symbols correspond to the experimental results and the lines to

the simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.15 (a) Tchannel for PD = 2.5 Wmm-1 and (b) RTH for two �nger devices

grown on sapphire with LGD = 5 μm and WG = 2x50 μm as a function

of LG. The empty symbols correspond to the experimental results and

the lines to the simulations. . . . . . . . . . . . . . . . . . . . . . . . . 148

5.16 Tchannel versus PD for devices grown on sapphire with LG = 3 μm, WG

= 100 μm, and (a) LGD = 2.5 μm, (b) LGD = 5 μm, (c) LGD = 10 μm,

(d) LGD = 15 μm, and (e) LGD = 20 μm. The solid symbols correspond

to the experimental results and the lines to the simulations. . . . . . . 150


sapphire with LG = 3 μm and WG = 100 μm as a function of LGD. The

empty symbols correspond to the experimental results and the curves to

the simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

5.18 Simulations of (a) Ex , (b) Ns, (c) PD density, and (d) Tchannel in region

under the gate and 1 μm near the gate edge. Two devices with LGD =

2.5 μm and 20 μm (�xed LG = 3 μm and WG = 100 μm) are compared

for the same power dissipation PD = 4.5 W/mm are compared. . . . . . 152


sapphire and on SiC with LG = 3 μm and WG = 100 μm as a function

of LGD. The solid/empty symbols correspond to the experimental re-

sults whereas the dotted/solid lines correspond to simulations for devices

grown on sapphire/SiC, respectively. . . . . . . . . . . . . . . . . . . . . 153

List of Figures xxi

6.1 GLR as a function of τON for devices with di�erent cap layers: GaN, in

situ SiN, and in situ SiN/GaN. GLR values were calculated at VGS =

0 V and VDS = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.2 RONnorm calculated at di�erent Tamb for the pulsed measurements per-

formed using the quiescent point (-6 V, 0 V). . . . . . . . . . . . . . . . 159

6.3 RONnorm calculated at di�erent Tamb for the pulsed measurements per-

formed using the quiescent point (-6 V, 20 V). . . . . . . . . . . . . . . 160

6.4 RONnorm calculated before and after thermal stress tests for the pulsed

measurements performed using (a) the quiescent point of (-6 V, 0 V),

and (b) the quiescent point of (-6 V, 20 V). . . . . . . . . . . . . . . . . 162

6.5 (a) ID and (b) gm double-pulsed characterization for AlGaN barrier de-

vices. The ID values were measured at VGS = 1 V, whereas the gm values

were obtained by the derivation of the ID - VGS curves when VDS = 4V. 166

6.6 (a) ID and (b) gm double-pulsed characterization for an InAlN barrier

devices. The ID values were measured at VGS = -2.5 V, whereas the gmvalues were obtained by the derivation of the ID - VGS curves when VDS

= 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

6.7 (a) Fitted ID transients recorded for the trap �lling and on-state bias

points described in table 6.4, and (b) Corresponding di�erential signals

for AlGaN barrier devices. . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.8 (a) Fitted ID transients recorded for the trap �lling and on-state bias

points described in table 6.4, and (b) Corresponding di�erential signals

for InAlN barrier devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 170

6.9 (a) Fitted ID transients recorded for the trap �lling voltages and the

on-state bias (-1, 10 V) described in table 6.5, and (b) corresponding

di�erential signals for AlGaN barrier devices. . . . . . . . . . . . . . . . 172

6.10 (a) Fitted ID transients recorded for the trap �lling voltages and the

on-state bias (-1, 10 V) described in table 6.5, and (b) corresponding

di�erential signals for InAlN barrier devices. . . . . . . . . . . . . . . . 173

6.11 (a) Thermal activation and (b) Arrhenius plot with apparent activation

energies for T1 and T2 in AlGaN barrier devices. . . . . . . . . . . . . . 174

6.12 (a) Thermal activation corresponding to the trap �lling voltage (-8.5

V, 8 V). (b) Thermal activation corresponding to the trap �lling volt-

age (-6 V, 12.5 V). (c) Arrhenius plot with apparent activation energy

corresponding to T1', T2' and T3' for InAlN barrier device. . . . . . . . 176

xxii List of Figures

6.13 GLR as a function of τON for (a) AlGaN and (b) InAlN barrier HEMTs

with �xed LGD = 15 μm and WG = 100 μm and di�erent LG. . . . . . . 178

6.14 GLR as a function of τON (a) AlGaN and (b) InAlN barrier HEMTs

with �xed LG = 3 μm and WG = 100 μm and di�erent LGD. . . . . . . . 178

6.15 Distribution of electric �eld magnitude |E| on the AlGaN surface as a

function of (a) LG from 3 μm to 6 μm and �xed LGD = 15 μm; (b) from

10 μm to 20 μm and �xed LG = 3 μm (the curves in are overlapping).

The position of maximum |E| indicates the drain-side gate edge. . . . . 180

6.16 Electron density comparison in the channel for the device with and with-

out virtual gate. LSG = 2 μm, LG = 3 μm, LGD = 10 μm. The virtual

gate length used for these simulations were 0.4 μm. . . . . . . . . . . . . 180

6.17 Simulated GLR values as a function of (a) LG and (b) LGD. The devices

were biased in the same conditions that for the experiments: VGS = 0

V and VDS = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.1 (a) Amplitude and (b) phase obtained. The inset corresponds to the

scheme of modulation used: VGS modulation with Vo = -3 V, VA = 6

V, (V1 = - 6 V, and V2 = 0 V) and flock-in = 149 Hz. The central cells

and the drain pad exhibited higher power dissipation. . . . . . . . . . . 190

7.2 Output characteristics of an AlGaN/GaN device on sapphire before and

after the deposition of the commercial ThermeneTM paste on the hot

spots. The repetition of the measurements led to a degradation of the ID.191

A.1 Detailed scheme of the pulsed system developed during this thesis. . . . 194

A.2 Flow chart of the software developed. . . . . . . . . . . . . . . . . . . . . 199

A.3 Controls of the front panel. . . . . . . . . . . . . . . . . . . . . . . . . . 202

A.4 Graph indicators in the front panel. . . . . . . . . . . . . . . . . . . . . 203

B.1 E-mode HEMTs (LSD = 5 μm, and WG = 2x50 μm) fabricated by either

�uorine plasma or �uorine implantation treatments. . . . . . . . . . . . 205

B.2 One �nger devices (LG = 3 μm, and WG = 100 μm) involved in the

assessment of the potential bene�ts of di�erent cap layers: GaN, in situ

SiN, and in situ SiN/GaN. . . . . . . . . . . . . . . . . . . . . . . . . . 206

B.3 InAlN/GaN HEMTs with LG = 250 nm and di�erent layouts. . . . . . . 207

B.4 One �nger HEMTs with �xed LGD = 15 μm, and WG = 100 μm, and

variable LG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

List of Figures xxiii

B.5 One �nger HEMTs with �xed LG = 3 μm, and WG = 100 μm, and

variable LGD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

B.6 One �nger devices with LG = 3 μm, LGD = 15 μm, and variable WG. . . 208

B.7 One �nger HEMTs with �xed LGD = 15 μm, WG = 100 μm, and variable

LG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

B.8 Two �nger HEMTs fabricated with LGD = 15 μm, WG = 100 μm, and

di�erent values of LG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

B.9 One �nger HEMTs with �xed LG = 3 μm, and WG = 100 μm, and

variable LGD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

B.10 One �nger HEMTs with �xed LG = 3 μm, LGD= 10 μm, and WG = 100

μm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

B.11 One �nger HEMTs with �xed LGD = 15 μm, and WG = 100 μm, and

variable LG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

B.12 Multi�nger HEMT analyzed by IR-thermography. . . . . . . . . . . . . . 212

B.13 One �nger devices with LG = 3 μm, LGD = 5 μm, and WG = 100 μm. . 212

List of Tables

1.1 Inherent advantages of GaN-based material properties. . . . . . . . . . . 3

1.2 Main properties of the semiconductors used in power applications [Mis08]. 4

1.3 Competitive advantages of GaN devices [Mis02]. . . . . . . . . . . . . . 5

1.4 Spontaneous polarization and related parameters in Ga-face AlN, GaN,

and InN [Wa06]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5 Comparison of piezoelectric polarization related parameters in AlN, GaN,

and InN [Wan06]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6 Polarization charges of AlGaN/GaN and LM InAlN/GaN structures

[Kuz01]. σvΔPspand σvΔPpzcorrespond to the charge due to ΔPsp of and

ΔPpz, respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.7 State-of-the-art of GaN-based HEMTs. . . . . . . . . . . . . . . . . . . . 13

1.8 Research groups and their areas of work within the RUE project. . . . . 30

2.1 Main advantages and drawbacks of the substrates used during this thesis. 40

2.2 Samples used in this thesis with respective origin, the study where they

were involved and the chapter where it is discussed. . . . . . . . . . . . . 42

3.1 Parameters for the three as-grown samples obtained by di�erent tech-

niques. RBS reported composition and thickness (tRBS). The thickness

was also obtained by XRD (tXRD). C-V measurements provided the

2DEG density (ns) and thickness (tC-V) [Bra14]. . . . . . . . . . . . . . 86

3.2 Parameters of etched samples: thickness obtained by XRD (tXRD) and

the 2DEG density (ns) and depth (tC-V) extracted from the C-V mea-

surements [Bra14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

xxv

xxvi List of Tables

4.1 DC parameters measured at RT for devices with di�erent cap layers (LG= 3 μm, LGD = 2.5 μm, and WG = 100 μm). ID.max corresponds to the

maximum ID at VGS = 0 V. RON was extracted from the ID - VDS curve

at VGS = 0 V. gm.max is the maximum gm at VDS = 9.9 V. ID.o� and

IG.o� correspond to the value of ID and IG, respectively, when the devices

were biased in o�-state at VGS = -6 V and VDS = 20 V. . . . . . . . . . 109

5.1 RTH as a function of temperature for experimental and simulated data. 135

5.2 Normalized ΔID.max calculated as ΔIsubstrateD.max

ΔISiCD.max

, and normalized RTH ex-

tracted as RsubstrateTH

RSiCTH

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.3 RTH as a function of temperature for experimental and simulated data

for devices with LG = 1.4 μm. . . . . . . . . . . . . . . . . . . . . . . . . 140

5.4 Description of the one �nger devices. . . . . . . . . . . . . . . . . . . . . 143

6.1 Electrical DC parameters obtained for the devices under studied . . . . 163

6.2 Description of the Q points used to evaluate the trapping e�ects. . . . . 164

6.3 Description of the device geometries under test. . . . . . . . . . . . . . . 165

6.4 Description of the on-state bias voltages assessed for AlGaN and InAlN

barrier devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

6.5 Description of the trap �lling voltages evaluated for AlGaN and InAlN

barrier devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

6.6 Summary of the results from the ID transient measurements performed

in the devices under test. . . . . . . . . . . . . . . . . . . . . . . . . . . 183

A.1 Description of the two selectable output ampli�ers [Key14]. . . . . . . . 194

A.2 Main characteristics of pulse waveform in high voltage ampli�er con�g-

uration for 50 Ω into open [Key14]. . . . . . . . . . . . . . . . . . . . . . 195

A.3 Main characteristics of its analog signal inputs [Yok14]. . . . . . . . . . 196

Acronyms

2DEG Two dimensional electron gas

AEGaN Ampli�cadores de envolvente de banda ancha para EER/ET y fabricación

de dispositivos de nitruro de galio

AlGaN Aluminum gallium nitride

AlN Aluminum nitride

CAVE Conmutación multinivel y multifase para aplicaciones espaciales

CEI Centro de electrónica industrial

CNM Centro Nacional de Microelectrónica

CVD Chemical vapor deposition

CG Gate capacitance

C-DTLS Capacitance deep-level transient spectroscopy

C-V Capacitance-voltage

D Drain

D-mode Depletion mode

EPC E�cient Power Conversion Corporation

EA Activation energy

EBD Breakdown electrical �eld

Eg Bandgap energy

xxvii

xxviii List of Tables

EX Electric �eld

E-mode Enhancement mode

FET Field-e�ect transistor

fmax Maximum frequency

fT Cut-o� frequency

G Gate

GaAs Gallium arsenide

GaN Gallium nitride

Gap Semiconductor band gap

GLR Gate lag ratio

GGD Gate-to-drain conductance

gm Transconductance

gm.max Maximum transconductance

gmint Intrinsic transconductance

HD-DVD High density-digital versatile disc

HEMT High-electron mobility transistor

HR Highly resistance

HVPE Hydride vapor phase epitaxy

I Current

ICP Inductively coupled plasma

InAlGaN Indium aluminum gallium nitride

InAlN Indium aluminum nitride

InN Indium nitride

List of Tables xxix

InP Indium phosphide

ISOM Instituto de Sistemas Optoelectrónicos y Microtecnología

ID Drain current

ID.DC Drain current under DC conditions

ID.max Maximum drain current

ID.o� Drain current in o�-state

ID.pulsed Drain current measured under pulsed conditions

Idiode Diode current

Idiode.invnormalized Normalized reverse diode current

IG Gate leakage current

Ixx Current applied between two parallel ohmic contacts

Ixy Current applied between two diagonal ohmic contacts

I-DLTS Drain-current deep-level transient spectroscopy

I-V Current-voltage

JFM Johnson's �gure-of-merit

LED Light emitting diode

LM Lattice matched

LG Gate length

LGD Gate-to-drain distance

LSD Source-to-drain distance

MBE Molecular beam epitaxy

MESFET Metal-semiconductor �eld e�ect transistor

MIS Metal-insulator-semiconductor

xxx List of Tables

MOCVD Metal organic chemical vapor deposition

NRL Naval Research Laboratory

ns Electron concentration in the channel

PECVD Plasma enhanced chemical vapor deposition

PD Dissipated power

Ppz Piezoelectric polarization

Psp Spontaneous polarization

Q Quiescent bias

R Resistance

RBS Rutherford backscattering spectroscopy

RF Radio frequency

RIE Reactive ion etching

RMS Root-mean-square

RT Room temperature

RTA Rapid thermal annealing

RUE Advance wide band gap semiconductor devices for rational use of energy

RC Contact resistance

Rcp Probe-to-metal contact resistance

RG Gate resistance

RH Hall resistance

Risolation Isolation resistance

RON On-resistance

Rp Probe resistance

List of Tables xxxi

RS Source resistance

RSD Source-to-drain resistance

Rsheet Sheet resistance

Rsheet.gs Gate-source sheet resistance

RT Total resistance

RTH Thermal resistance

Rxx Longitudinal resistance

S Source

Si Silicon

SiC Silicon carbide

SIMS Secondary ions mass spectrum

SiN Silicon nitride

t Barrier thickness

TC Thermal cycle

TLM Transmission line method

tafter Barrier thickness after wet-etching

tbefore Barrier thickness before wet-etching

Tchannel Channel temperature

tC-V Barrier thickness calculated from the C-V measurements

tRBS Barrier thickness extracted from RBS measurements

tXRD Barrier thickness obtained by XRD characterization

UPM Universidad politécnica de Madrid

V Voltage

xxxii List of Tables

VBD Breakdown voltage

VDS Drain-source voltage

VDS.F Filling trap drain-source voltage in transient measurements of drain current

VDS.M On-state drain-source voltage in transient measurements of drain current

VDS.Q Quiescent drain-source voltage in pulsed measurements

VFB Flatband voltage

VGS Gate-source voltage

VGS.F Filling trap gate-source voltage in transient measurements of drain current

VGS.M On-state gate-source voltage bias in transient measurements of drain cur-

rent

VGS.Q Quiescent gate-source voltage in pulsed measurements

VK Knee voltage

vsat Saturation velocity

VTH Threshold voltage

Vxx Voltage measured between two parallel ohmic contacts

Vxy Voltage measured between two diagonal ohmic contacts

WG Gate width

XRD X-ray di�raction

Z Depth

List of Tables xxxiii

ΔID Variation of drain current

ΔIsat Change of drain current in the saturation region

ΔPtotal Di�erence of total polarization

ΔRS Change in source resistance

ΔTamb Variation of ambient temperature

ΔTchannel Variation of channel temperature

ΔVFB Variation of �atband voltage

ΔVTH Variation of threshold voltage

ε Dielectric constant

θ Linear �t slope of ID versus Tamb

κ Thermal conductivity

µ Electron mobility

ρ Resistivity

σv Conductivity of the channel

σvpol Induced charge

τ Period

τF Filling trap time in drain current measurements

τM On-state bias time during drain current measurements

τOFF O�-state time

τON Pulse duration

Chapter 1

Introduction

1.1 State of the art

The gallium nitride (GaN) semiconductor has been considered as one of the most

promising materials for the development of optical as well as power and frequency

electronic applications since the early nineties. Nowadays, GaN-based devices are

already integrated in optical applications, for example, light emitting diodes (LEDs)

are commonly used in tra�c lights, and lasers are also used in laser pointers, high

density-digital versatile disc (HD-DVD) and blue-ray disc [Rom10]. However, GaN-

based devices for electronic applications, where the high electron mobility transis-

tors (HEMTs) are the key components, have not been extensively commercialized

yet and intensive research is still ongoing to overcome their limitations. There are

only few companies which o�er GaN-based devices for these applications. For exam-

ple, the American company called E�cient Power Conversion Corporation (EPC)

has been the �rst to introduce enhancement-mode GaN on silicon �eld e�ect transis-

tors (FETs) in applications such as servers, wireless, power transmission, envelope

tracking, and RF transmission [Epc14]. Another American company called RFMD

o�ers a variety of high power GaN on SiC HEMT RF products used in both, com-

mercial and military applications [Rfm14]. On the other hand, some European

companies o�er high-quality GaN III-nitride epitaxial layers which are suitable for

the development of HEMTs. For instance, EpiGaN o�ers AlGaN-based heterostruc-

tures with an in situ SiN passivation grown on Si or SiC for high voltage or high

frequency applications, respectively [Epi14].

1

2 CHAPTER 1. INTRODUCTION

Figure 1.1: The main applications of GaN-based materials [Mwr14].

1.1.1 GaN-based heterostructures and applications

In the last decades, GaN and its alloy compounds with InN and AlN have attracted

the attention of the scienti�c community, opening a wide range of research topics

and applications such as power and microwave electronics, piezoelectric sensors, etc.

Figure 1.1 shows the main applications of GaN-based materials which are based on

their outstanding properties, for instance, wide bandgap, chemical stability, and

piezoelectric e�ect. Table 1.1 summarizes the inherent advantages of the GaN-

based material properties which enable the III-nitride compound semiconductors

to be applied into several applications, where the conventional compound or silicon

semiconductors can not be used [Wan06].

Regarding the optical �eld, GaN-based semiconductors enable the fabrication

of LEDs and lasers in a wide spectrum from UV to green thanks to the large di-

rect bandgap range covered by the AlGaN and InGaN alloys [Nak97]. Moreover,

ultraviolet photodetectors based on GaN are suitable for both military and civil

applications [Mon03]. Concerning the electronic applications, the development of

GaN-based HEMTs will lead to a great achievement for satellite and radar commu-

1.1. STATE OF THE ART 3

Table 1.1: Inherent advantages of GaN-based material properties.

PROPERTY ADVANTAGES

Wide bandgapThe bandgaps of InN (0.7 eV) [Dav02], GaN (3.4eV) [Str92] and AlN (6.2 eV) [Str92] cover visible

and UV light spectrum

Chemical stabilityPossibility of working at high temperature and in

high pressure environmentsStrong piezoelectric e�ect Epitaxy design of sensor and electronic structures

Figure 1.2: Potential militar (black) and commercial (grey) application of GaN-based HEMTs [Mis02].

nications, which require high power ampli�ers operating at a frequency range from

hundreds of MHz to tens of GHz (see �gure 1.2).

GaN shows excellent thermal and electronic transport properties, as well as

high breakdown voltage, and good chemical and thermal stability [Jim03]. However,

some of its competing materials, such as silicon (Si), gallium arsenide (GaAs), or

indium phosphide (InP), present performance limitations at both high power density

and high temperature conditions due to their narrow bandgap. Table 1.2 shows the

comparison between GaN and their competitors related to the main semiconductor

parameters, such as mobility (μ), saturation velocity (vsat), breakdown electrical

�eld (EBD), dielectric constant (ε), thermal conductivity (κ), and bandgap energy


Table 1.2: Main properties of the semiconductors used in power applications

[Mis08].

Si GaAs 4H-SiC GaN Diamond

Eg (eV) 1.1 1.42 3.26 3.39 5.45εr 11.8 13.1 10 9.0 5.5

μ

(cm2/V·s)

1350 8500 7001200 (bulk)2000 (2DEG)

1900

vs·107

(cm/s)

1.0 1.0 2.0 2.5 2.7

EBD(MV/cm)

0.3 0.4 3.0 3.3 5.6

κ

(W/K·cm)

1.5 0.43 3.3-4.5 1.3 20

JFM (vs

Si)

1 2.7 20 27.5 50

(Eg) as well as the Johnson's �gure-of-merit (JFM), which is de�ned as [Joh65]:

JFM =EBD·vs

2π(1.1)

and is commonly used for the evaluation of the suitability of semiconductor mate-

rials for the development of high frequency power devices, since the current gain

cut-o� frequency (fT) is linked to the vs value; and the breakdown voltage (VBD)

of the device is related to the EBD [Mar12].

Although, according to Table 1.2, the best material for the power devices

development would be diamond, its complex technology is not mature yet. On the

other hand, SiC and GaN present similar thermal and electrical stability, breakdown

voltage and bandgap; but GaN has the advantage of better electron transport prop-

erties (μ is between 1200-2000 cm2/V·s for GaN whereas for SiC is approximately

700 cm2/V·s). Although SiC was one of the �rst studied wide bandgap semicon-

ductors for high voltage applications [Tak07], GaN is more interesting thanks to

the possibility of the development of HEMTs based on the GaN heterojunctions.

Furthermore, GaN presents a high JFM value which indicates its suitability for high

power and high frequency applications.

The competitive advantages of GaN devices are shown in Table 1.3. The


Table 1.3: Competitive advantages of GaN devices [Mis02].

NEEDENABLING

FEATURE

PERFORMANCE

ADVANTAGE

High power per unit

width

Wide bandgap, high

�eldCompact, ease of matching

High voltage

operationHigh breakdown �eld Eliminate/reduce step down

High linearity HEMT topology Optimum band alocation

High frequency High electron velocity Bandwidth, μ-wave/mm-wave

High e�ciencyHigh operating

voltage

Power saving, reduced

cooling

Low noise High gain, high velocity High dynamic range receivers

High temperature

operationWide bandgap

Rugged, reliable, reduced

cooling

Thermal management SiC substrateHigh power devices with

reduced cooling needs

Technology leverageDirect bandgap.

Enabler for lighting

Driving force for

technology: low cost

�rst column corresponds to the requirements for any power device, the second

column presents the characteristics which enable GaN-based devices to ful�ll these

needs, and the last column shows the performance advantages resulting from these

GaN properties. The highlighted characteristics correspond to the GaN device

advantages in comparison with other technologies, and most of them are due to

the AlGaN/GaN heterostructure. For instance, high power per unit width leads to

smaller devices that are easier to fabricate and match them to the system thanks to

their higher impedance [Mis02]. The high voltage operation reduces or eliminates

the need for voltage conversion since GaN devices can operate at the same voltage

as the commercial systems [Mis02]. Another important advantage of GaN devices is

their high operating voltage resulting in their high e�ciency, which reduces power

requirements and simpli�es cooling [Mis02].

The polar nature of GaN and AlGaN �lms dramatically a�ects the device be-

havior and may also determinate the defect density [Mis02]. Although the III-nitride

compound semiconductors can be growth with two di�erent crystalline structures,

the zincblende and the wurtzite (see �gure 1.3), only material with wurtzite struc-

ture was used during this thesis since it is the most thermodynamically stable. As

�gure 1.4 shows, the wurtzite GaN crystalline structure can grow with two di�erent


Figure 1.3: The distribution of atoms in zincblende and wurtzite structure [Wan06].

Figure 1.4: The directions of spontaneous polarization in the N-face and Ga-FaceGaN wurtzite structure [Wan06].

face-type, the N-face and the Ga-face, which decides the direction of the sponta-

neous polarization. Noting that, the material used during this dissertation was all

Ga-face since currently, all high-quality material is grown with this polarity [Mis02].

The spontaneous polarization (Psp) depends on both, the asymmetry of struc-

ture in Z-axis and the ratio of√

coao, where ao and co are the lattice constants of

X-axis and Y-axis, respectively [Ber97]. The spontaneous polarization of Ga-face

InN, GaN, and AlN are all negative (see table 1.4), and hence, their directions


Table 1.4: Spontaneous polarization and related parameters in Ga-face AlN, GaN,and InN [Wa06].

AlN GaN InN

ao (Å) 3.112 3.189 3.54co (Å) 4.982 5.185 5.705√

coao

1.619 1.6336 1.627

Psp (C·m-2) -0.081 -0.029 -0.032

are towards substrate (see �gure 1.4). Therefore, the two layers which form the

AlxGa1-xN/GaN heterostructure present negative spontaneous polarization.

Besides the spontaneous polarization described above, AlGaN/GaN heterostruc-

ture also shows piezoelectric polarization (Ppz) due to the di�erent lattice constants

of AlGaN and GaN semiconductors (see �gure 1.5).

The tensile strain caused by the growth of AlxGa1-xN on GaN leads to a

piezoelectric polarization which adds to the net spontaneous polarization [Mis02].

The strain-induced piezoelectric polarization in thick GaN bu�er can be neglected

because the lattice mismatch e�ect between GaN and substrate is released by the

apparition of defects or dislocations in the GaN bu�er layer [Wan06]. The piezoelec-

tric polarization can be extracted from the following equation reported in [Amb00]:

Ppz = e33ez + e31 (εx + εy) (1.2)

where e33 and e31 are the piezoelectric constants for the deformed material just

considering the polarization in Z-axis and assuming the polarizations in X-axis and

Y-axis compensated, and εx, εy and εz are the deformations of material in X-axis,

Y-axis and Z-axis, respectively, and de�ned as:

εx = εy =(a− ao)ao

(1.3)

εz =(c− co)co

(1.4)

Assuming that the deformations of the material in the X-axis and Y-axis are

isotropic, the deformation in the Z-axis can be described as two times of deformation

in X-axis multiplying by an elastic ratio:

εz =(c− co)co

= −2C13

C33

(a− ao)ao

(1.5)


(a)

(b)

Figure 1.5: (a) Lattice constant di�erences for the (Al, Ga, In, N) system and theresulting AlGaN/GaN structure [Mis02]. (b) Bandgap and piezoelectric polariza-tion versus the lattice constant for (Al, Ga, In, N) system [Wan06].


Table 1.5: Comparison of piezoelectric polarization related parameters in AlN, GaN,and InN [Wan06].

AlN GaN InN

e33 (C/m2) 1.46 0.73 0.97

e31 (C/m2) -0.6 -0.49 -0.57

C33 (GPa) 395 379 182C13 (GPa) 120 70 121(e31 − e33C13

C33

)-0.86 -0.68 -0.9

where C13 and C33 are the elastic constants. Finally, substituting eq. (1.3) and eq.

(1.5) into eq. (1.2) results in:

P pz = 2(a− ao)ao

·

(e31 − e33

C13

C33

)(1.6)

Taking into account the values of the piezoelectric polarization parameters of

AlN, GaN and InN shown in Table 1.5, the value of(e31 − e33C13

C33

)is always negative

for the III-nitride compound semiconductors. Moreover, the value of (a−ao)ao

is always

positive. Therefore, the piezoelectric polarization is always negative, which means

that the direction of the piezoelectric polarization is also to substrate [Amb00]. The

di�erence of total polarization (ΔPtotal) between the AlxGa1-xN and the GaN of

the heterostructure leads to an induced charge (σvpol):

σpol = −∆Ptotal = − (ΔPsp +ΔPpz) = [Psp(AlGaN)− Psp(GaN)] + Ppz(AlGaN)

(1.7)

Assuming that the strength of spontaneous polarization in GaN, Psp (GaN), is

larger than in AlGaN, Psp (AlGaN), both ΔPsp and ΔPpz are negative. Therefore,

the charges induced by these two polarizations will be added, indicating that these

two polarizations introduce the two dimensional electron gas (2DEG) simultane-

ously [Wan06]. Figure 1.6 describes in detail the piezoelectric and the spontaneous

polarization contributions to the concentration of 2DEG.

The strain resulting from the mismatch and modulated by piezoelectric e�ects

have been found to be responsible for some important reliability problems [Joh06],

which will be deeply explained in the section 1.1.3 of this chapter. The AlGaN

barrier can be replaced by lattice matched (LM) InAlN in order to avoid these

instability problems which lead the AlGaN/GaN HEMTs to be reliable only when

they operate below their theoretical limits [Med06]. LM InAlN/GaN heterostruc-


(a)

(b)

Figure 1.6: (a) Total polarizations and (b) their e�ects on the 2DEG concentrationin AlGaN/GaN HEMT [Sac01].


Table 1.6: Polarization charges of AlGaN/GaN and LM InAlN/GaN structures[Kuz01]. σvΔPspand σvΔPpzcorrespond to the charge due to ΔPsp of and ΔPpz,respectively.

Semiconductor σvΔPsp(1013 C·cm-2) σvΔPpz

(1013 C·cm-2) σvtotal(1013 C·cm-2)

Al0.2Ga0.8N 0.65 0.53 1.18

In0.17Al0.83N 2.73 0 2.73

ture o�ers potentially higher sheet charge densities thanks to a higher spontaneous

polarization of InAlN in comparison to AlGaN [Kuz01]. Furthermore, as �gure 1.7

shows, InAlN also presents a larger conduction band discontinuity which provides

improved electron con�nement [Gon06]. Applying the Vegard's law for alloys of

InN, AlN and GaN, InAlN layers with In content of 17% can be grown LM on GaN,

which means no piezoelectric polarization (see �gure 1.7) [Kuz01, Kuz02a, Neu04].

Therefore, σvpol for a LM InAlN/GaN heterostructure can be calculated applying

eq. (1.7):

σpol = −ΔPtotal = − (ΔPsp +ΔPpz) = ΔPsp = [Psp(InAlN)− Psp(GaN)] (1.8)

Eq. (1.8) indicates that only the spontaneous polarizations introduce the

2DEG in the case of a LM InAlN/GaN heterostructure. However, its sheet charge

density can be higher than the corresponding to an AlGaN/GaN heterostructure

thanks to the higher ΔPsp of LM InAlN/GaN (see Table 1.6).

During this thesis both, AlGaN/GaN and LM InAlN/GaN heterostructures

were used for the fabrication and the study of di�erent aspects of HEMTs.

1.1.2 High electron mobility transistors

Brief history of GaN-based HEMTs

The �rst AlGaN/GaN HEMT was reported by Khan et al. in 1992 with a carrier

density of 1011 cm-2 and a mobility of 400-800 cm2/Vs [Kha92]. The same group

reported the DC and RF performances of AlGaN/GaN HEMTs in 1993 and 1994,

respectively [Kha93, Kha94a]. Wu et al. achieved a power density of 1.1 W/mm

at 2 GHz in 1996 [Wu96]. The lower transconductance (gm) and poor frequency

response exhibited by the early HEMTs were mainly due to the poor crystal quality

of the heterostructure [Cho13]. During the last decade and a half, great e�orts


Figure 1.7: Bandgap over the lattice constant of InN, AlN, GaN pointing out thatlattice-matched InAlN is obtained for an In content of 17% [Bah12].

were made by the scienti�c community to optimize the metal organic chemical

vapor deposition (MOCVD) and the molecular beam epitaxy (MBE) procedures to

improve the crystal quality of the heterostructure and hence, the DC and RF HEMT

performances [Kel01, Jim03]. Moreover, to further improve the performance of

these devices, several studies concerning their processing were carried out, specially

focused on the reduction of DC-RF dispersion by the deposition of a SiN passivation

step [Gre00]. Recently, a 60 nm standard-gate devices grown on SiC have exhibited

an excellent RF performance, showing a fmax of 300 GHz and a VBD of 20 V [Chu10].

Moreover, 150 nm T-gate devices grown on Si have reached a VBD of 132 V and

a fT of 63 GHz [Ran14]. Table 1.7 illustrates a more detailed description of these

results.

On the other hand, InAlN/GaN HEMTs attracted the attention of the re-

search groups in the 2000's. Although the thermodynamic analysis showed that

InAlN epitaxial growth could be di�cult [Kou00], high-quality LM InAlN were re-

ported [Kar99]. Moreover, it was demonstrated that inserting a thin AlN layer be-

tween InAlN barrier and GaN e�ectively reduces the alloy scattering and improves


Table 1.7: State-of-the-art of GaN-based HEMTs.

Reference Barrier Substrate VBD

(V)

fT

(GHz)

fT·VBD

(1012

V/s)

Gate

shape

Passivation

[Cha10] AlGaN SiC 20 70 1.40 T Unpassivated

[Ran14] AlGaN Si 132 63.0 8.32 T [(NH4)2Six]SiN

[Lee11] InAlN SiC 30 300 9.00 Rectangular Al2O3

the electron mobility in the 2DEG [Gon06]. Recently, Jardel et al. presented InAlN

barrier devices processed at III-V Labs with excellent power performances, even in

Ku band [Jar10]. Furthermore, Lee at al. reported in [Lee11] lattice-matched In-

AlN/GaN HEMTs with an InGaN back barrier on a SiC substrate showing a record

fT of 300 GHz for 30 nm gate length devices (see table 1.7).

Fundamentals of GaN-based HEMTs

HEMTs are solid state devices which belong to the family of the �eld e�ect transis-

tors (FETs), since the current through the channel is controlled by an electric �eld.

These devices have three terminals: drain (D), source (S) and gate (G). Drain and

source are wired by ohmic contacts and the gate corresponds to a Schottky contact.

Typically, the Schottky contact is placed between the two ohmic contacts, as shown

in �gure 1.8. The current (ID) �ows from drain to source through the channel cre-

ated by the 2DEG, and it is only due to the majority carriers, which are electrons.

The conductivity of the channel (σv) is de�ned as [Sze85]:

σ = q·ns·µ (1.9)

where q is the electron charge, ns corresponds to the electron concentration in the

channel, and μ is the electron mobility. Therefore, the product ns·μ is a crucial

parameter of 2DEG [Rom10].

These electrons are con�ned in the 2DEG at zero gate-source voltage (VGS),

thus HEMTs are normally-on or so-called depletion mode (D-mode) devices since

ID �ows when VGS= 0 V. Therefore, a negative VGS is required to deplete the

channel and then control ID. The VGS value which fully depletes the channel is

called threshold voltage (VTH).


Figure 1.8: Scheme of a standard HEMT.

(a) (b)

Figure 1.9: Band diagram of HEMT when (a) VGS= 0 V and (b) VGS ≤ VTH.

Figure 1.9 shows a schematic diagram that explains the gate control mech-

anism in these devices, where the 2DEG density is modi�ed by the VGS applied

[Kal09]. When VGS = 0 V or positive, the channel is formed and the ID is maxi-

mum. Decreasing the value of VGS to negative values, ID is reducing down to VGS

≤ VTH, when the 2DEG is completely pinched o� and hence ID is zero.

Figure 1.10 presents the I-V output characteristics of an ideal HEMT. Accord-

ing to the I-V behavior, it is possible to identify two regimes namely the linear and


Figure 1.10: Output I-V characteristics of an ideal HEMT. ID.max corresponds tothe maximum ID at VGS= 0 V whereas VBD is the minimum VDS which causes ananomalous device performance. The black dash line points out the transition fromlinear to saturation region.

the saturation regimes. The knee voltage (VK) is the drain source voltage (VDS)

of the I-V curves transition from linear to saturation region [Khu11]. The break-

down voltage (VBD) corresponds to the minimum VDS in which a rapid increase

in leakage current occurrs [Ini12], which could cause an anomalous performance or

the breakdown of the device. Moreover, ID.max can be de�ned as the ID in the

saturation region for VGS = 0 V.

The main geometrical parameters which de�ne the device are the gate length

(LG), the gate width (WG), as well as the distance source-to-gate (LSG) and the

distance gate-to-drain (LGD). The layout of the device will be determined by its

application. For example, LG limits the maximum frequency (fmax) of the device,

therefore, sub-micron LG devices are more suitable for RF applications. Larger

WG HEMTs provide higher levels of power [Raj13]; whereas larger gate-to-drain

distance (LGD) increases the breakdown voltage (VBD) of the device.

Electrical properties of GaN-based HEMTs

The electrical properties of HEMTs are characterized by the following parameters:


� The drain current which is de�ned by the following expression:

ID =WG·μ·CG

LDS

[(VGS − VTH)VDS −

V 2DS

2

](1.10)

where μ is the electron mobility, WG is the gate width, LDS corresponds to

the source-to-drain distance, CG is the gate capacitance; and VTH is the threshold

voltage.

� The transconductance (gm), which is an important parameter for microwave

applications, is related to the gain of the device and represents the e�ective-

ness of gate modulating the ID. It is de�ned as:

gm =∂ID∂VGS

|VDS = cte (1.11)

The transconductance mainly depends on the ohmic contact resistivity, the

AlGaN thickness and the source-to-drain distance.

� The power density which is de�ned as:

dPout =ID.max (VBD − VK)

8(1.12)

where VBD is the breakdown voltage and VK corresponds to the knee voltage.

� The current gain cut-o� frequency (fT) which can be expressed as:

fT =gm

(2πCG)(1.13)

� The power gain cut-o� frequency or maximum oscillation frequency (fmax)

which is proportional to fT:

fmax∞fT√

RSD·GGD(1.14)

where RSD is the source-to-drain resistance and GGD corresponds to the gate-

to-drain conductance.


Figure 1.11: Transfer characteristics of E-mode devices and D-mode devices, usedas reference [Pal06a].

Normally-o� devices

GaN-based HEMTs are very promising for the development of high power switches,

microwave ampli�ers and integrated circuits operating at high temperature. Com-

pered to the conventional depletion mode (D-mode) HEMTs, enhancement mode

(E-mode) or normally-o� HEMTs would be more desirable in these applications.

This is due to its positive VTH, which leads to some important advantages, namely

lower power consumption, and secondly simpler circuit design and fail-safe opera-

tion (see �gure 1.11).

Several techniques for the fabrication of normally-o� GaN transistors have

been reported. Some of them start with an as-grown D-mode heterostructure

and include di�erent treatments, such as a �uorine-based plasma treatment [Cai05]

and/or a recess of the region under the gate [Pal06a, Sai06]. Other procedures also

include the deposition of gate dielectric together with the gate-recess [Kan10] or the


(a) (b)

(c) (d)

Figure 1.12: Normally-o� AlGaN/GaN transistors fabricated by: (a) �uorine-treatment, (b) p-type gate technology, (c) thinner barrier, and (d) gate-recess tech-nology [Lu13].

combination of �uorine based plasma treatment with a metal-oxide-semiconductor

gate architecture [Cha10]. However, other techniques are based on di�erent het-

erostructures; for instance, the use of thinner AlGaN barrier layers [Ohm06] or GaN

n-channel MOSFETs fabricated on p-type GaN bu�er [Hua06]. Figure 1.12 reviews

some of these technologies:

� Fluorine based plasma treatment under the gate region has been used to

fabricate E-mode AlGaN/GaN HEMTs [Pal06a, Sai06, Chu11] starting from

an as-grown D-mode heterostructure (see �gure 1.12a). The introduction of

negatively charged �uorine ions into the AlGaN layer depletes the 2DEG in

the channel shifting the VTH to positive values [Yua08]. These �uorine ions

are believed to introduce acceptor-like deep-level states that are near the mid-

bandgap [Wan09a]. Thermal stress studies in E-mode devices fabricated by


means of this technique demonstrated thermal stability at 200°C for more

than 80 days [Miz07]; whereas they exhibited a negative VTH shift operating

at high temperature [Wan09a]. This can be explained as the consequence of

the thermal excitation of electrons con�ned in the �uorine ions, which leads

to the reduction in the number of the negatively-charged �uorine ions in the

AlGaN layer [Wan09a].

� p-GaN, p-AlGaN or p-InGaN gated AlGaN/GaN transistors [Uem07, Shi08]

(see �gure 1.12b) are normally-o� devices. This is due to the built-in potential

between the p-type gate and the channel which depletes the 2DEG under the

gate at VGS = 0 V [Lu13].

� Thinner AlGaN or AlN barrier layer together with the deposition of a thin

dielectric on the surface (see �gure 1.12c). The thin barrier leads to almost no

2DEG at the heterojunction interface. Then, the passivation dielectric layer

is deposited covering the surface except the gate region, which increases the

2DEG in the access regions [Lu13].

� The gate-recess method is based on the in�uence of the AlGaN barrier thick-

ness on the net polarization charge at the heterostructure. Therefore, the

recess-etching in the gate area reduces the 2DEG density in this region, re-

sulting in a VTH shift to positive values [Sai06]. Moreover, the fabrication of a

MIS-HEMT combining the gate-recess with the deposition of a gate dielectric,

as �gure 1.12d shows, leads to a much higher VTH as well as lower leakage

current and larger forward gate-bias capability [Kan10]. Some aspects of the

recess-etching need to be addressed, such as the etch damages which increase

surface roughness and reduce the electron mobility, or the variation in etch

depth which results in a non-uniform VTH value.

1.1.3 Reliability and failure mechanisms

As stated above, GaN-based HEMTs are considered very promising candidates for

high power, high frequency and high temperature applications. In spite of their

theoretical impressive attributes and the excellent performance demonstrated, they

are not widely deployed in these applications yet due to some reliability problems

[Ala06, Sin06]. A better understanding of the failure mechanisms is required for

the improvement of their reliability. However, this task can be very challenging


since there is a wide range of aspects involved, such as the device physics, the

material defects and the fabrication processes [Mis08, Men08]. Figure 1.13 shows

the main failure mechanisms found out in nitride-based HEMTs together with the

areas which are more likely to su�er them. They can be classi�ed in di�erent groups

regarding their origin [Del03], namely concerning the material, the technology, or

the electrical operation, as detailed below:

1. Material

a) Crystalline defects: promote the metal di�usion and the carrier recom-

bination leading to some reliability problems [Del03].

b) Non-uniformity: the epitaxial control plays a key role in the �nal elec-

trical characteristics. Therefore, any lack of uniformity may result in

dispersions leading to device failure when it works under extreme condi-

tions [Del03].

2. Technology

a) Ohmic contact degradation: the thermal stability of the ohmic contacts

is a mandatory requirement since several applications lead to work at

high temperature.

b) Gate sinking: corresponds to the metal-interdifussion e�ect which causes

a change in the pinch-o� voltage and a reduction of the ID and gm [Del03].

This phenomenon is more common in GaAs HEMTs than in GaN-based

HEMTs [Men08].

c) Purple plague: this defect is related to the gold-aluminum reaction and

can cause total device failure. Therefore, a barrier-di�usion metal is

included in order to avoid this phenomenon. Several studies have been

already performed to assess which metal would be the most suitable

barrier; for example, titanium [Ver06], nickel [Cre02], or molybdenum

[Sel04, Ver06].

d) Passivation degradation: the passivation layer has two main purposes,

�rstly to protect the device from chemical environment aggression and

secondly to avoid the presence of carrier traps. However, any defects


in the passivation layer may cause the degradation of the device perfor-

mance [Del03]. For instance, the alkaline contamination of the passiva-

tion layer causes changes in the current �ow. Moreover, the delamination

of the passivation layer leads to device failure [Bou07].

3. Electrical behaviors

a) Current collapse: originally, this term was used for the reduction in drain

current which occurs after the application of high drain bias [Dru83].

However, nowadays it regards any degradation resulting in either a re-

duction of available current or power [Lea10, Has13], or an increase of

the dynamic on-resistance (RON) [Has13]. The current collapse can be

recovered or avoided by heating or illuminating the sample, indicating

that it is a phenomenon related to charge trapping [Mit03, Kol03].

b) Gate lag refers to a delayed response of ID to a sudden change in VGS.

This phenomenon has been attributed to the presence of surface states

that act as electron traps located in the access region [Bin01, Zha03]

depleting the 2-DEG in this area. Their e�ects can be evaluated by VGS

pulsed measurements from o�-state to on-state [Zha03].

c) Drain lag corresponds to the current drift observed before reaching a

new steady state values after a VDS change for a �xed VGS [Del03].

This e�ect is usually linked to the presence of traps in the bu�er [Bin01,

Zha03] and can be studied observing the ID transient during VDS pulsed

measurements.

Besides the failure mechanisms mentioned above, another challenging issue

related to the HEMTs reliability is the self-heating. During this thesis, special

attention has been paid to the study of the trapping e�ects as well as the evaluation

of the self-heating and its e�ects on the device performance. For that reason, a more

detailed description of these two issues will be done below.

Trapping e�ects

Many studies have reported that trapping e�ects are the main cause for the power

densities degradation in GaN HEMTs, which exhibits lower levels of power in RF

than the predicted in DC by the eq. (1.12) and gate-leakage [Bin01, Bin02, Vet01,


Figure 1.13: Schematic cross section of an AlGaN/GaN HEMT, identifying thecritical areas where the degradation can occur [Men08].

Kal09]. Figure 1.14 shows an schematic of the I-V output characteristics of a HEMT

in on-state (VGS = 0 V) and o�-state (VGS.OFF) when the device is bias between

VK and VBD in both DC and RF conditions. When the device is in o�-state with a

high VDS, charge injection into surface states occurs, and the trapping of electrons

by the surface traps in the gate-to-drain access region disturbs the charge neutrality

balance, reducing the sheet channel charge density in that region. This leads to a

reduction of ID.max as well as an increase of VK when the device operates under RF

conditions.

The term traps refers to energy states in the bandgap of the semiconductor

[Has13]. As we previously mentioned, the presence of traps can be the consequence

of crystal defects, dislocations or impurities, etc. Trap states in the upper part of

the bandgap, above the neutral level, which means closer to the conduction band,

are acceptor-like, neutral when are empty and negatively charged when occupied

[Has13]. On the other hand, trap states in the lower part of the bandgap, below

the neutral level, which means closer to the valence band, are donor-like, positively

charged when are empty and neutral when occupied [Has13]. Their possible location

are the AlGaN surface, the AlGaN layer as well as the GaN bulk [Kal09], and at

the interfaces between layers of di�erent materials.


Figure 1.14: Dispersion in I-V characteristics of GaN-based HEMT under DC andRF conditions due to the presence of traps [Alo12].

� Trap states at the AlGaN surface: their presence has been con�rmed by

measurements of surface potential using �oating gate. These experiments

demonstrated that the surface became negatively charged under large drain

bias in the o�-state, which can be explained by the presence of donor-like

surface states on the AlGaN surface [Vet00].

� Trap states in the AlGaN layer: these traps are attributed to carbon and

oxygen, whose concentration has been found to be higher than in GaN and

increases with the Al content [Kal09].

� Trap states in the GaN layer: GaN bu�er layers usually grow as a weakly

n-type material due to the presence of oxygen and nitrogen vacancies [Pea99].

However, semi-insulating GaN bu�er is required for the reduction of the leak-

age current [Vet00, Kal09]. Therefore, the method known as compensation is

used for obtaining semi-insulating GaN layers and involves doping the mate-

rial with impurities, which leads to the introduction of many traps states in

the GaN bu�er layer [Vet00, Kal09]. These introduced traps are believed to

be acceptor-like [Kal09].


Figure 1.15: Current collapse in GaN HEMTs I-V output characteristics (i) beforeand (ii) after the application of VDS = 20 V [Kha04b].

� Trap states at the interfaces (i.e., between layers of di�erent materials): the

presence of these traps can be related to dislocations of the crystalline struc-

ture due to mismatch of crystalline lattices and thermal or mechanical stress

during the crystal growth [Zam09].

The main trapping e�ects are the current collapse and the gate lag. The current col-

lapse was �rst reported in an AlGaN/GaN HEMT by Khan et al. in 1993 [Kha93].

Figure 1.15 shows the current collapse after applying a large drain-source bias. IDcan be recovered under illumination conditions as was previously demonstrated in

GaN MESFET [Bin97] (see �gure 1.16). Figure 1.17 reports the ID dependence on

the wavelength of the light source in GaN MESTET [Bin97]. The di�erent wave-

lengths penetrated across the entire bu�er layer of the MESFET suggesting that the

majority of the trap states were in the bu�er layer [Bin02]. These results regard-

ing MESFET devices suggested that deep traps in the highly resistive bu�er layer

caused the current collapse which was later con�rmed [Bin02]. Similarly, studies

on GaN HEMTs have also pointed out that trap states in the GaN bu�er layer

dominate the current collapse [Kal09].

On the other hand, the gate lag, previously described, corresponds to a recov-

erable reduction in the ID when the VGS is abruptly changed. It is widely accepted


Figure 1.16: Output characteristics illustrating current collapse and the ID recoveryunder illumination conditions for GaN MESFET [Bin97].

Figure 1.17: Dependency of ID recovery on the light wavelength [Bin97].


Figure 1.18: (a) Location of the virtual gate in the device and (b) schematic repre-sentation of the device including the virtual gate [Vet01].

that gate lag is directly related to trap states at the surface [Vet01] since several

studies con�rmed the relationship between surface traps and gate lag; for exam-

ple, the gate lag decreases with annealing or the deposition of a passivation layer

[Gre00]. It can be explained by the formation of the virtual gate. The virtual gate

is assumed to be located in the gate-to-drain region, being in series to the depletion

layer underneath the gate [Kho03], and it acts as a negatively biased gate due to

the presence of negative charge on the surface [Men04, Kua08]. Whereas the gate

electrode potential is controlled by the applied gate bias, the virtual gate poten-

tial is controlled by the total amount of trapped charge in the gate-to-drain access

region (see �gure 1.18). Interestingly, bulk traps may also contribute to gate lag

which would be due to the capture of hot electrons from the channel in the bu�er

traps, depleting the 2DEG and hence, reducing the ID [Bra04, Kal09].

The assessment of trap states and their e�ects are essential since they not

only limit the device performance but also play a crucial role in terms of relia-

bility [Joh11]. There are several techniques for the characterization of trapping

phenomena in GaN-based HEMTs detailed in [Men11]. For example, gate (drain)

lag measurements, based on the analysis of the ID delay in response to a gate (drain)

voltage change, can provide information on the time constant of the trapping phe-

nomena [Tir07, Men04]. Double-pulse ID-VDS and ID-VGS measurements allow the

quick and reliable characterization of current collapse and the extraction of valuable

information regarding changes in ID, VTH and on-resistance (RON) [Men11]. The


study of ID transients in the on-state after the device exposition to an o�-state (a

negative gate bias, or a high drain-gate voltage) through multi-exponential tran-

sient measurements may provide an accurate description of some aspects of the

traps [Men04, Men13].

Research groups have made several attempts to reduce the in�uence of trap-

ping e�ects. For example, SiN passivation was found useful to reduce the gate lag

e�ects [Gre00]; �eld-plate was demonstrated to decrease the current collapse and

especially the drain lag [Hor09]; and in situ SiN cap layer was proved to be po-

tentially helpful to reduce the current collapse [Tad10, Ale13]. However, further

studies are required to better understand the presence of trap states in order to

�nd out the optimal way for the reduction of the trapping e�ects.

Self-heating

High current and high voltage result in a heat generation in the channel which leads

to a rise in the lattice-temperature, mainly caused by power dissipation problems

[Gas98, Kuz02b]. Experiments and simulations have demonstrated that high tem-

perature near the 2DEG reduces both the ID (see �gure 1.19) and the operation

frequency mainly due to the reduction of the electron mobility [Ga98] and the drift

velocity [Hu06, Par04]. Self-heating a�ects the reliability of the device through

accelerated aging and electromigration of the metallization which result in device

failure [Kub02, Gon11]; therefore, heat dissipation management is a critical issue

to enable reliable and e�cient GaN HEMT power operation [Alo12].

Several measurement techniques have been developed for the estimation of

the channel temperature (Tchannel), such as microphotoluminescence [Gon11], scan-

ning thermal microscopy [Aub07], and micro-Raman spectroscopy [Kub02]. Some

of them are based on DC [McA06] or pulsed measurements [Joh09]. The results

presented in the literature indicated that the substrate pays a key role in the ther-

mal management, therefore, the higher is the thermal conductivity of the substrate

the lower Tchannel values are reached. However, substrate is not the only parameter

to take into account during the design stage since the layout of the device plays

a major in�uence on self-heating [Alo12]. Further studies are required to evaluate

the role of the design parameters by means of experimental and simulation tools.


Figure 1.19: I-V output characteristics of a device. ID decreases in the saturationregion as consequence of self-heating [McA09].

1.2 Framework: RUE and AEGaN projects

This thesis has been developed in the semiconductor device group belonging to the

Instituto de Sistemas Optoelectrónicos y Microtecnología (ISOM) of the Universi-

dad Politécnica de Madrid (UPM). It has a great experience in the research of GaN-

based devices, such as photodetectors [Pau03, Mon00, Riv07], LEDs [Fer01, Nar03],

SAWs [Ped07, Rod12], MEMS [Sil08], and HEMTs [Cal03, Gon09, Jim03, Rom10,

Wan14a]. After years of extensive studies regarding di�erent aspects of HEMTs,

for instance the growth of AlGaN/GaN heterostructures by molecular beam epitaxy

(MBE) devoted to the fabrication of HEMTs [Jim03], this group was involved in

the project KORRIGAN. This 5 year European project was launched in 2005 and

its challenging �nal aim was to accelerate the development of independent GaN

HEMT foundries in Europe [Gau06]. The group worked actively in the workpack-

ages related to material study, device processing, and reliability. For example, the

structural and electrical characterization of the GaN-based heterostructures was

carried out to identify the limiting factors of the HEMTs performance and their

main failure mechanisms [Gon09]. Moreover, it contributed to the processing of

1.2. FRAMEWORK: RUE AND AEGAN PROJECTS 29

GaN-based HEMTs, especially in the formation of ohmic contacts, thermal stabil-

ity of Schottky contacts and device passivation [Rom10]. On the other hand, some

of their major thermal issues were also assessed by the group in the framework of

this project [Cue09, Cue11]. The knowledge acquired during the participation in

the KORRIGAN formed the base for the achievement of the goals of two national

projects: RUE and AEGaN, which were the framework of this thesis. It is im-

portant to note that, unlike the KORRIGAN project, which was more focused on

the development of GaN-based HEMTs for high frequency applications, RUE and

AEGaN projects were devoted to development of HEMTs for power switching ap-

plications (in the order of few dozens of MHz). Therefore, the layout of the devices

needed to be modify to meet the requirements of the new applications.

1.2.1 RUE project

�Advance Wide Band Gap Semiconductor Devices for Rational Use of Energy

(RUE)� is a 5 year national project which belongs to the Consolider-Ingenio 2010

programme of the Spanish Ministry of Science and Innovation (MICINN) whose

project number is CSD 2009-00046. Recently, a one-year extension has been given

by MICINN-MINECO thanks to the promising results obtained in the last months.

This project is the �rst one in Spain which integrates in a consortium di�erent

pro�les of power electronics research groups, some devoted to the physics and ma-

terial science, others to the solid-state device and processing technology and others

dedicated to the electrical and electronic circuit and systems development. Table

1.8 shows the groups which formed the consortium as well as their main areas of

work.

The idea of this project arose from the fact that power electronics plays a

key role in the generation-storage-distribution cycle of the electric energy since

the main portion of the generated electric energy is consumed after undergoing

several transformations, many of them performed by power electronic converters.

The power losses in these power electronic converters are dissipated in their power

semiconductor devices, which are currently based on the mature and well established

silicon technology [Mil08]. However, in the last years, the so-called wide bandgap

semiconductor devices have been demonstrated to be promising candidates for its

integration in this kind of power electronics since they could overcome the limits

of silicon device performance. Therefore, the general purpose of RUE project is


Table 1.8: Research groups and their areas of work within the RUE project.

GROUPAREA OF

WORK

Centro Nacional de Microelectrónica (CNM)Materials &

Devices

Instituto de Sistemas Optoelectrónicos y Microtecnología de la

Universidad Politécnica de Madrid (ISOM-UPM)

Materials &

Devices

Centro de Electrónica Industrial de la Universidad Politécnica de

Madrid (CEI-UPM)

Materials &

Devices &

Applications

Grupo de Sistemas Electrónicos de Alimentación y Grupo de

Accionamientos Eléctricos de la Universidad de Oviedo (UO)

Applications

Laboratorio de Electrónica Industrial e Instrumenatción Universidad

de Valencia (UV)

Devices &

Applications

Centro de Investigación en Electrónica de Potencia de la Universitat

Politècnica de Catalunya (UPC)

Materials &

Devices &

Applications

Grupo de Electrónica de Potencia y Microelectrónica de la

Universidad de Zaragoza (UZ)

Applications

Grupo de Automática y Electrónica Industrial de la Universitat

Rovira I Virgili (URV)

Applications

Unidad de Energía de TECNALIA Corporación Tecnológica (RBTK) Applications

to develop a �rst generation of wide bandgap power semiconductor devices and

their related technologies and electronics, such as suitable packages, drivers and

controllers (see �gure 1.20). This will allow the use of these devices in real power

applications where the actual devices based on silicon can not be used due to their

limitations in voltage blocking capability, working temperature range and switching

speed [Rue14]. In order to ful�ll this main objective, some intermediate goals were

planned to be achieved:

1. Concerning materials and devices:

� To overcome the main limitations of the SiC devices, such as low MOS

channel mobility, metallization problems at high temperature, passiva-

tion schemes, etc.

� To develop a �rst generation of GaN power devices for very high switch-

ing speed power electronics in the same temperature range as the silicon


devices.

2. Regarding characterization, control and packaging:

� To develop new characterization, testing and modeling tools and proto-

cols adapted to the new voltage, temperature and frequency operation

ranges.

� To provide the additional circuitry, such as speci�c drivers and con-

trollers, for the integration of the wide bandgap semiconductor devices

in real applications.

� To �nd an optimal package solution for the integration of the devices in

real applications.

3. Related to real applications:

� To design, build and assess speci�c power converters which could per-

form either at high temperature or under radiation hardness or at high

frequency maintaining high e�ciency.

� To demonstrate the advantages of the developed devices and systems in

the applications where Si devices can not performed as well as in those

where they present some advantages, for example, an improved e�ciency,

smaller size or faster transient response in comparison with the existing

devices which nowadays cover these applications.

The proposal of this project is summarized in the �gure 1.21 which also shows the

issues where the research e�orts are more focused on:

� Regarding wide bandgap semiconductor materials and processing, new ap-

proaches are oriented to overcome the Si limitations by means of the de-

velopment of innovative processing based on improved surface preparation,

optimized insulator layers, and interface control [Rue14].

� Concerning wide bandgap semiconductor solid-state devices, the previous in-

novative approaches will be applied to the processing of cutting-edge wide

bandgap devices, summarized in �gure 1.22. For instance, whereas switches

based on 4-H SiC MOSFETs will be developed to operate between 600 V and

1.2 kV, at a frequency lower than 100 kHz, and at very high temperature; GaN


based HEMTs will be optimized to operate as switches in a voltage range of

200 V and 1.2 kV, at high frequency (10 MHz-30 MHz), and high temperature

(100°C-200°C).

� Related to packaging, thermal management, electrical and physical modeling

and novel drivers and controllers, the previous innovative wide bandgap de-

vices will present a high temperature operation capability, which will lead to

higher dissipated power densities with higher junction temperatures than the

current power semiconductor devices. Moreover, new controllers and drivers

are needed for SiC and GaN devices, due to their temperature and frequency

ranges, normal state and activation logic. Furthermore, powerful models are

also required for system design [Rue14].

The ISOM group is in charge of the following tasks related to GaN-based devices:

� Improvement of the reliability of both, ohmic and Schottky contacts.

� Assessment of novel passivation schemes.

� Development of devices for high voltage, high switching speed and high tem-

perature operation.

� Design of new protocols for their electro-thermal characterization.

� Evaluation of their failure mechanisms and reliability.

1.2.2 AEGaN project

The project called �Ampli�cadores de Envolvente de Banda Ancha para EER/ET

y fabricación de dispositivos de nitruro de galio (AEGaN)� was a 3 year national

project launched in 2010 and funded by MICINN-MINECO. Three research groups

from three centers in Universidad Politécnica de Madrid were involved in the devel-

opment of di�erent aspects of the power electronics in the framework of this project:

the CEI which is specializing in the design of circuits and integrated circuits; the

Grupo de Ingeniería de Radio (GIRA), whose area of expertise is related to the ra-

dio techniques, and the ISOM dedicated to the development of GaN-based devices.

The general purpose of this project was the improvement of the radiofrequency and

microwave linear high e�ciency power ampli�ers for communication applications in


Figure 1.20: General purpose of RUE project [Mil11].

Figure 1.21: The RUE proposal [Rue14].


Figure 1.22: Diagram of the potential operating conditions (voltage, frequency,and temperature) of the wide bandgap semiconductor devices involved in the RUEproject [Rue14].

the UHF and microwave bands. To accomplish it, advanced linearization techniques

based on envelope elimination restoration (EER) and envelope tracking (ET) were

improved as well as new semiconductor technology was implemented for the inte-

gration of GaN-based HEMTs as switching devices. The �nal goal is to achieve 10

MHz-20 MHz bandwidth with 50 W-100 W output power ampli�er to be used in

base stations.

The main tasks carried out by the ISOM group in the framework of this

project were:

� Development of GaN-based devices which met the requirements of power

switching devices.

� Evaluation of the HEMTs performance taking into account its �nal applica-

1.3. MOTIVATION AND OBJECTIVES 35

tion.

� Modeling of GaN-based HEMTs.

� Studies of reliability and failure mechanisms of the developed devices.

Note that the promising results obtained during this project facilitated the award

of another national project more focused on aerospace applications called Conver-

tidores de Alta Velocidad de Conmutación Multinivel y Multifase para Aplicaciones

Espaciales (CAVE).

1.3 Motivation and objectives

The motivation of this thesis is the contribution to the development of a new gen-

eration of GaN-based HEMTs which will present some relevant advantages in com-

parison with the existing devices based on silicon regarding power switching appli-

cations, specially at high temperature operation. The main purpose is to overcome

the limitations that the current silicon devices show, which are related to the low

blocking voltage capability, the limited range of operating temperature and the

velocity response. The following objectives are pursued:

� The optimization of the fabrication processing which is already known by the

group in which this thesis is developed [Jim03, Cal03, Rom10].

� The development of E-mode devices using di�erent approaches which involve

the recess of the region under the gate, a �uorine treatment or a combination

of both.

� The evaluation of di�erent device designs and geometries to �nd out the

optimal one for each kind of applications. The variable parameters are LG ,

WG, LGD, and the number of gates.

� The optimization of the assessment protocol of the electrical characterization

in order to adapt them to the new current and temperature ranges, taking

into account the previous experience of our group [Cue08].

� The performance assessment of the fabricated devices at high temperature

since many of their possible applications would involve harsh environment

and high ambient temperature.


� The study of some issues related to the reliability and the failure mechanisms,

in particular the topics linked to trapping e�ects and self-heating ,which can

reduce the device performance and the long-term reliability. Moreover, special

attention are paid to the in�uence of some aspects, such as the substrate, the

cap layer or the device geometry on these issues. It is important to mention

that a mandatory task to achieve this objective is the development of a new

pulsed system which enable these studies.

1.4 Dissertation organization

The thesis is divided into seven chapters. This �rst chapter corresponds to the in-

troduction where the state-of-the-art of GaN-based HEMTs and their fundamentals

have been discussed, as well as the framework of this thesis and its main objectives.

Then, the second chapter deals with the main experimental techniques used

in this work. Firstly, it illustrates the fabrication of HEMTs, including the opti-

mization of ohmic contacts formation. Afterward, the electrical characterization

procedures are described.

In the third chapter, di�erent procedures proposed for the fabrication of

normally-o� devices are described in detail. Moreover, it also includes the eval-

uation of the performance of the fabricated D-mode devices.

Chapter 4 is devoted to the assessment of HEMTs operating at di�erent tem-

perature. It presents the performance of AlGaN/GaN devices in a wide temperature

range as well as the e�ects of thermal stress on the device performance. Moreover,

it is also discussed the high temperature performance of InAlN/GaN HEMTs with

di�erent layout and geometries.

Chapter 5 addresses di�erent aspects of the self-heating. For instance, a new

electrical method for the estimation of the channel temperature is proposed. The

in�uence of the geometrical parameters of the devices on the self-heating is also

investigated.

Chapter 6 is mainly focused on two tasks related to trapping e�ects. The

�rst one is the evaluation of the potential bene�ts of di�erent cap layers in terms

of reduction of trapping e�ects; and the second one is the study of the trapping

e�ects in both AlGaN and InAlN barrier devices.

Finally, chapter 7 summarizes the conclusions that can be drawn from the

work described in this thesis and provides recommendations for future research.

1.4. DISSERTATION ORGANIZATION 37

On the other hand, appendix A describes the double-pulsed set-up devel-

oped during this thesis, including both aspects: the hardware and the software.

Furthermore, appendix B summarizes the HEMTs studied during this thesis.

Chapter 2

Experimental techniques

This chapter describes the main experimental techniques involved in this thesis

work. Firstly, the technique used for the epitaxial growth of the heterostructures as

well as the samples used during this dissertation are presented. Then, the following

sections are focused on the description of the device fabrication steps. An overview

of the main structures used for testing the quality of each fabrication step is also in-

cluded. The third part of this chapter is dedicated to the electrical characterization

methodology. The measurements conducted for the characterization of diodes and

MIS-diodes and the DC are described. Furthermore, the pulsed characterization

performed in HEMTs is explained in detail.

2.1 Epitaxial growth and samples

In spite of the outstanding properties of GaN, its technical development came later

than in the case of other semiconductors. This is due to the lack of commercial

free-standing GaN substrates which leads to the heteroepitaxial growth of GaN

on a di�erent substrate. A suitable substrate would be a material which presents

similar physical and crystallographic properties to GaN, such as lattice parameters

and thermal expansion coe�cients [Gre12]. Sapphire (Al2O3), SiC and silicon are

the more common substrates, although other materials have also attracted the

attention of the scienti�c community, for instance, diamond could improve the

thermal management [Van09]. Moreover, several e�orts have been made to achieve

free-standing GaN substrates [Sto07], but the quality of the grown material is not

good enough yet. Table 2.1 shows the main advantages and drawbacks of substrates

39

40 CHAPTER 2. EXPERIMENTAL TECHNIQUES

Table 2.1: Main advantages and drawbacks of the substrates used during this thesis.

SUBSTRATE ADVANTAGES DRAWBACKS

Sapphire

Ideal for optoelectronics

applicationsLarge lattice and thermal

expansion coe�cient mismatchInsulating

Cheap

Can withstand the high

temperature required for the

GaN growth

SiC

Low lattice and thermal

expansion coe�cient mismatchInvalid for UV devices

Best candidate for power

applications thanks to its high

thermal conductivity

High price

Si

Possible integration with the

mature Si electronics

technology

Large lattice mismatch and

very large expansion coe�cient

mismatch which lead to the

formation of cracks and defects

Low costLarger substrate diameters

used during this thesis.

The development of the GaN technology requires not only the selection of a

suitable substrate, but also the employment of the most appropriate growth tech-

nique to obtain high quality material. Nowadays, metal organic chemical vapor

deposition (MOCVD) has become the most used technique to grow GaN, although

there are other epitaxial techniques, such as hydride vapor phase epitaxy (HVPE)

and molecular beam epitaxy (MBE). The heterostructures used during this disserta-

tion were grown by MOCVD. This technique presents some important advantages,

for instance, a superior quality of the grown material, comparable to MBE, the

high degree of composition control and uniformity, the reasonable growth rates (1-2

μm/h) and the possibility to use high purity chemical sources and to grow abrupt

junctions [Gre12].

MOCVD uses as precursors for the reaction the trimethylgallium (TEGa),

the treimethylaluminum (TEAl) or the trimethylindium (TEIn) for the group III

and the ammonia (NH3) for the group V. They are carried to a heated substrate by

carrier gases (hydrogen and/or nitrogen) where gas phase reaction occurs [Cho09].

This reaction takes place close to the substrate and needs to be kept at high tem-

2.2. DEVICE FABRICATION AND TESTING 41

perature (1000°C-1100°C) due to the low cracking e�ciency of NH3. The control

of the N/Ga molar ratio is a critical aspect and it is mandatory to keep it high in

order to compensate the nitrogen losses due to the high partial nitrogen pressure

at the high growth temperature [Kel96].

Samples used in this thesis are summarized in table 2.2. Samples with both

AlGaN and InAlN barriers have been tested. In same cases they were grown in col-

laborating institutes (Picogiga, Qinetiq) whereas in other cases they were purchased

from privates companies (EpiGaN, Novagan).

2.2 Device fabrication and testing

The processing of HEMTs is a complex and challenging task since it consists of

several steps which depend critically on the previous ones. Therefore, speci�c test

structures are required to enable the veri�cation of each step before starting the next

one. This section is devoted to the description of the standard HEMT fabrication

procedure including the optimization of the ohmic contact formation as well as the

tests performed during the device processing.

2.2.1 Device layouts

The device fabrication was carried out at the ISOM facilities and, as a result of

a fruitful collaboration, at the Naval Research Laboratory (NRL). Furthermore,

some HEMTs, already processed and coming from III-V Labs (France) and the

Fraunhofer Institute (Germany), were also included in some of the experiments

presented in this dissertation. Concerning the device fabrication developed at the

ISOM facilities, the mask used for the processing of the devices studied in the �rst

experiments was the one known as PCM (Processing Control Monitoring). It was

designed during the KORRIGAN project, which was devoted to the development

of GaN-based HEMTs for high frequency applications. Therefore, these devices

exhibited short gate length as well as short gate-to-drain distance values. Figure

2.1 illustrates a simpli�ed scheme of one cell of the PCM mask, which includes both

test structures and RF two-�nger HEMTs.

Then, a mask was designed to meet the requirements of the RUE and AEGaN

projects, devoted to power switching applications. Therefore, the gate length of the

devices are not required to have sub-micron values. This new mask called ISOM2010


Table 2.2: Samples used in this thesis with respective origin, the study where theywere involved and the chapter where it is discussed.

STRUCTURE ORIGIN STUDY CHAPTER

GaN/AlGaN/GaN/Si PicogigaFabrication of E-mode devices:

�uorine treatments

3

Performance of E-mode and

D-mode devices at high

temperature

4

InAlN/AlN/GaN/Si

Novagan Wet etching for gate-recess 3InAlGaN/AlN/GaN/SiC

InAlGaN/AlN/GaN/Al2O3

GaN/InAlN/AlN/GaN/SiC III-V Labs Performance at hightemperature

4

GaN/AlGaN/GaN/Si Picogiga

Self-heating evaluation

5

GaN/AlGaN/GaN/SiC Picogiga

AlGaN/GaN/Al2O3 Qinetiq

Tchannel versus device geometry

GaN/InAlN/AlN/GaN/SiC NovaganTrapping e�ects on AlGaN and

InAlN barrier devices6

GaN/AlGaN/GaN/SiC Picogiga

GaN/AlGaN/GaN/Si

EpiGaN

Performance at hightemperature

4

Impact of di�erent cap layers on

trapping e�ects

6

in situ SiN/AlGaN/GaN/SiPerformance at hightemperature

4


trapping e�ects

6

in situ

SiN/GaN/AlGaN/GaN/Si

Performance at hightemperature

4


trapping e�ects

6


Figure 2.1: Simpli�ed scheme of one cell of the PCM mask.

not only included the test structures and the RF two-�nger devices present in the

PCM mask, but also one �nger devices with variable geometry. Figure 2.2 describes

the layout of one cell of the ISOM2010 mask.

On the other hand, the mask used for the device fabrication at NRL is similar

to the ISOM mask but it also includes a greater number of one-�nger HEMTs

with variable geometries, which enabled the evaluation of the geometry impact on

di�erent reliability aspects (see �gure ).

2.2.2 Fabrication technology

Figure 2.4 shows a simpli�ed �ow chart of the standard device fabrication whose

steps are described below.


Figure 2.2: Scheme of one cell corresponding to the ISOM2010 mask.

Surface cleaning

Surface cleaning is a mandatory step to prepare the surface (see �gure 2.5). It is

always performed with organic solvents, such as acetone and isopropanol, to remove

all the residues. Moreover, semiconductors usually develop a thin oxide cap on top,

which requires a cleaning with acids, such as hydro�uoric (HF) or hydrochloric acid

(HCl). This cleaning procedure is also carried out before several steps, such as

metallization, to reduce impurity and interface defects at the metal/semiconductor

boundary as well as to improve adherence.

Electrical isolation

Electrical isolation is an essential step because devices fabricated in the same sample

are connected through the 2DEG, and to minimize current leakages. It is usually

achieved thanks to the creation of �islands� where devices are fabricated. This


Figure 2.3: Scheme of one cell corresponding to the NRL mask.

procedure is known as MESA isolation. Its depth depends on the 2DEG location,

typically higher than 50 nm, since the GaN layer is insulator. The process consists

of a photolithography step followed by a dry etch step.

Photolithography

Firstly, a photoresist is deposited and spun in order to be uniformly distributed

on the heterostructure surface and then, the photoresist is baked. Secondly, the

photoresist is exposed selectively to UV-light thanks to a mask (see �gure 2.6a).

Figure 2.7 shows the UV photolithography system used at the ISOM facilities. The

minimum resolution depends on the wavelength of the light used, being in practical

cases greater than or equal to 1 μm. The UV-light changes the properties of the ex-

posed photoresist, becoming more soluble in a speci�c solution called developer (see


Figure 2.4: Flow chart of a standard device fabrication.

Figure 2.5: Surface cleaning procedure.


(a) (b)

(c)

Figure 2.6: Electrical isolation procedure. (a) Optical lithography, (b) result ofdeveloping the pattern, and (c) structure after the dry etching.

�gure 2.6b). Therefore, at this point, the material is patterned with the photoresist

which is resistant to other treatments.

Etching

The aim of this process is the removal of the material which is not covered with

photoresist (see �gure 2.6b) to achieve the device electrical isolation and the def-

inition of the device active area (see �gure 2.6c). The etching can be performed

by wet or dry procedures. However, the development of wet etching processes is

a challenging issue due to the good chemical stability of GaN [Str92]. Thus, dry

etching techniques have been used as a reliable way to pattern in this materials.


Figure 2.7: Karl Suss KG UV photolithography system.

The MESA etching requirements are high etch rate, anisotropic pro�les,

smooth sidewalls as well as low induced damages, selective etching of one layer

over another and smooth surface morphology [Pea99]. Two dry etching techniques

were used during this dissertation, the reactive ion etching (RIE), and the induc-

tively coupled plasma etching (ICP):

� Reactive ion etching: its etch mechanism is based on both chemical and phys-

ical components which enable the achievement of anisotropic pro�les, dimen-

sional control and high etch rates. Figure 2.8a shows the schematic of the

RIE system. A radiofrequency power, typically of 13.56 MHz, generates the

plasma between two parallel electrodes in a reactive gas. The substrate is

placed on the powered electrode where a potential is induced, and ion with

typical energies of a few hundred eV are produced. RIE is operated at low

pressures which promotes anisotropic etching thanks to increased mean free

paths and reduced collisional scattering of ions during acceleration in the

sheath [Pea99]. The recipe used for RIE etching at ISOM is the following:

� Gases: SiCl4 / Ar / SF6

� Pressure: 33 mTorr

� RF power: 120 W

� DC bias: 290 V


� Step: 200 nm approximately

� Inductively coupled plasma etching also uses both chemical and physical com-

ponents as etch mechanism, but with the advantage of having a higher density

plasma. ICP plasma is formed in a dielectric vessel encircled by an inductive

oil into which a radiofrequency power is applied. The alternating electric �eld

between the coils induces as strong alternating magnetic �eld trapping elec-

trons in the center of the chamber and generates a high-density plasma (see

�gure 2.8b). Since ion energy and plasma density can be e�ectively decou-

pled, uniform density and energy distributions are transferred to the sample

while keeping ion and electron energy low. This leads to fast etch rates and

lower damages. Moreover, anisotropy can be achieved by superimposing a

radiofrequency bias on the sample. The following recipe was used for the ICP

etching at ISOM:

� Gases: Cl2 / Ar


� ICP / RIE power: 40 W / 100 W

� DC bias: 367 V


The ICP etching recipe used at NRL is:

� Gases: Cl2 / Ar



� DC bias: 160 V


Ohmic contact formation

The drain and the source of HEMTs are formed by ohmic contacts and therefore,

their quality has a huge impact on the adequate performance of the device. High

power and high frequency applications require the formation of ohmic contacts with

the following characteristics:


(a)

(b)

Figure 2.8: Schematics of (a) RIE and (b) ICP systems.


� Low contact resistance (RC) which leads to:

� Higher ID.max

� Lower access resistance to the 2DEG, which means a decrease of the VK

� Higher fT and fmax by maximizing the extrinsic transconductance (gm)

which can be expressed as [Rom10]:

gm =gmint

1 +RS ·gmint

(2.1)

where gmint is the intrinsic transconductance and RS is the source resis-

tance, which corresponds to the gate-source sheet resistance (Rsheet.gs)

and RC.

� Good de�nition which enables the possibility of reducing the gate-to-source

distance. This leads to the reduction of Rsheet and hence, the increase of gm.

Moreover, this also increase the VBD.

� Smooth surface morphology to facilitate the photolithographies and the de�-

nition of the alignment masks for next steps [Rom10].

� Good mechanical stability to avoid damages during tests and bonding.

� Good thermal stability to enable the performance at the high temperature

caused by either self-heating or ambient temperature.

The ohmic contact processing involves di�erent processes, �rstly a photolithography

is carried out to de�ne the areas of the ohmic contacts. Then, the metal stack is

evaporated and lifted-o�. Finally, a thermal annealing is performed to di�use the

metals through the semiconductor to contact with the 2DEG.

Photolithography

This procedure is similar to the previous one described in the MESA process. The

photolithography and the posterior photoresist developing are shown in �gure 2.9a

and �gure 2.9b, respectively.


Metallization

The metallization schemes more widely used for the formation of ohmic contacts

are based on Ti / Al, for example, Ti / Al / Ti / Au [Bar06], Ti/Al/Ni/Au [Cre03].

Latter, refractory metals like molybdenum or wolfram has also been included in the

stack, e.g. Ti / Al / Mo / Au [Sun05, Bar06]. The Ti / Al ratio is the responsible for

the formation of the ohmic contact with very little consumption of the barrier layer

[Fay02, Bri01]. After this reaction, a thin layer of AlN, TiN, or AlTi2N is present

at the interface creating a high n-type region underneath the contacts, which is

believed to be generated by nitrogen vacancies [Cre03]. Au layer is used to not only

make the wiring less resistive, but also avoid the oxidation of the Ti / Al. However,

it can di�use towards the semiconductor. Therefore, a metal barrier (Ti, Ni, or Mo)

is required to prevent the ohmic contact degradation caused by the di�usion of Au.

Initially, the metal stack used in the device fabrication done at the ISOM

facilities was (20 nm) Ti / (80 nm) Al / (50 nm) Ti / (55 nm) Au. However, the

metal multilayer was optimized during this work substituting the Ti barrier layer by

a Ni layer. Moreover, the Ti/Al ratio was also optimized since it was demonstrated

to be crucial for the ohmic contact formation [Fay02, Bri01]. The optimal ratio was

found to be 20 nm / 120 nm. Then, two di�erent Ni thicknesses (30 nm and 40 nm)

were investigated obtaining better results with the Ni layer of 40 nm. Finally, the

resulting optimized metal stack was (20 nm) Ti / (120 nm) Al / (40 nm) Ni / (50

nm) Au. Similarly, the metal stack used for the fabrication of the ohmic contacts

at NRL is (20 nm) Ti / (120 nm) Al / (40 nm) Ni / (80 nm) Au.

The metallization involves some steps:

1. Surface cleaning with a low power O2-plasma is carried out to remove any

rest of developed resist.

2. Surface cleaning with an acid solution of HF : H2O (1:10) is performed before

the metal evaporation to prepare the surface removing any oxide.

3. Metal deposition by means of an e-beam evaporation system (see �gure 2.10a).

Figure 2.10b shows the scheme of this technique which consists of the bom-

bardment of a target anode with an electron beam given o� by a charged

tungsten �lament under high vacuum. The electron beam causes atoms from

the target to transform into the gaseous phase. These atoms then precipitate


into solid form, coating everything in the vacuum chamber with a thin layer

of the anode material.

4. Lift-o� of the deposited metal on the resists basically immersing the sample

in acetone (see �gure 2.9d).

Thermal annealing

A thermal annealing is required to di�use the metals towards the 2DEG and hence

achieve the ohmic behavior. The annealing is performed at a temperature between

800°C and 900°C and in inert atmosphere. During this dissertation, it was carried

out the optimization of the annealing recipe for devices fabricated at ISOM. The

particularities of the rapid thermal annealing (RTA) system used at ISOM (see

�gure 2.11a) leads to the need for a two-step annealing to assure the stability of the

annealing temperature. The recipe consists of a �rst step of 7 s at 800°C followed

by a second step of 30 s at 870°C in N2 atmosphere (see �gure 2.11b). On the

other hand, the thermal annealing recipe used at NRL was 850°C during 30 s in N2

atmosphere.

Schottky contact formation

The formation of Schottky contact, which corresponds to the gate electron of the

device, is a critical step. The main requirements that it should meet are:

� Low gate resistance (RG).

� Low leakage current.

� High VBD.

� Good thermal stability.

It is important to note that the geometry of the Schottky contact has a huge

in�uence on the performance of the device as was previously explained in chapter

1:

� Decreasing LG increases the value of important device parameters, such as ID,

fT, and fmax. However, the possible minimum LG depends on several aspects,

such as the layer thicknesses of the heterostructure, the short channel e�ects,


(a) (b)

(c) (d)

(e)

Figure 2.9: Procedure of ohmic contact formation. (a) Photolithography, (b) pho-toresist developing, (c) metallization, (d) lift-o�, and (e) ohmic contact after ther-mal annealing.


(a) (b)

Figure 2.10: (a) E-beam evaporation system used at the ISOM facilites and (b)scheme of an e-beam evaporation [Eng14].

(a) (b)

Figure 2.11: (a) RTA system and (b) scheme of the two-steps thermal annealing.


(a) (b)

Figure 2.12: Pictures of fabricated devices with (a) one and (b) two �ngers.

the available facilities for the device fabrication and the transmission line

resistance of the gate or RG, which increases with decreasing LG.

� Increasing WG leads to higher ID and hence higher power density. However,

for microwave applications, the enlargement of WG is limited by the increase

of RG, which leads to a reduction of fmax. A possible way to increase the WG

is the connection in parallel of several �ngers.

� The more common multi�nger layouts are T-shape and U-shape which presents

higher self-heating due to the proximity of its �ngers.

Devices with one (see �gure 2.12a) and two-�ngers (see �gure 2.12b) were fabricated

and studied during this thesis. Their LG values were between 500 nm and 6 μm

whereas their WG values were between 100 μm and 300 μm.

Figure 2.13 shows the main steps for the fabrication of Schottky contacts

which are basically the lithography and the metallization.

Lithography

Photolithography and e-beam lithography were used to pattern the Schottky con-

tacts. Whereas the photolithography has a minimum resolution of 1 μm, the e-beam

lithography shows a much high resolution (approximately 10 nm of the ISOM's sys-

tem).

In the case of the e-beam lithography, the sample is covered with an electron

sensitive resist. Then, a focused e-beam is used to scan the sample drawing the


pattern. The exposition to the e-beam changes the resist properties enabling the

selective removal during the developing.

Metallization

This process has been already described in the formation of the ohmic contacts.

The metal stack used for the formation of Schottky contacts was Ni / Au at both

ISOM and NRL, although the thickness of the metals were slightly di�erent, being

30 nm / 170 nm for devices processed at ISOM and 20 nm / 200 nm for devices

fabricated at NRL.

Passivation

The passivation is basically the deposition of a passivation layer, typically SixNy,

which not only protects the device but also is believed to decrease the trapping

e�ects previously described in chapter 1. Figure 2.14 illustrates in detail this step.

Firstly, the deposition of the passivation layer over all the sample. Secondly, the

photolithography which patterns the areas where the passivation layer should be

removed to enable the access to the contacts. Finally, the selective etching of the

passivation layer.

Deposition of the passivation layer

The devices fabricated during this thesis were passivated with a SixNy layer de-

posited by plasma-enhanced chemical vapor deposition (PECVD). This technique

achieves the layer deposition by introducing reactant gases between parallel elec-

trodes: a grounded electrode, where the substrate is placed and heated to 250°C

to 350°C and a RF-energized electrode (see �gure 2.15a). The capacitive coupling

between the electrodes excites the reactant gases into a plasma, which induces

a chemical reaction resulting in the product which is deposited on the substrate

[Pla14]. The PECVD equipment used at ISOM is shown in �gure 2.15b. The

following recipe was used for the deposition of the passivation layer at ISOM:

� A prior in situ N2 plasma pretreatment was performed following the details

described in [Fat12]

� Gases: NH3 / SiCH4


(a) (b)

(c) (d)

Figure 2.13: Steps of Schottky contact fabrication: (a) Photolithography, (b) pho-toresist developing, (c) metal evaporation, and (d) the result after lift-o�.


(a) (b)

(c) (d)

Figure 2.14: Scheme of the passivation step: (a) Passivation layer deposition, (b)photolithography, (c) developing and (d) the resulting device after the etching.


(a) (b)

Figure 2.15: Schematic of PECVD and (b) system used at ISOM.

� RF power: 205 W

� Temperature: 350°C

� Thickness: 120 nm approximately

Whereas the recipe used at the NRL for the deposition of the passivation layer was:

� Gases: SiH4 / NH3 / N2

� RF power: 205 W

� Temperature: 300°C

� Thickness: 100 nm approximately

Photolithography

This procedure is similar to the previously described in the formation of the ohmic

contacts.


(a) (b)

Figure 2.16: (a) Scheme and (b) picture of the electrical isolation test structure.

Etching

The aim of this step is the removal of the SixNy layer to enable the contact with

the electrodes of the device. The recipe used at ISOM was:

� Gases: SF6 / Ar



� DC bias: 280V

2.2.3 Checking of the processing steps

This section is devoted to the description of the di�erent test structures which are

fabricated at the same time as the HEMTs to enable the veri�cation of every step.

Electrical isolation test structure

The electrical isolation test structure consists of two ohmic contacts fabricated

in di�erent �islands� (see �gure 2.16). The measurement of the I-V curve between

these two pads provides information regarding the electrical isolation. The isolation

resistance (Risolation) corresponds to the slope of the I-V curve and is typically in

the order of 106 Ω. Figure 2.17 shows the equipments used for the I-V measurements

which are a Karl Suss DC probe station and an Agilent HP4156C semiconductor

parameter analyzer.


(a) (b)

Figure 2.17: I-V measurements setup: (a) Karl SussDC probe station and (b)Agilent HP 4156C parameter semiconductor analyzer.

Transmission line method

The test structure used for testing the quality of the ohmic contacts is the well-

known transmission line method (TLM). It consists of a series of ohmic contacts

separated by various distances (d) as �gure 2.18 shows.

TLM measurements were carried out to extract the values of RC and Rsheet.

Since several resistances are involved in these measurements (see �gure 2.19a), four-

point technique was applied to eliminate the parasitic resistance introduced by the

probes. As �gure 2.19b illustrates, a current (I) is applied between two consecutive

ohmic contacts and the resulting voltage (V) is measured. Taking into account

the equivalent circuit (see �gure 2.19c), and assuming that the resistance of the

voltmeter is much larger than the probe resistance (Rp) and the probe-to-metal

contact resistance (Rcp), these Rp and Rcp can be neglected. Therefore, the total

resistance can be expressed as:

RT =V

I= 2·RC+Rsheet (2.2)

Figure 2.20a illustrates the eq. (2.2). The RT value for each two consecutive


(a) (b)

Figure 2.18: (a) Scheme and (b) picture of a TLM.

ohmic contacts is extracted and plotted. As �gure 2.20b shows, RC value can be

obtained by �tting the RT values to a linear curve and extrapolating to d = 0.

Moreover, the Rsheet can be extracted from its slope since:

slope =Rsheet

W(2.3)

where W is the width of the ohmic contacts.

Note that the equipments used for these measurements were the ones shown

in �gure 2.17.

Schottky diode

The Schottky diode is the test structure fabricated to check the quality of the

Schottky contact which forms the gate electrode (see �gure 2.21). The Schottky

diodes evaluated during the processing of HEMTs consisted of an extended ohmic

contact and a circular metal-semiconductor junction fabricated at the same time as

the gate electrode. Current-voltage measurements were carried out in these devices

using the setup described in �gure 2.17 to obtain valuable information concerning


(a) (b)

(c)

Figure 2.19: (a) Resistances involved, (b) Scheme of I-V and (c) equivalent circuitfor TLM measurements [Che14].

(a) (b)

Figure 2.20: (a) Illustration of RT and (b) representation of its measured values.

2.3. ELECTRICAL CHARACTERIZATION 65

(a) (b)

Figure 2.21: (a) Scheme and (b) picture of a Schottky diode.

Figure 2.22: I-V curve of a Schottky diode.

the quality of the gate Schottky contact. Figure 2.22 shows the I-V curve of a

Schottky diode, where two regions can be easily distinguished: reverse and forward.

The reverse current of Schottky diodes was evaluated during the HEMTs processing

since it is related to the leakage current of the gate electrode.

2.3 Electrical characterization

The studies done during this thesis are mainly based on di�erent electrical protocols.

The description of the electrical measurements carried out are described below.

Note that RF characterization was not performed since the framework of this thesis


(a) (b)

Figure 2.23: (a) Scheme and (b) picture of a van der Pauw structure.

was mainly related to power applications (see section 1.2).

2.3.1 Hall measurements

Magnetotransport measurements are useful to characterize the 2DEG and extract

parameters such as the carrier density and the mobility. During this work, these

kind of measurements were performed using van der Pauw geometry. As �gure 2.23

illustrates, they consist of four ohmic contacts fabricated in the corners of a square

�island�.

Firstly, as �gure 2.24a shows, a current is applied between two parallel con-

tacts (Ixx) and the resulting voltage is measured between the other two contacts

(Vxx). Then, the longitudinal resistance (Rxx) can be calculated as follows:

Rxx =VxxIxx

(2.4)

The resistivity (ρ) can be extracted straightforward from Rxx. Secondly, a

current is applied between two diagonal ohmic contacts (Ixy) and, as �gure 2.24b

shows, the resulting voltage is measured between the other two contacts (Vxy).

Then, the Hall resistance (RH) is calculated as:

RH =VxyIxy

(2.5)

Finally, the carrier density (ns) and the Hall mobility (μH) can be extracted

as [Jim03]:

Documents

Technology and characterization of GaN-HEMT devices: high