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Tera-Pixel APS for CALICE. Progress Meeting 6 th September 2006. Main Activities. Meeting with Foundry B Tender for 0.18 micron fabrication Phone meeting with Foundry D [JC] Digital logic design & simulations [RT] New analog pixel circuits Meeting with Guilio, Mike, Marcel & Konstantin. - PowerPoint PPT Presentation
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Tera-Pixel APS for CALICE
Progress Meeting 6th September 2006
Main Activities
• Meeting with Foundry B• Tender for 0.18 micron fabrication• Phone meeting with Foundry D• [JC] Digital logic design & simulations• [RT] New analog pixel circuits• Meeting with Guilio, Mike, Marcel & Konstantin
This presentation
‘0’’1’
‘1’
DA
B C
Ф1
Ф2b
Ф2 Ф2
dmy dmy
fwd
fwd
bck
bck
Bidirectional SRAM Shift-Register Cell
Consolidated Hit Logic
Init
Phi2
Hit Detect + Mux
Addr[2:0]
DataValid
DataCode
TimeStamp
phi2 MaskShiftReg
Mode
Latch
Done
ReadEn
Fwd
RdEn#
WrEn#SRAM
For each reg…
phi1
Phi1
Hit Sequencingphi2
phi1
Init
Addr
Address 0 drives DataValid and DataCode to all 0s. Therefore (2^n)-1 sub-regions can be addressed.
0 1 2 3 4 5 6 0
DataValid
2 channels are hit
Phi2 pulse that reaches SRAM shift register
Timestamp 0x008E 0x008F
we1
we2we3
we3
Logic causes the next SRAM to also receive a write-enable signal. Not a problem: Would be overwritten with valid data or ignored in readout
hold
Readout Sequencingphi3
phi1
readInit
readEnables
Row 1
[3 hits]
Row 2
[0 hits]
Row 3
[1 hit]
12 3
First numbered readEnable is driven from outside to commence readout; all others derive from previous row =(n-1)
Note possible combinational delay when passing through empty rows (n=2)
4
Cell being read
Area Estimates
26 bits ~ 100um
19 r
egis
ters
~ 5
0um
Mas
k +
sam
ple
Mux
Log
ic +
Buf
feri
ng
SR
AM
con
trol
ler
Mask: 8.5um per 16 channels
Local data buffers for global readout
Mas
k +
sam
ple
Mas
k +
sam
ple
Sel
ect l
ogic
Bidir SR: 8.2um per 10 cells
SR
AM
con
trol
ler
~16.5u ~25.5u
5080um
Layout Example
64x64
64x64
64x64
64x64
10mm
10mm
Readout
Control
Pad & Power Ring
Pixels
Test Bump Pads Test Structures
36 pixels 36 pixels
1800um200um
1800um200um
4000um4000um
80 pixels
4000um
Readout + I/O buffers
2mm
x 4
mm
Logic Simulation
SRAM Readout
Verilog Stimulus
Row Control Logic
1st Bunch Crossing: 1 hit
2nd Bunch Crossing: 1 hit
3rd Bunch Crossing: 2 hit
Initialise for readout
Clear & Initialise Logic
Readout
Program Mask Register
Readout Data = 0101000011111111111100Readout Data = 1100100101111111111100Readout Data = 1000111011111111111101Readout Data = 0010011001111111111110
Mask = 111111000000111111111111111111111111
Hit1 = 000000000000001100000000000000000000
Hit2 = 000000010000000000000000011101000000
Hit3 = 100001000000000000000000000000010010
MuxAddr = 101 000 001 101 100 110
3rd
3rd
2nd
1st
Addr Hit Pattern Timestamp
(Masked hit)
1st Bunch Crossing: 1 hit
2nd Bunch Crossing: 1 hit
3rd Bunch Crossing: 2 hit
Initialise for readout
Clear & Initialise Logic
Readout
Program Mask Register 2us 36 registers @ approx 18 Mhz
0.5 us 20 registers @ approx 24 Mhz
148ns
148ns Mux address cycles 6 addresses @ 45 Mhz
148ns
50ns
170ns 4 registers @ approx 24 Mhz
Questions
• Number of sub-sets of pixels?– 6 or 7
• Number of pixels in a sub-set?– 6 or 7 or 8
Currently Implemented 36 pixels = 1800 um
Control logic + SRAM = 200 um
Dead Area = 10 %
(19 regs)
Question
• Assuming a row must be reset after a hit (real or noise)…– This reset is likely to occupy the next bunch
crossing, ie lasting 150ns, during which time the N pixels in this row will be ‘blind’ to a subsequent hit (real or noise)
– Is this acceptable?