Test setup for RAL structures - Cedric Mansuy

Test setup ready main board + chip carrier PCBs (2 types: transistors (1), HV

transistors, insulation, capacitances (2)) Setup with lab instruments (switching matrix, LCRmeter,

source-meters) and Labview Software for analyzing data (Matlab)

See presentations by Cedric in WG3 meetingshttps://indico.cern.ch/categoryDisplay.py?categId=3308

Wire bonding of dies not possible due to matrix-structure of the pads >> Au ball bonding with company in Switzerland (Hybrid SA)

10 carriers with chips mounted and Au ball bonded delivered 29/5/2012

Main board with chip carrier

Chip

10 chips mounted: 5.5 um epi without

deep p-well Next carriers

equipped with 12 um epi layer and without deep p-well

Connect 1-11 and 10-20 or 11-21 and 20-24

Chip carrier

0 0.5 1 1.5 2 2.5 3 3.50

50

100

150

200

NMOS HV NUM2

Gate=0Gate=1Gate=2Gate=3Gate=3.3

Vds [V]

Ids [

uA

]NMOS transistor (preliminary)

0 0.5 1 1.5 20

50

100

150

200

NMOS LV NUM2Gate=0Gate=0.5Gate=1Gate=1.5Gate=1.8

Vds [V]

Ids [

uA

]

Ids Vs Vds

Low voltage

High voltage

PMOS transistor (preliminary)

0 0.5 1 1.5 2 2.5 3 3.50

200

400

600

800

1000

1200

PMOS HV NUM1

Gate=0Gate=1VGate=2VGate=3VGate=3.3V

Vds [V]

Ids[u

A]

Ids Vs Vds

Isolation (preliminary)

Leakage current Vs voltage

Capacitance (preliminary)

Capacitance Vs voltage bias