TH EDA NTHU-CS VLSI/CAD LAB 1 A Probabilistic Approach to Logic Equivalence Checking Chun-Yao Wang ( 王俊堯 ) Dept. CS NTHU 2006. 01. 06

1

TH EDATH EDA

NTHU-CS VLSI/CAD LAB

A Probabilistic Approach to Logic Equivalence Checking

Chun-Yao Wang ( 王俊堯 )Dept. CS NTHU

2006. 01. 06

2 TH EDATH EDANTHU-CS VLSI/CAD LAB

Outline

• Introduction

• Previous Work

• Probabilistic Logic Equivalence Checking– Exact Approach– Approximate Approach

• Experimental Results

• Conclusions


Motivation

• Logic equivalence checking– Logic optimization, scan insertion, manual

modification

• Exhaustively simulation is infeasible for practical designs


Problem Formulation

• Given two netlists N_ori, N_opt

– N_ori is the original netlist

– N_opt is the netlist after area/timing optimization (restructuring)

• The problem is to formally verify the equivalence of N_ori and N_opt


Outline

• Introduction

• Previous Work

• Probabilistic Logic Equivalence Checking– Exact Approach– Approximation Approach


• Conclusions


Previous Work (1/3)

• Probabilistic based approach– Assume circuits only consist of AND/OR/NOT gates

– Probability formulae (independent signals)• Symbol represents the probability of signal one

a ba

b

a1 - a

b

a 1 - (1 - a) (1 - b) = a + b - a b


Previous Work (2/3)

• Assign the probability symbol to PIs

• Derive probability expressions

• Perform exponent suppression ( xm→ x ) on reconvergent gates

• Compare the output probabilities (unique)

• Problem: Representation complexity

ab

c

1-b

a × (1-b)

b × c

a × (1-b) + b × c – a × (1-b) × b × c= a × (1-b) + b × c – a × (b-b2) × c= a × (1-b) + b × c – a × (b-b) × c= a × (1-b) + b × c

E. J. McCluskey et al, "Probabilistic treatment of general combinational networks,"IEEE Trans. Computer, June 1975


Previous Work (3/3)

• Assign real numbers as input probabilities instead of symbols– Evaluate output probability (number) of circuits

• Arithmetic operationsArithmetic operations

– Problems:Problems:• Aliasing occurrenceAliasing occurrence

• Signal correlation Signal correlation

J. A. Abraham et al, " Probabilistic design verification ," ICCAD, 1991


Aliasing Problem

• Two different circuits have the same output probabilityTwo different circuits have the same output probability

• Example:Example:– NN11≡≡NN22,, but with the same output probability but with the same output probability

• Multiple runs increase the confidence levelMultiple runs increase the confidence level

1

6

1

2

1

3

1

6

1

21

2

1

3

N1N2

1

6


Signal Correlation Problem

• Numbers cannot be assigned immediatelyNumbers cannot be assigned immediately– Numbers should be assigned after exponent suppressionNumbers should be assigned after exponent suppression

• Example:Example:– Two inputs of Two inputs of G2G2 are correlated with are correlated with signal Bsignal B

– Without considering exponent suppression Without considering exponent suppression

– Considering exponent suppressionConsidering exponent suppression

1

2

1

3

1

61

18

1

6( ○ )

( × )

G1G2

A

B

1

181

6


Outline

• Introduction

• Previous Work

• Probabilistic Logic Equivalence Checking– Exact Approach

• Aliasing-Free Probability Assignments• Encoding Scheme and Alternative Operations• Dealing with Signal Correlation• Internal Tree-Structure Replacement

– Approximate Approach


• Conclusions


Aliasing-Free Probability Assignments

• An aliasing-free assignment– xxii= =

– aaii+1+1=(=(aaii-1)-1)22+1, +1, aa11>=3>=3 & & Z Z++, , ii=1~=1~nn-1-1

– Problem:Problem:• The assignments grow exponentially• n <= 24 is feasible

• Examples:– xx1 1 = , = , xx2 2 = , = , xx3 3 = , …, = , …, xx6 6 = , …= , …

1

3

Teslenko, M., Dubrova, E., and Tenhunen H., ""Computing a perfect input assignment for probabilistic verification"", EMT'2005, May 12-15

1

5

1

17

1

ia

1

4,294,967,297


Why Aliasing-Free

• A 3-input function has distinct functions– Assume xx1 1 = , xx2 2 = , x , x33 =

– The probability of each function is distributed from ~

32 82 2 256 1

3

1

5

1

17

X1 X2

X30 0 1 0 0 1 1 1

0

1 1

255

2

255

4

2558

255

16

255

32

255

64

255128

255

0

255

255

255


Encoding Scheme• Denominators are either aaii or the product of aaii

– , , , ,

• Suppose the weight of bit-i is aaii

– Multiplication replaces additionMultiplication replaces addition– Reduce memory usageReduce memory usage

• Examples:Examples:– xx1 1 = = == = =

– xx2 2 = = = = = =

– xx3 3 = = == = =

– xx1 1 × × xx2 2 × × xx3 3 = = × × = ( )× × = ( )

1

1

a

1

3

2

1

a

1

5

1

3

1

5

0001

00010001

0010

0001

0111

1

3

1

5

1

3 5

3

1

a

1

170001

01001

17

0001

11111111


Example – AND Gate

• Original formulation

• Bitwise-AND (∩) operation

1

3

1

5

1 1 1

3 5 15

0001

0001

1

3( ) =

0101

0011( )5

15 0101 0011 0001

0011 0011

( )1

15

0001

0010

1

5( ) =

0011

0011( )3

15


Shift-Add Operation

• When transforming two input probabilities to their equivalent probabilities– Denominators are either 3, 5, 17, …,

– Shift-add operations are used to obtain the numerator instead of multiplication operations

• Example:–

– Numerator 5 = 1 × 5 can be obtained by ( 0001 << 2 ) + 0001 = 0101 = 5

122 1i

0001

0001

1

3( ) =

0101

0011( )

5

15


Example – OR Gate

• Original formulation

• Bitwise-OR ( ) ∪ operation

1

51 1 1 1 21

5 17 5 17 85

1

17

0001

0010( ) =1

5 ( )

( ) =0001

0100

1

17

( )10001

0110

17

85

( )00101

0110

5

85

10001 00101 10101

0110 0110

21

85


Dealing with Signal CorrelationDealing with Signal Correlation

• When transforming two input probabilities to their equivalent probabilities– The lowest common multiple suppresses the

correlation of two input probabilities if the denominators have the same factor

1

3

1

5

G1

G3

( ) = ( )0001

0011

1

15

010001

0111

17

255

1

17( ) = ( )10101

0110

21

85

111111

0111

63

255

011

010

1 0111

001 111111 010001 ( )17

255

G2

A

B

C


Internal Tree-Structure Replacement

• Example:– Verify if N1≡ N2

– Only two input assignments and are used

1

3

G1

G2

B

C

A

C

N1 N2

1

5

1

3

G1BA

1

5 G2

1

15

1

15

7

15

1

5

1

3

1

3

1

5

1

15

≡

1

3

1

5


Outline

• Introduction

• Previous Work

• Probabilistic Logic Equivalence Checking– Exact Approach

• Aliasing-Free Probability Assignments• Encoding Scheme and Alternative Operations• Dealing with Signal Correlation• Internal Tree-Structure Replacement

– Approximate Approach


• Conclusions


Approximation Structure• Connect Random Probability Generator (RPG) to DUV• Aliasing-free assignments are assigned to RPG’s PIs• RPG produces every possible function• |PO| in RPG = |PI| in DUV• Verify the equivalence of S1 and S2 Verify the

equivalence of L1 and L2

RPG

︰aliasing-free assignments

:S1

RPG


︰ S2

L1 L2


Problem Formulation

• Given two large netlists S1, S2 (# of required input assignments > 24)

• The problem is to verify the equivalence of S1 and S2 with aliasing rate (ε)

• ε pr(S1S2 ∩ L1L2)


Analysis (1/3)

• Assume r (resource) input assignments are available, and S1, S2 (DUVs) have n PIs. What is the aliasing rate ε in using Approximation Structure to verify the equivalence of S1 and S2?

RPG

︰aliasing-free Assignments

:S1

RPG


︰ S2

L1 L2

rn r

n


Analysis (2/3)

• r=2, n=3, connect 2/15, 7/15, 9/15 to the inputs of S1

• Uniformly hash 16 S-functions to one L-function

• ε

L_0 S_0~S_15

L_1 S_16~S_31

L_2 S_32~S_47

L_3 S_48~S_63

L_4 S_64~S_79

L_5 S_80~S_95

L_6 S_96~S_111

L_7 S_112~S_127

L_8 S_128~S_143

L_9 S_144~S_159

L_10 S_160~S_175

L_11 S_176~S_191

L_12 S_192~S_207

L_13 S_208~S_223

L_14 S_224~S_239

L_15 S_240~S_255

1/3 1/5

RPG

S1

L12/15

7/15

9/15

0586.065536

3840

256256

216 16

256

2

C


• ε pr(S1 ≠ S2 ∩ L1 = L2)

= pr(L1 = L2) - pr(S1 = S2) = -

• Assume n>24 ( ), εis simply related to r– r=8, ε 10-77

– r=9, ε 10-154

– r=10, ε 10-308

– r=11, ε 10-616

– r=12, ε 10-1233

AnalysisAnalysis (3/3)(3/3)

2

10

2n

L1=L2S1=S2

2

1

2n2

1

2r


Outline

• Introduction

• Previous Work



• Conclusions


Experimental Results – exact approach

Circuits |PI| |PO| Max ai / Max TFI|PI|Tree

(Y/N)Time (s)

Ours / BDD

Mem. (MB)

Ours / BDD

i9 88 63 13 / 13 N 0.76 / 0.66 6.66 / 6.45

x4 94 71 15 / 15 Y 0.22 / 0.22 5.48 / 5.57

i3 132 6 7 / 32 Y 0.05 / 0.05 3.41 / 4.80

i5 133 66 19 / 19 Y 0.17 / 0.23 5.62 / 5.30

i8 133 81 17 / 17 Y 1.71 / 1.44 11.00 / 10.00

apex6 135 99 22 / 24 Y 0.51 / 0.42 9.50 / 6.23

x3 135 99 23 / 24 Y 1.41 / 0.45 15.00 / 6.52

i6 138 67 5 / 5 N 0.21 / 0.32 5.87 / 5.94

frg2 143 139 23 / 25 Y 2.35 / 0.87 15.00 / 7.63

i7 199 67 6 / 6 N 0.25 / 0.46 6.25 / 6.33

des 256 245 18 / 19 Y 5.23 / 4.42 15.00 / 15.00


Experimental Results – approximate approach (r=10, ε, ε 10 10-308-308)

46

21

66

17

10

25

32

9

32

6

RPG |PO|

11.003.71194108207C7552

18.0029.41323232C6288

8.340.2567123178C5315

9.38 4.69502250C3540

8.521.15122140233C2670

6.64 1.37332533C1908

6.96 2.21413241C1355

5.16 0.26452660C880

6.27 1.71413241C499

7.39 0.3236736 C432

Mem. (MB)Time (s)n=Max TFI|PI||PO||PI|Circuits


Outline

• Introduction

• Previous Work



• Conclusions


Conclusions

• An aliasing-free assignment procedure is proposed

• More efficient operations, such as bitwise-AND, bitwise-OR, and shift-add operations are used

• The aliasing-free assignment and bitwise operations deal with the signal correlation problem well

• Internal tree-structure replacement is used to reduce the number of required input assignments

• An approximate approach with configurable aliasing rate is proposed for large circuits


AppendixAppendix

• P.31~P.37


Calculate Signal Probability

• Transform two input probabilities to their equivalent probability– The denominator is the lowest common multiple

of the original denominators

• The two new numerators conduct bitwise-AND/ bitwise-OR operation to obtain the numerator of output probability if it is an AND/OR gates


Why Work – AND Gate

• The operation 0101∩0011 is analogous to perform intersection on minterm sets 0001

0001

1

3( ) =

0101

0011( )

5

15 0101 0011 0001

0011 0011

( )1

15

0001

0010

1

5( ) =

0011

0011( )

3

15

1

3

0 0

0 1

1 0

1 1

X2 X1 prob. of minterm

1

5 ×

×

×

×

1

5

(1- )1

5

1

3

(1- )1

3(1- )1

5

=

=

=

=

1

15

2

15

4

15

8

15 0

1

0

1

0

0

1

1

∩ =

0

0

0

1

bitwise-AND

1

3(1- )


Why Work – OR Gate

• The operation 10001∪00101 is analogous to perform union on minterm sets

0 0

0 1

1 0

1 1

X2 X1 prob. of minterm

×

×

×

×

=

=

=

=

1

85

4

85

16

85

64

850

1

0

1

0

0

1

1

=

0

1

1

1

0001

0010( ) =

1

5 ( )

( ) =0001

0100

1

17

( )10001

0110

17

85

( )00101

0110

5

85

10001 00101 10101

0110 0110

21

85

1

17

1

5

(1- )1

5(1- )1

17

∪

bitwise-OR

(1- )1

17

(1- )1

5

1

51

17


Internal Tree-Structure Replacement (1/2)

• Only consider two Boolean networks for verification

– Internal tree-structure replacement can be used to reduce the number of required assignments

– The output probability is changed, but it does not affect the judgement on the equivalence checking


L1=L2

Analysis Analysis (2/3)(2/3)

• pr(S1 = S2) =

• pr(L1 = L2) =

• If S1=S2, then L1=L2– (1) pr(S1 = S2 ∩ L1 ≠ L2) = 0

• pr(S1 = S2 ∩ L1 = L2) + pr(S1 = S2 ∩ L1 ≠ L2) = pr(S1 = S2) = – (2) pr(S1 = S2 ∩ L1 = L2) =

• (3) ε pr(S1 ≠ S2 ∩ L1 = L2) = pr(L1 = L2) - pr(S1 = S2) = -

• (4) pr(S1 ≠ S2 ∩ L1 ≠ L2) = 1 – pr(L1 = L2) = 1 -• (1) + (2) + (3) + (4) = 1

2

1

2n

S1=S2

2

1

2r

2

1

2n

2

1

2n2

1

2r

2

1

2r

L1=L2S1=S2

2

1

2n


Experimental Setup• Benchmarks

– n<=24 exact approach MCNC benchmarks in BLIF format – n>24 approximate approach ISCAS-85 benchmarks in BLIF format

• Environment– SIS environment– Sun Blade 2500 workstation

• Experimental flow– Map benchmarks to the SIS library (22-1.genlib), decompose the ne

tworks to AND/OR/NOT gates

– Verify the equivalence between original Netlist and Netlist after area optimization (map –m0)

– Separate multiple-output network into many single-output subnetworks

– BDD based approach - ntbdd_verify_network( N1, N2, DFS_ORDER, ONE_AT_A_TIME )

Documents

TH EDA NTHU-CS VLSI/CAD LAB 1 A Probabilistic Approach to Logic Equivalence Checking Chun-Yao Wang ( 王俊堯 ) Dept. CS NTHU 2006. 01. 06