The DatasheetArchive - Datasheet Search Engine › coco › mc6847_2.pdf · MCW7/MCW7Y VIDEO DISPLAY GENERATOR (VDG) The video display generator (VDG) provides a means of interfacing

MCW7/MCW7Y VIDEO DISPLAY GENERATOR (VDG)

The video display generator (VDG) provides a means of interfacing

the M~OO microprocessor family (or similar products) to a standard col-

or or black and white NTSC television receiver. Applications of the VDG

include video games, process control displays, home computers,

education, communications, and graphics applications.

The VDG reads data from memory and produces a video signal which

will allow the generation of alphanumeric or graphic displays. The

generated video signal may be modulated to either channel 3 or 4 by

using the compatible MC1372 (TV chroma and video modulator). This

modulated signal is suitable for reception by a standard unmodified

television receiver. A typical TV game is shown in Figure 1.

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●

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Compatible with the M6800 Family, the M68000 Family, and Other

Microprocessor Families

Generates Four Different Alphanumeric Display Modes, Two Semi- ,$

graphic Modes, and Eight Graphic Display Modes ~.!..~t..~.,,.>.:.~

The Alphanumeric Modes Display 32 Characters Per Line by 16 Lin~$~’’:t’\t$.

Using Either the Internal ROM or an External Character Genera@r’*$~ek,..~i.$*$:k...*.

Alphanumeric and Semigraphic Modes May Be Mixed onq$~aSr-

acter-by-Character Basis .:,,~t>}:..,

Alphanumeric Modes Support Selectable lnverse,,~~~ a C“haracter-

by-Character Basis<:;$.>

~~$:> .’.~,,.h:.’{t:t,>i.:$f’~i:

Internal ROM May Be Mask Programmed w.~,~~$~ustom Pattern, “’.’’><)~~.’~~.\

.$\:.>,+,,,.>, ,:*Full Graphic Modes Offer 64x M, 128,~~;$~:%x 96, 128x 192, or

256 x 192 Densities,,..,,.,.$\>,,:..+ ‘ ‘:.,,, ,,:J: +?$* *~t\

:.$, “ :$.Full Graphic Modes Use One o~~w:~s#<Color Sets or One of Two

2-Color Sets .\K. ,:.~,+,,:ts~;i.,:.$1&

*f

Compatible with the M~&$~t@#d MC1373 Modulators Via Y, R-Y

(4A), and B-Y (@B) ln&fa6#.Xjlkr:$?’#,l\,

MC6847Non=lnterlace

MC6847YInterlace

/

S SUFFIXERDIP PACKAGE

CASE 73

PIN ASSIGNMENT

Vss[ 10

DD6[ 2 39 Css

DDO[ 3 38 m

DD1[ 4 37 7s

DD2[ 5 36 w

DD3 [ 6 35 ~/G

DD4[ 7 34 K/s

DD5[ 8 33 CLK

CHB[ 9 32 INV

$B [ 10 31 ~T/ EXT

+A [ 11 30 GMO

Kc 12 29 GM1

DA5[ 13 28 Y

DA6 [ 14 27 GM2

DA7[ 15 26 DA4

DA8 [ 16 25 DA3

Vcc [ 17 24 DA2

DA9[ la 23 DAI

DA1O[ 19 22 DAO

DA1l[ 20 21 DA12

@MOTOROLA INC., 19W DS%23-RI

Game _Paddles

EM C6809E

MPU ~

DO-D7

AO-A15

AO-AI 5

DO-D7

M C6646ROM

1/0 Timer

Cs

FIGURE 1 – BLOCK DIAGRAM OF A TV GAME USING THE VDG AND THE MC6BWE MPU

4X ColorBurst Freq14,38 MHz

3J*SO-S2

ESynchronous CLK CLK

M C6~3 AddressMultiplexer DAO + - DAO

5——

ZO-Z7 WE CAS RAS R *—. m ~B

16 8il I M C6W7 M &

\8’ T

RAMA ,,0,, I Ikl

ELECTRICAL SP@kf&TIONSABSOLUTE M~j~u~ RATINGS. /,,,.,,..,,.

,f}~$+, fiaracteristics,,,/,,~ Symbol Value Unit

supply .y$%@e+ ‘ Vcc –0.3 to +7.0 v

Input ~,olt~&”Any Pin Vin –0.3 to +7.0 v

TA Oto +70 ‘c

Tstg –65to +150 ‘c

$

THERMAL CHARACTERISTICSVcc)

Characteristics Symbol Value Unit

Thermal Resistance 1

This device contains circuitry to protect the tn-puts against damage due to high static voltagesor electric fields; however, it is advised that nor-mal precautions be taken to avoid application ofany voltage higher than maximum rated voltagesto this high impedance circuit. Reliability ofoperation is enhanced if unused inputs are tied toan appropriate logic voltage (e.g., either VSS or

I CeramicPlastic I OJA

I

50100 I

QClwI

@MOTOROLA Semiconductor Products Inc.

2

.—

.-

DC (STATIC) CHARACTERISTICS (VCC= 5.o V i 5%, VSS =0.0 V, TA=OOC to 70°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

Input High Voltage

CLK vlH VSS+2,4 — Vcc vOther Inputs VSS+2.O — Vcc

Input Low VoltageCLK vlL VSS– O.3 – Vss+O.6 vOther Inputs VSS– O.3 – Vss+0,8 ~t

Input Leakage Current, Force 5.25 V on Pin Under Test,s,.’},,.

%$;,VCC=5.5 V CLK, GMO-GM2, INV, ~T/EXT, ~, vss,

.:**,Iin — — 2.5 ; : $+, ‘

DDO-DD7, ~/S, ~/G .$},, ::*J.,..!,.:,:*,& ~~~’

Three-State (Off State) Input Current DAO-DA12.,,i..,,., \ ,~..,,,

Force 2.4 V and 0.4 V on Pin Under TestIOL — — ,:+>*+@$+’:* PA.<>$:,,,*..,.,

Output High Voltage (CLoad=30 pF, lLoad= – 100pA TP, TS, R vOH 2.4,Jk.$:.,:— .*,?;:,,,.,;)? v

Output High voltage (cLoad= 55 PF, lLoad= – l~pA) DAO-DA12 vOH 2.4i; , $., _— !.:}+,<,.’;., v

Output Low vOltage (CL~ad= 30 pF, lLoad = 1.6 mA) RP, HS, FS vOL — ~:,{.y~\,\, ..?., “VSS+0,4 v

Output Low voitage (c Load= 55 pf, lLoad = 1.6 mA) DAO-DA12 vOL :tj,,jl. <.!:}]— *. .x.<,, .4VSS+O.4 v

Output High Current (Sourcing) All Outputs (Except ~)~,.+$* *

(V0H=2.4V)IOH – 100 .*$‘~$.~:,~$+

4A, 4B, Y, and CHB)— PA

.!~ .;*... ...Output Low Current (Sinking) All Outputs (Except

.*,,,,,,.....t~>.

(vOL=0.4v) @A, @B, Y, and CHB)IOL *~*Q ‘“$: – — mA

,:). ;Y

Input Capacitance (Vin=O, TA=250C, f= 1.0 MHz) All Inputs Cin*‘ l?% ‘- —,,,t\,*’:*i; if, 7.5 pF

Internal Power Dissipation (Measured at TA= O to 70°C) PiNT$ &., $$– — 600 mW

Chroma @AVoltage (Figure 3) v l*c,l,$$ m 1.8 2.0 2.2

(CLoad=20 Pf, RLoad= 100 kQ) ;?,VR %f:. 1.34 1.5 1.66 v(Note 1) ,,,”;“’~~QL 0,8 1.0 1.2

Chroma @B Voltage (Figure 3),,(* .>,+< S. vjH 1,8 2.0 2.2

(CLoad =20 PF, RLoad= 100 kQ),$+,,, ~$‘J;., vR 1.34 1.5 1.66.:tT\., -Q,*

(Note 1)v.x,:;:,:j.t:,:>:$,~

.,+* vOL 0.80 1.0 1.2<.:>+.,,. vBurst 1.07 1.25 1.43

Luminance Y Voltage (Figure 3) ,.).if(CLoad =20 PF, RLoad= 100 kQ) *.,.\.\i.i

(Voltage Svnchronlzation) $.)% ‘:*‘I:’.* Vs 0.9 1.0 1.1:JLS,

(Voltage Blank)~,~+;~y>.~,,,,,>,>t*

vB[ank~’-,.:.’,..\., J**. 0.63 0.77 0.9(Voltage Black) ,} v

,,$’$.;:$&$.,*$’ vBlack 0.58 0.72 0.83(Voltage White Low) ‘~.::i~, .$\.,,5},,.. .\\.,1.,..*. vWL 0.51 0.65 0.75(Voltage White Medium)

‘..~..{:~>~>:$*,,.>,!* :,,~>.~,,.:.J$, vwM$*+‘“~33

0.40 O.M 0.65(Voltage White High) (Note 11 %><, *<. vWH 0,27 0.42 0.53

Chroma Bias Voltage (cLoad = 20 PF, R$Jaj =:W kQ) vR 0.27 vcc 0.3 Vcc 0.33 Vcc v,,-.Resistor YOof VSS Tracking (Analog,@~fp~~&Linearity Error) RT — 1,0 3.0 0/0..,, ., I,,.\ ‘..$


3

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in ‘C can be obtained from:

TJ=TA+(PD-OJA)

Where:

(1)

TA= Ambient Temperature, ‘C

OJA= Package Thermal Resistance, Junction-to-Ambient, OC/W .!,.

PD=PINT+PpORT

A),,),,l.~:~:.*L~\,\.,,.l.,.,$..,t,.,~ ,1...

PINT= ICC x VCC, Watts – Chip Internal Power~*:~\,:::’~”,<$,+

){t t,$.~t.+

PpORT= Port Power Dissipation, Watts – User Determined\ “:tt+.:?.,:t:’i’..:~,,i,, ‘~ *,

For most applications PpORT< PINT and can be neglected. PpORT may become significant if the deviq~tw~,nflgured to

*)?-~+‘,,,.:,“ :.,’s

dtive Darlington bases or sink LED loads.,3$* ..:,:?*~.; ,:,,+?F

An approximate relationship between PD and TJ (if PpORT is neglected) is:

.;\a~,..:.:.....\yt3..,,,~,~t>,~:?i~,,,<,,.\

PD=K+(TJ+2730C).’\t,,> ...

~.:~+,,$.:, (2)

Solving equations 1 and 2 for K gives:

‘?$, ‘+’‘:4:j:\:.t.:Y..~\

K= PD*(TA+2730c) +oJAoPD2‘J.&,“,x.’,%1,?,,,“!’.1>>

-,.~.. -~h~;:~ (3)

Where K is a constant pertaining to the particular part. K can be determined from equati~o~~$y:, measuring PD (at equilibrium)

fora known TA. Using this value of K the values of PD and TJ can be obtained by solving@~~~ns (1) and (2) iteratively for any

value of TA, .\.,$).,~:~,.,’i~;’<,‘.

+~j$,<..ki:+<:.s

CHAIN


4

— --—.————-

C (DYNAMIC) CHARACTERISTICS (VCC= 5.0 V + 5Y0, TA= O°C to 70”C) (Load Circuit

Characteristic

CLK (Frequency (3.579W5 Color Burst Frequency)

CLK Duty Cycle

Clock Rise Time

Clock Fall Time

)f Figur

Symbol

3,579535f

CLKdc 45

tcLKr ——tcLKf

‘WCLK 120Clock Pulse Width

Horizontal Display Address Delay from Counter DAO-DA3

DA4

—[HDAD

HDA4[

tHDAH

—

Horizontal Display Address Hold Time o0HDA4t

tDDS

tDDH

tDHSf

Display Data Setup Time CSS, INV, ~/S, lNT/EXT, DDO-DD7

Display Data Hold Time CSS, INV, K/s, m/EXT, DDO-DD7

Horizontal Sync (~) Delay Fall

70

140—

Rise tDHsr

tDRpfRow Preset (~) Delay Fall

Rise

Vertical Display Address Delay from Counter DA5-DA12

Vertical Display Address Hold Time

Field Sync (~) Delay Fa~

——

*R*;Memory Select Low to Display Address High-Impedance

‘i,:,.<:’,:~ *->,,>,.>>,\i

Memorv Select High to Displav Address Valid <*:*,\+,.,.

,:DFsr

tDMsT

tDMsv

—

80 ns 9

400 ns 9

100

100100

100 ns 12

100

100

100

100

100 ns 12

lm ns 12

——

Chroma Rise and Fall Times-!<.,,

i::!

(OA Rise Time) trC$Atr@A

tfC~A

tf@A

trC@B

tr@BtfC@B

tf~ B

——(oA Fall Time)

(+B Rise Time)

—

(+B Fall Time)———

tcBr

tCBf

– 50 140 I ns I 11tyAtyB

try

tfy

tHr

tHf

tHBr

tHBf

tFp

– 50

Luminance Rise Time $f,, .::?!I?:,*... ...>....,.Luminance Fall Time !,:’y ‘~--,.-“+1,

—

s100 ns 12

100 ns 12

100 ns 12

100 ns 12

100 ns 12

2,4 KS 12

5.1 #s 12

8.3 US 12

—... ,.,Horizontal Sync Rise Time on.+&:Q,@~*? —

——

Horizontal Sync Fall Timeon’%:Q~fput

Horizontal Blanking Ris@f~,@e on Y Output, .,.,!. ..

Horizontal Blanking,@F&~T& on Y Output

Front Porch Du~r~@h$:ne (7x 1/f)

Back Porch Dur&*~~ime (l7.5x I/f)

—

1.8

4.5

7.5

tBp

tLB

tRB

tcB

7.5

2,7 *

FIGURE 3 – TEST LOADS

——AO-A12, %, RP, HS

MMD6150 I 4’75 v4A, 40, Y, CH8

Test

m

or Equlv. 2.50 k~

Point

24 k 30 pF MM D7~

or Equiv,

v =

‘est‘“’nt7 ,m k

I=

—


5

FIGURE 4 – CLOCK AND LONG CYCLE HORIZONTAL ACCESS TIMING

tcLKf+ +

1.2.

3.

4.

5.

The VDG may power-up using either the rising or falling edge of the clock (dotted Iine):A:$$, W]?

Transitions of DA4-DA12 occur outside the display area. DAO-DA3 access the 16 bytes G$,tQ&?dlsplayed during each scan line in the dis-

play area. ,~~,,;,i,:..,$’..:$... ,.,,~+:...,

Long cycle timing applies to CGI, RGI, RG2, and RG3 modes (see Table 3). ~/G ;S ~h~~$S, lNT/EXT, and INV input levels do not affect., _

the VDG in long cycle modes.....~.::$t,{?h.~

Usable RAM access time for the long cycle may be calculated using the f~$bwi’~,,equation:

tRACL=8-1/fmax –tHDADmax– tDDSmin–tCLKr ‘P’’’~%ti

If address and data buffers are used, the access time must be adjust~@8~or8ngly.

All timing is measured to and from a low voltage of 0.8 volts and +$,~~~:,~ltage of 2.0 volts unless otherwise specified.

:*:):{

.>\ *.$.<:~’,i,~ih.~.I%ke,

NOTES: ~ .,:, $+,:++’?3:..::1. The @~,~@~y power-up using either the rising or falling edge of the clock as shown in Figure 4,

2. Tr~g~~o~$ of DA5-DA12 occur outside the display area. DAO-DA4 access the 32 bytes of data displayed during each scan line in the dis-

.~a$,g{e~.,&~$,S~rt cycle timing applies to t~e four alphanumeric modes, two semigraphic modes, and to the CG2, CG3, CG6, RG6 modes (see Table 3),

~$ *@”the four graphic modes, A/G is high and the~/S, ~/EXT, and INV input levels do not affect the VDG.~{{ Usable RAM access time for the short cycle may be calculated using the following equation:

“ tRACS=4*l/fma~– tHDA4Dmax– tDDSmin–tCLKr

If address and data buffers are used, the access time must be adjusted accordingly,

5. Ail timing is measured to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless othewise specified.


6

—

—.

—.

---— .

} ~ J

FIGURE 6 – HORIZONTAL ADDRESS AND VALID DATA SETUP AND HOLD TIMING(Rming Relationships Shown From Beginning of Line)

DAO-DA3 I Valld Address

~alid Data

CSS, INV, ~/S, lNT/~DDO-DD7

HORIZONTALSYNCHRON1ZATIONTIMING

=~ -

RT4

DA5-DA12.

(,$,.*I. f),

~ tVDAH ~*$j\

NOTES ,.*F’tk\::, i.,s,t:,:t~.’

1. All tlm!rlg Is&$- [o arid from a low voltage of 0,8 volts and a h]gh voltage of 2.0 VOIIS unless otherwise spec(fled.

2 HS puls~t~~d:~~y be determined by tWHS= 16.5.1 /f-tDHSF+tDHSr.

3 HS to RP$~;@& determined by tHSRp=3.5.1 /f-tDHSr+tDRpf,4 RP pulse W@th mav be determined bv t~Rp=3.5.1 /f–tORpf+tORpr,

5. DA5 OA12 WIII change during the lnact[ve portion of the dlsplav.

6. tpHS= 227 5.1/f

7 100 T=fif

NOTES:

FIGURE 8 – FIELD SYNC (=) TIMING

mNote 1

MAO-MA12


8

—

FIGURE 10 – VIDEO AND CHROMINANCE OUTPUT WAVEFORM RELATIONSHIPS

TFp

BlankBlack

WL

WMWH

End ofHorizontal ~lG*=S

IllSync AI GsC~SIll I

+tHcD

+F

Note 1 IItcB

VIHZIG+ EIG. CSS IVR

IVB”r~t ~lG*

VOL ACR I

I(Burst is removed

for IAIGOCSSOGMO)

I Magenta OrangeVIH AjG+K/G.~VRVOL ~fG*=S


9

‘svnc

vBl~”k

vB[~~k

VWL

vw~

vw~

FIGURE 12 – TIMING DIAGRAMSVIDEO RISE AND FALL TIMES (Illustrates Beginning of One Horizontal Line)

*tHBNK+


10

4+

—.

—.

FIGURE 13 – DISPLAY AREA TIMING

Vertical Blankinq 13 H Lines

—

Top Border 25 H Lines

Active Display Area 192 H Lines

. . . . . . .

4. 2W Dots ~...1.*. ~. DISPLAY AREA

E (49,152 dots, all under VDGN

control in all modes. Each

Tone of up to 8 colors when on

depend, ng on mode. )

“One on each non-interlaced line; for Interlace, the lines of the odd

4

field are copied into the even field thus doubllng the number of dls

played dots

@M070ROLA Semiconductor Products Inc.

11

VIDEO DISPLAY GENERATOR DESCRIPTION

The MC6W7/MC6W7Y video display generators provide a

simple interface for display of digital information on a color

monitor or standard color/black and white television

receiver.Television transmissions in North and South America and

Japan conform to the National Television System Commit-

tee (NTSC) standards. This system is based on a field repeti-

tion rate of 60 fields per second. There are 525 interlaced

lines per frame or one-half this number per field.

The MCW7 scans one field of 262 lines 60 times per sec-

ond. The MC6B47 non-interlace VDG is recommended foruse in systems (i.e., TV games and personal computers)

where absolute NTSC compatibility is not required. If NTSC

compatibility is required, perhaps for caption overlays on

broad-case signals, then the MC6B47Y interlace VDG

recommended,

NOTE

A system with the MC6W7 VDG and the MC1372

video modulator forms a transmitter, transmitting at

61.2 MHz (channel 3) or67.25 MHz (channel 4) depen-

ding on component values chosen. This being a Class I

TV device, care must be taken to meet FCC re-

quirements Part 15, Subpart H, However, if the com-

posite video output from the MC1372 were to drive the

television directly, Section 15,7 of the FCC specifica-

tion must be adhered to.

is

SIGNAL DESCRIPTION .\,y’,$. +$,,,{

DISPLAY ADDRESS OUTPUT LINES ( DAO-DA12) ,,+$~,k,’x”%

Thirteen address lines are used by the VDG tv@$*,~~+hedisplay memory as shown in Figures 4-7. Th~+$~t~~g ad-

dress of the display memory is located at th~~~~~?eft cor-

ner of the display screen. As the televisioni~.~w from theleft to right and top to bottom, the,,~~~w,]$crements theRAM display address. The timing foF. thQ’%VCeSSeS Startin9

change during the active display area. A4 changes during the

active display area in the alphanumerics, semigraphics, CG2,

CG3, CG6, and RG6 modes. A5-A12 do not toggle within the

active display area but instead, ripple through the address

during border and blanking time.

DATA INPUTS (DDO-DD7)

Eight TTL compatible data lines are used to inR,u*&ata,$r~.:FAQ*~:*+

from RAM to be processed by the VDG. The dat~+is,~>~~~n-

terpreted and transformed into luminance (Y1 ~~&~roma

outputs (4A and @B).~)?\,>,,.mt:.:*:,

\t::!>t>t.$!?~,“+.?~:. .~,’.,?*.... ~ ,,,,...

POWER INPUTS – VCC requires ~;~,$~d$&+ 5% VSS

requires zero volts and is normally grW,R@~.$~e tolerance and

current requirements of the VDG ~,~ $~ecified in the Elec-‘\$\.,.

trical Characteristics. :$,.[:,,G~?i....Jt}x\..::~.#.\,

VIDEO OUTPUTS (oA,,#&jt8% CHB) – These four analog

outputs are used to tra$?$~[#@inance and color information;

to a standard NTSC+*{~$.Nlevision receiver, either via the

MC1372 RF mod,#jtoF%r’via drivers directly into Y, +A, ~B

television vide~~~,~~~~ (see Figures 10, 11, and 12).,,~.:,*,!,,;.,, “,;s::,t,,,<.J, ,

Lumin4~~:(,$~ – This six level analog output containscompo~~~jgync, blanking and four levels of video luminance.

‘.,:,.,,

$~~$- This three level analog output is used in combina-

#f&~~iwfih @B and Y outputs to specify one of eight colors.*:,,‘>,s$i~)~ct‘>.,,

‘~~~~y @B – This four level output is used in combination with‘~re.‘~+i +A and Y outputs to specify one of eight colors. Additional-<,.:>, Iy, one analog level is used to specify the time of the color

burst reference signal.

Chroma Bias (CHB) – This pin is an analog output and

provides a DC reference corresponding to the quiescent

value of @A and 4B. CHB is used to guarantee good thermal

tracking and minimize the variation between the MC1372 and

MC6B47. This pin, when pulled low, resets certain registers

within the chip. In a user’s system, this pin should not nor-

mallv be used as an in~ut. It is used mainlv to enhance test

capabilities within the factory

.+:).::~i.’.+<F,,\‘,? \$ *,+,,*5 ~ FIGURE 15 – COLOR COMPOSITE VIDEO TO COLOR MONITOR

... A

360 560

Adjust for

4 dc Output14

12 4.3 v=0.4 mA pp Typ 2N4403

MC1372 I I 4

d750 ac Output

t3.3 k

=

3.9 k*

1

Ratio: Color to Video Trim

/ 2N4401

*

*3.9 kQ is M C1372 effective load,

pin 12 voltage doesn’t move and is virtual ground.


12

..

-—- .

SYNCHRONIZING INPUTS (M=, CLK)

THREE-STATE CONTROL – (MS) is a TTL compatible

input which, when low, forces the VDG address lines into a

high-impedance state, as shown in Figure 9. This may be

done to allow other devices (such as an MPU) to address the

display memory (RAM).

CLOCK (CLK) – The VDG clock input (CLK) requires a

3.579W5 MHz (standard color burst) TV crystal frequency

square wave. The duty cycle of this clock must be between

45 and 55~o since it controls the width of alternate dots on

the television screen. The MC1372 RF modulator may be

used to supply the 3.579545 MHz clock and has provisions

for a duty cycle adjustment. The VDG will power-up using

either the rising or falling edge of the clock. The dotted line

on the CLK signal in Figure 4 indicates this characteristic of

latching in data on either clock edge.

SYNCHRONIZING OUTPUTS (=, ~S, =P)

Three TTL compatible outputs provide circuits, exterior to

the VDG, with timing references to the following internal

VDG states:

FIELD SYNC (=) – The high-to-low transition of the =

output coincides with the end of active display area (seeFigure 8). During this time interval, an MPU may have total

access to the display RAM without causing undesired flicker

on the screen. The low-to-high transition of ~S coincides

with the trailing edge of the vertical synchronization pulse.

HORIZONTAL SYNC (~) – The ~ pulse coincides

with the horizontal synchronization pulse furnished to the

television receiver by the VDG (see Figure 7), The high-to-

Iow transition of the ~ output coincides with the leading

edge of the horizontal synchronization pulse and the low-to-

high transition coincides with the trailing edge.

ROW PRESET (~P) – If desired, an external charh~ter,,$\*:,,,*>:<>generator ROM may be used with the VDG. HowevS{,’WW-

ternal four bit counter must be added to supp~~’’&~%ad-

dresses. The counter is clocked by the ~:,%,w$%nd is

cleared by the ~P signal. ~P pulses occur in:~],~s{~’%anumeric

and semigraphics modes; no pulses ar:~Qtit@? in the full

graphic modes. ~ occurs after t~.@yt~@~S>valid 12 lines.

Therefore, use an ~ clocked prelo~iab?~ ?ounter such as a

74 LS161 as shown in Figures 7, j~, dN#’23.‘,!~~,t$,..‘:,;}\

MODE CONTROL LINE:~i~iyT(X/G, K/s, FT/ExT,GMO, GM1, GM2, CSSc.i~:~,,~

Eight TTL compak~#~$j<&uts are used to control theoperating mode of. the*~PG. ~/S ~/ EXT, CSS, and INV

may be change~$~~}$$.ha racter-by-character basis. The CS Spin is used t~.a$~.between two possible alphanumeric col-

ors when tb~~YD.@ is in the alphanumeric mode and between

two cole$$~ts$d~en the VDG is in the Semigraphics 6 or fullgrap~k mti~s. Table 1 illustrates the various modes that can

be:~bt~~ned using the mode control lines. There are two dif-

~?@R{ tvpes of memory access concerning these modes,

$$>bg~?bre a short and a long access cycle, which differ by a

FiGuRE 16 – EXTERNAL cHARA$~,R G?NERATOR Row couNTER FoR Mcw7~.~t},,*,.,‘s. ,$.

1314+1,16

2m

GND%

Cp f8

Qo QI Q2—

Q3

Row Address(Zero Through Eleven)

— m MOrOROLA Semiconductor Products Inc.

TABLE 1 – MODE CONTROL LINES (INPUTS)

fi/G Af s ml EXT INV GM2 GM1 GMO Alpha/Graphic Mode Select # of Colors

o 0 0 0 x x x Internal Alphanumerics

o 0 0 1 x x x Internal Alphanumerics Inverted

o 0 1 0 x x x External Alphanumerics2

0 0 1 1 x x x External Alphanumerics Inverted

o 1 0 x x x x Semigraphics 4 (SG4) 8

0 1 1 x x x x Semigraphics 6 (SG6) 8

1 x x x o 0 0 UXM Color Graph[cs One (CGI) 4

1 x x x o 0 1 128x64 Resolution Graphics One (RG1) 2

1 x x x o 1 0 128x 64 Color Graphics Two (CG2)

1 x x x o 1 14 <~;

128 x 96 Resolution Graphics Two (RG2)

1 x@y,

x x 1 0 0 128x 96 Color Graphics Three (cG3)

1 x,m,J&\i”,,,>

x x 1 0 1 128x 192 Resolution Graphics Three (RG3) ~$?’‘**Y

1 x,$,,..g’$~f

x x 1 1 0 128x 192 Color Graphics Six (CG6) , ‘it,,,! @

1 x.,.::.i:

x x 1 1 1 256 x 192 Resolution Graphics Six (RG6~+~ ;: ‘ 2

~3., 4+, \.

shift of one full 3.58 MHz cycle. One of the differences be-

tween these access times, in the short access time frame, is

a shift of one full 3.58 MHz cycle from the corresponding

normal long access time frame, as shown in Figure 6. The

modes using short access times read memory twice as often

as the long access modes.

OPERATION OF THE VDG

A simplified block diagram of the VDG is shown in Figure

17a and a detailed block diagram is shown in Figure 17b.

The externally generated 3.58 MHz color burst clock drives

the VDG. Referring to Figures 11 and 12, note that:{{he

horizontal screen span from blanking to blanking is<J9~$~:

clock periods ( = 53.95 ps). The display window is of%~t~~mthe left-hand edge by 283 periods and lasts for,~$~~ Wiods

(35.75 vs), Of the 242 lines on the vertical scr~,~’’’?$@*blank-

ing to blanking, 192 lines are used for t%’$##ay, The

display window is offset from the top by ~t~~~~~, Under theconstraint of the master clock, the s~~$~xstjyisplay element

possible for the VDG is half perio~o’f ~$~ 3.58 MHz clock

wide by one scan line high. Al(~@~@-d?~s~lay elements are

DISPLAY MEMORY A~R~@DRIVERS

The address drive:$.~~$~ally drive the video refresh ad-

dress into the ~~p~~y’$e~emory so characters may be

displayed on th~ ~~%#$When the memory select pin (MS) is

pulled low byj~$~~:@rnal decoder, the driver outputs go to a

high-impe+@~&sfate so external three-state drivers may

switch tha~~ti’produced address onto the display memoryaddrq~~$~u~yhe MPU may directly manipulate data in the

dis~~a~:~aemory.‘~.~,~,3!,\.,,.\~., <,.!*,

VID~~ TIMING AND CONTROL

This subsystem of the VDG includes the mode decoding,timing generation, and associated row counter logic, and

uses the 3,58 MHz color frequency to generate horizontal

and vertical timing information (via linear shift register

counters), which the video and chroma encoder uses to

generate color video information. The horizontal timing for

the VDG is summarized in Figure 7. Ten and one-half cycles

of the3.58 MHz subcarrier are transmitted on the back porch

~$},,,*,-~’ ,.

of every horizontal bl~[~~~eriod. This color burst is sup-

pressed during verf~q~~~nc and equalizing intervals. Color

burst is also su~~~ss#& in the most dense two color graphic

modes. This le~$%~some interesting rainbow effects on the

display wh$~$:%quency and pattern dependent. The ver-

tical ti@#~?~~,:~e VDG is given in Figure 18. Vertical retrace

is initia%@ by the luminance signal being brought to the

bl~~]ing F&vel. The vertical blanking period begins with three

.,J$q~$:%~equalizing pulses followed by three lines of serrated: j~~e~cal sync pulses followed by three more lines of equaliz-

~%j~3;@’pulses. The remaining vertical blanking period contains

,J;~’’the normal horizontal sync pulses. The equalizing and serra-!/+\

.t~, “ tion pulses are at half line frequency, Notice the difference in

spacing between the last horizontal sync pulse and the first

equalizing pulse in even and odd fields. It is the half line dif-

ference between fields that produces the interlaced picture in

a frame. Vertical timing between fields for the non-interlaced

VDG, on the other hand, is identical, The equalizing and ser-

ration pulses are, however, at the horizontal frequency,

The 3.58 MHz color frequency is also used to clock the

video shift register load counter. This counter and the video

shift clock inhibit circuitry derive the dot-clock for the output

of the video shift registers and the load signals for the video

shift registers’ input latches. The vertical and horizontal ad-

dress counters generate the addresses for the external

display memory.

INTERNAL CHARACTER GENERATOR ROM

Since many uses of the VDG will involve the display of

alphanumeric data, a character-generator ROM is included

on the chip. This ROM will generate ~ standard 5x 7 dot

matrix characters from standard 6-bit ASCII input, A stan-

dard character set is included in the MC6W7 although the

ROM is custom programmable,

lNTERNAL/EXTERNAL CHARACTER GENERATOR

MULTIPLEXER

The internal/external multiplexer allows the use of either

the internal ROM or an external character generator. This

multiplexer may be switched on a character-by-character

basis to allow mixed internal and external characters on the

CRT, The external character may be any desired dot-pattern

in the standard 8 x 12 one-character display matrix, thus

allowing the maximum 256 x 192 screen density.

—


14

.-.

.-.

-———

FIGURE 17a – SIMPLIFIED VDG BLOCK DIAGRAM

MPU Address Bus MPU Data Bus

)<+5 Ov

4)

uVDD Vss Ks

/VDG / ‘ 13

I I

L

,,,The ~+~t o$tput of the internal/external multiplexer is,. ,,. >t,~,.... called Y. The luminance signal, Y, and the two chrominance

serializ@Q:~&%an 8-bit shift register clocked at the dot-clock

freq%:~f

outputs, @A (R-Y) and @B (B-Y), can be combined

(modulated) by an MC1372 into a composite video signalT&>”\ tirninance information from the shift register is sum- with color. Figures 8, 9, 10, and 16 show the relationship be-

med %ith the horizontal and vertical sync signals to produce tween the luminance and chrominance signals and the resul-

a composite video signal less the chrominance information, tant color.


15

FIGURE 17b – DETAILED VDG BLOCK DIAGRAM

D,splav Address B~Js

I

Zlc

xl s

INTI

ExT

INv

GM2

GM1

GM(

Cs z

‘DD

1 Vss

3*102MH2

b Svncand

Blar, kLog(c aCK D CK D

o Q

Mul[$plexer FCK D

LdlchesQ

colorB“rsIr,. .

I I \ I I I Latctes I - I I .,,-,,,. I “ I I,:,h,.I$1 IGerleratur

. . . . .CLK O“t OaIa

Log,c

4 I I A I I I IW*I D-A Ill D-A

(6 Levels) (4 Levels] P

I (R.Y) (8-Y)

,.*Odd F,eld Interlaced

FIGURE 18 – NON-INTERLACE VERTICAL TIMING

(For Interlace Vertical Timing Use Inserts)

DISPLAY MODES The 5 x 7 character font is posi~ioned two columns to the

There are two malor display modes in the VDG. Maior right and three rows down within the 8 x 12 character ele-

mode 1 contains four alphanumeric and two limited graphic ment. Six bits of the 8-bit data word are typically used for the

modes. Major mode 2 contains eight graphic modes. Of internal ASCII character generator. The remaining two bits

these, four are full color graphic and four restricted color may be used to implement inverse video, color switching, or

graphic modes. The mode selection for the VDG is sum- external character generator ROM selection on a character-

marized in Table 2. The mnemonics of these fourteen modes by-character basis. For those who wish to display lower case

are explained in the following sections. letters, special characters, or even limited-graphics:, a~~xter-

In maior mode 1 the display window is divided into 32 col- nal ROM may be used. If such external ROM is+y~~~il of

umns by 16 character element rows thus requiring 512 bytes the 8X 12 picture elements, or pixels, in the @~@$ter ele-

of memorv, Each character element is 8 half ~eriods bv 12 ment can be utilized. Characters mav be ei~~?$g$~en on a

scan lines in size as shown in Figure 19. The area outside the dark green background or orange o$~g$~~rk orange

display window is black. background, depending on the state O@TQe-Q$S pin. The in-

The VDG has a built-in character generator ROM contain- vert pin can be used to display dar~’’~~~racters on a bright

ing the 64 ASCII characters in a 5x 7 format (see Figure 20). background.,.,?YJ++F>..l..$+~

?\.:h, *:ij.:,.:..\\!~\*,.‘!$’4.

.* .,,i ,,

~tle Memory Display Elements Colors Title .4&+ ~fiernory Displey Elements Colors1

~lphanumerics 512x8

(Internal) 24 H’ 2 ‘em’g’4$h’c41 512X8

—

~tle

Mx 64 Color Graphic

128x64 Graphics’

128x 64 Color Graphic

128x 96 Graphics’


128x 192 Graphics’


256x 192 Graphics

Memory

1 kx8

lkx8

2kx8

1.5kx8

3kx8

3kx8

6kx8

6kx8

:olor:

4

2

4

2

4

2

4

2

Comments

Matrix W x 64 Elements

Matrix 128 Elements Wide byW Elements High

Matrix 128 Elements Wide by

96 Elements High


192 Elements High


192 Elements High

●Graphics mode turns on or off each element, The color may be one of two

m MOTOROLA Semiconductor Products Inc.18

..

.,-.

——

TABLE 3 – DETAILED DESCRIPTION OF VDG MODESr

VDG V“, Color TV ~rw”

W9 G/x Slx NIINT GM2 GM1 GM Css INV Cham.le, Color Background Border DmPlay M&VDG Da- S.,

,%b<,:q:&”.

Dmil

o ~ ;,:;Slack 32 Characrer$

y’,%,

D

The ALPHAN@ER@2~JERNAL m06e “=s a“ tnfer”,l chec,cter

1 0 0 0 x x x’G,..” B1aCk De, row g...lo~o~ .~h’~k.:.:~s fhe fOilOW,.Q f,.e dO1 by se... d.t

O,ange1 : ~,ack

Black 16 Characters 2

Or,”ge ‘leCk t“ rows

u

,ha,aq~fr-~i;~., t:,*aBC DE FGHIJKLMNOp OR ST UVWXy2

111111111

[\I~i*s& ‘?w%wI 1.+. –.01zMw7s. < = >? The SIX b,,. .~s@+@h;#s w. blls fr- end thwe ~Y ti externally co.

127 . . .—~

:~te~ tp<J@mode PI.S IG/X. S(K EXT/l NT. GM2. GM1 GMO

L

extr, ASCII Code.J $*ot Iw

. . . ,,}:., ;.?., \ .i~.., .<>..

. ..~,. %y1.,,, ”,! A! Phanumer8cs ,;::$,.

o ; :;:;Black S2 Cherac!er, ‘3:$

1 0 0 1 x x xG,,,” ‘%ack per cow *S+ *:,

orange

3*,*$1A•|’2•Ü?2•TheThe ALPHANUMERIC EXTERNAL mode .s.s an external ch,recter

1 y ~ ,ack

n

...$ ~ ‘*,slack ~,,ck 16 Charac(er,

generator as well as e row co..te, Thus. c.$,Om .har,c,~r f..1$ ‘r

orange “ row, . . . . lllll@graoh,c sYmbol sets w,th “O to 2* d,ffere”t S. 12 dot ch,,ac!er,

~i, .,+: . .: “:,1,. . . . may & d,$pla”ed

12 ●..:.;.

., . . ,,,$,,

1

:~;@ ~( ,’?

. . . .. . ~g:qGher*rs. .

. . . \ ‘:::,.:!.,.\J,+ ,; .<-~)y< ~,. ~, .<., .. .

LX C2 c1 co color ,t&:*0 x x x Black

1

1

1

1

D ,,:, ~~~ “

4*4M.!\f The SEMIGRAPHICS FOUR mode U*S an ,“%,,”.1 CO”<,, a(,Ph(cs

0 0 0 GreenM D8sD18Y elements

Der row T

.$ it,.? ge.erator I. Wh,ch a reC7,.gle (e,9ht dO1$ bY w.Iv. d.y.l IS d,v,ded.> ,.. .

1 0 0 1 Ye!l.w 6 LS Lz?nto four ea”al parts The lum,..nce of each part IS determ,”ed by a

‘?! ; .

1 0 1 0 x x x x x 1 0 1 0 s!”, Black32 D!soley elemen[s

! “’*” J3Yc2’c’’co’L3’L2 “1”0]

cor,espond,ng b,t 0“ the VDG data bus The color of ,Il”m,”aled Darts

0 1 1 Redis dete,m, ned by three b,,,

,0 rows

)

$!,1 0 0 Bull

1 0 1 c“..6 LI LO ;(~men, >\,,:.!.

.:}+ >.: , ..SI ex[’a

k

,>: ,,

1 1 1 0 Magenta “ ‘.*,:,; ;:.~’

1 1 1 1 Or, ”ge .. ‘ ~{:s,

Lx c1 co color

o x x Slack~.~.

1 0 0 Greenh4A44 ~$<$:%:$.

The SEMIGRA?HIC SIX mode ,S ,,m,lar to the SEMIGRAPHIC FOUR

1 0 1 YellowM D,sPla” elemenls

1

1

1, B

mode w,th th. follow, ”g differences The e,ght dot by welve dot rec-,.

14 : ~}tangle 8s dIv$fled (“!0 stx equal ports Col”r ts determined by the two

0 1 1 0 Slue B!eck ‘e’ ‘“w4 L5 (ema,”,”g b,!,

1 0 1 1 x x x x 1 1 1 Redb.\ ~:~i, ,,.P+

C] CO L5 U L3 L2 LI LO

0 x x slackW D8,PIBY elemenls 4 L~F t% . ~ b?.

0 0 Buff,“ rows

~ .. ~~~:ane

0 1 CYa.,

‘1 “w, Elemsn!1 1 0 M.ge”ta

1 1 1 O’a”ge,,,$’$

c, co color .,..::;:,0 0 Green *,,, , ~,.t

o

The COLOR GRAPHICS ONE mode “se, a me.,m.m.1 1024 bY1es of

1 Yellow Green

0

d)spley RAM 8. whch o“e oe,r of b,ls spec,l$es “ne 0,.1,,,. e!emen!

1 0 Blue

1 1 x x 0 0 0 x 1 1 R&

E;isk “-;

c, co c, co c, co c, co

1 0 0 Suff Buff

0 1 CY..,.:..i ,. ~ ~~,:.,:,

1 0 Magent,.,, “~.>t;,!$. “,:,,.

1 1 Ora”g, ~~Q+ Y~~?:

Lx Colo,

0 0 Black

1 1 x x 0 0 1 x 1 Gree,>

1 ~; 11~111111

The RESOLUTION GRAPHICS ONE mode ,,s,s 8 mex,mum of 1024

L, L@ L~ 4 L~ Is L, LO bvtes of dISDt6Y RAM,. WllICh..e bIt ,Pec,f!es one o,c~.re elemc.t

01

S.me color a,o

The COLOR GRAPHICS TWO mode CIses a max,m.m of 2W bytes

1 1 x x 0 1 0 xCOIO, Gr,Ph,c3

0.. “*:

c, co c, co c, co c1 co .1 d,splay RAM,. wll,.h one p.,r of b,ts spec,f,es one Q,ct”re element

1@ Dtsplay eieme”!s

e“ff ,“ ,.w,

0

+

The RESOLUTION GRAP14!CS TWO moae “s,s a max,m”m “f 1~

1 1 x x o 1 1 xL7L6L5b L3L2L1U by!,, of d,,Dlay RAM ,“ wh,ch one b,, ,Dec,f,es o.. P8ct”ce eleme”l

1 L7~~t,r ~,> Buff ,“ row,

12s D,,play elem,”l,

oGreen

per row 42WThe COLOR GRAPHICS THREE mode “s.s a m,xtm”m of S72 bytes

1 1 x x 1 0 0 ~+

of d,spl.y RAM I“ Wh,ch one P.,r .1 bytes spec$t,e$ one P,cl.re elec1 co c, co c, co c, co ~enl

% D8sQI,” ,Iem,”tsBuff ,“ ,Ow,

Green

:D:x -$

The RESOLUTION GRAPHIC5 THREE mode “se, a ma.,m”m of

1 1 x x 1 0W72 bytes of d,solay RAM t. Wh,ch one b,t spe.tf!es “.. p,c%.re e!e-LT 16 Lb L4 LS L2 L, LO ~en~

Buff ,“ ,Ow,

same ..10, 8s 12s D,,pla” elementsGreen ~e, ,Ow

42b i

The COLOR GRAPHICS SIX mode .%.s a max,m”m of 61M bytes of

1 1 x x 1 ~c1 co c, co c, co c, co

d,spl.y RAM IrI wl>,ch “!I. pat, .1 b,ts speclf$es one p,ct.re element

192 0),0!,” ElementsBuff ,“ ,Ow,

‘OT

:{;’~$ 0 same color 8s Green

Re,o$vt,o”f:: -b+

The RESOLUTION GRAPHICS SIX mode “s.s a m,xtm”m of 61M

1 1 x x 1 1 1 xGraph,cs One

L? L6 LS u LS Lz L, LobYIeS of d,sn!.Y RAM I. Wh,.h ..e bI1 soec,fles o.e D,ctur. eleme.t

1S.ff ,“ ,Ow,

FIGURE19– ALPHANUMERIC MODE (INTERNAL)

512 Characters (32x16)Typical Character

Oooooom00000000OODOCOODOooooomOO*OGCOC’Ooeoooc’00-0000Oooomms8$ggg380000GO’3C’Oooooooc)

– Dot Off–Dot Lit

Inverted NormalBlack Character Black BackgroundOrange or Green Orange or GreenBackground (Selectable) Character (Selectable)

Character Source:Internal – 6 Bit ASCll Generator ROM On Chip or User DefinableExternal – Users ROM

The two limited graphic modes are Semigraphics4 and

Semigraphics6. In Semigraphics 4,the8x 12 dot character

block is divided into four pixels (each pixel is four half-clocks

by six scan lines), The four low-order bits (DDO-DD3) of each

incoming byte of data select one of sixteen possible illumina-

tion patterns while the next three bits (D D4-DD6) determine

the color of the illuminated elements. The most significant

bit is unused, Figure 21 shows the color and pattern selec-

tions. In Semigraphics 6 the 8x 12 dot character block is

divided into six pixels, each four half-clocks by four scan

FIGURE 20 – AVAILABLE ALPHANUMERICS

MD4=INV=D4MD7=AS=D7

O = Inverted Character – Illuminated Background,Dark Character

–01” 2.3-4 ..5–6–7–8_9_ A_ B_ C_ D_E_F

THE 128x W COLQ~t~~$PHICS TWO (CG2) MODE –The 128 x W color q{$Q,~~~g’mode generates a display matrix128 elements wi,~e b~,~ elements high. Each element may

be one of fo~~c~(~,~s. A 2k x 8 display memory is required.

The displaW~$~w ‘~s accessed 32 times per horizontal line.

Each pik~&&qq&ls two half-clocks by three scan lines,,... $lty,$.::,.<j:,.,.

,JHE”>~~8 x 96 RESOLUTION GRAPHICS TWO (RG2)

M@QE – The 128x 96 graphics mode generates a display

~$:’%~tr!k 128 elements wide by 96 elements high. Each element

t-, ?:%@v be either ON or OFF. However, the entire dis~lav mavlines. The six low-order bits of each byte of incoming data i:~~~~be one of two colors selected by using the color set selectselect one of 64 possible illumination patterns while the CSS .J{,,l

,. pin: A 1,5k x 8 displav memorv is required, The dis~lav RAMinput and the high-order data bits (D D6-DD7) determine, the,,~

color of the illuminated elements.>,ff,$~$i,

The display window in major mode 2 (full graphio%]\ti~@a

less rigorous format than in major mode 1. ,,Jti&:~@play

elements vary from one scan line to three~~~ :~$nes in

height. The length of the display element i~#$+@’Peight or

sixteen half-periods wide. Each display el%$$s divided in-

to four or eight pixels. The former cor~~,s~~~ to a full color~:$,,1

mode while the latter a restrict@~ ~%{~~ mode, like the

semigraphics modes, represents ill~mi~tion data. When it is

high the pixel is illuminated wi~~~~w~or chosen by the col-

or set select (CSS) pin. W~~$$$.,~#~low the pixel is black. In

the full color modes, pai~~~o~i$ata bits choose one of four

colors in one of two$Jcolo’+$#5ts defined by the CSS pin,

Depending on the :$~~’b~:,the CSS pin, the area outside the

display window ~~?~$hwgreen or buff. The display formats

and color sele~~~~.~$r this major mode are summarized in

THE- ~x,@*COLOR GRAPHICS ONE (CG1) MODE –

The:i@~twolor graphics mode generates a display matrix

~~ki~~:rnents wide by 64 elements high. Each element may

b~i$~eof four colors, A Ikx 8 display memory is required.

T~@ display RAM is accessed 16 times per horizontal line.

Each pixel equals four half-clocks by three scan lines.

THE l~x64 RESOLUTION GRAPHICS .ONE (RGI)

MODE – The 128x 64 graphics mode generates a matrix

128 elements wide by 64 elements high. Each element may

be either ON or OFF. However, the entire display maybe one

of two colors, selected by using the color set select pin. A

Ikx 8 display memory is required. The display RAM is ac-

cessed 16 times per horizontal line. Each pixel equals two

half-clocks by three scan lines.

m MOTOROLA

is accessed 16 times per horizontal line. Each pixel ‘equals

two half-clocks by two scan lines.

THE 128x 96 COLOR GRAPHICS THREE (CG3) MODE –

The 128 x 96 color graphics mode generates a display 128

elements wide by 96 elements high. Each element may be

one of four colors. A 3kx 8 display memory is required, The

display RAM is accessed 32 times per horizontal line. Each

pixel equals two half-clocks by two scan lines.

THE 128x 192 RESOLUTION GRAPHICS THREE (RG3)

MODE – The 128x 192 graphics mode generates a display

matrix 128 elements wide by 192 elements high. Each ele-

ment may be either ON or OFF, but the ON element may be

one of two colors selected with the color set select pin. A

3kx8 display memory is required. The display RAM is ac-

cessed 16 times per horizontal line. Each pixel equals two

half-clocks by one scan line.

THE 128x 192 COLOR GRAPHICS SIX (CG6) MODE –

The 128 x 192 color graphics mode generates a display 128

elements wide by 192 elements high. Each element may be

one of four colors, A 6k x 8 display memory is required. The

displav RAM is accessed 32 times per horizontal line, Each

pixel equals two half-clocks by one scan line.

THE 256x 192 RESOLUTION GRAPHICS SIX (RG6)

MODE – The 256x 193 graphics mode generates a display

256 elements wide bv 192 elements high. Each element may

be either ON or OFF, but the ON element may be one of twocolors selected with the color set select pin. A 6k x 8 displaymemorv is required. The displav RAM is accessed 32 times

per horizontal line. Each pixel equals one half-clock by one

scan line.

Semiconductor Products Inc.20

FIGURE 21 – SEMIGRAPHIC MODE ENCODING

(a) Data and Display Formats

D7 D6 D5 D4 D3 D2 D1 Do

kchroma+ Luma+

Semigraphics 4

nlCSS D7 D6 D5 D4 D3 D2 D1 Do

(b) Color Selection

D6

xo0001111

SG4D5

xo0110011

~

D4

xo1010101

LumaDN

o11111111

FIGURE 22 – G@APH$& MODE ENCODING(a) Data Format

2 (T/2) + ~ $

Long Element Modes Short Element Modes

ResCol(

DN

Jtion

ModeColor

Color ModeCss BorderDN+I DN

oColor

Greeno0001111

Green

Green

Green

Green

Buff

Buff

Buff

Buff

o111

0111

Black

Green

Green

Green

Black

Buff

Buff

Buff Lo011

0011 1

Yellow

Blue

Red

Buff

Cyan

Magenta

Orange

m MOTOROLA Semiconductor Products Inc.21

TYPICAL SYSTEM IMPLEMENTATIONThe block diagram in Figure 23 shows how the VDG is

related to other functional blocks in a typical system

(non-W3). A negative row preset signal (~) generated by

the VDG initializes the row scan counter for the external

character generator once every twelve scan lines, while the

negative horizontal sync (=) acts as clock to this counter.

The negative field sync (~) generates an interrupt to the

MPU, signifying that the display memory can be updated

without interference with the VDG display function. This

signal must not be confused with the system vertical sync

signal. Field sync is activated by the end of the vertical

display window and deactivated by the trailing edge of ver-

tical sync. This gives the MPU a total of thirty-two scan lines

or 2.03 ms to update the display memory, The MPU

acknowledges the interrupt request from the VDG by bring-

ing the negative memory select input (MS) to the VDG low.

This puts the address bus output from the VDG into high-

impedance state, thus relinquishing bus control to the MPU,

The timing relationship of horizontal sync, row preset, and

field sync are shown in Figures 7, 8, and 13,

The display memory is an element-by-element map of the

display window on the screen. The VDG addresses the

display memory storage locations in succession and

translates their contents into luminance and chrominance

levels. The frequency of address update is dependent on the

length of the display element, Recall that display elements in

major mode 1 are four periods and major mode 2 are either

four or eight periods of the master clock. Data from the

dis~lay memorv is latched on everv address transition,

rows. The presence of row preset in major mode 1 serves as

a flag for the beginning of a new element row. Detection of

this signal can initiate a major mode switch from 1 to 2.

Display memory size is a function of the display density.

Quite often a graphic display contains shapes that are several

times larger than that of the display elements in the VDG.

This is particularly true of certain video games. Much, of the

display consists of a fixed background. The vertical${~~~~f a

display element can be doubled or quadrupled $~,3~Q~ig-

noring the lowest order or the first two low ord~ ~$~ical ad-dresses, respectively, from the VDG. Red~$~!&ti~J&~ address

lines naturally leads to reduction in mew+~;?e. Another

method of memory reduction is to ~$~~~ ~Bf$cts or object

fragments in ROM and store their$w’~<~%ddresses in theRAM portion of display memory. %%re~ithe larger the object

fragment, the greater the me,~’~{y s&~ng.

ASSOCIATED DEVICE>$sf~~t~, ....<:.:+.,

Mc- – syNcHRQ.&dS ADDRESS MULTIPLEXER

This device, ~,j~?ea~$ipolar companion to the MC6800 orMC6809E (e,X#[@aJff clock inputs), is primarily a VDGtransparen~~~~~~ controller. It allows the microprocessor

to load w&l$t+~$e to VDG display memory (“screen RAM”)

withoti$tw$iting for a blank screen interval. Figure 1 shows a‘~~;$s

ty,~&%l s~em using the SAM and the MC6809E, The in-

h~re%.~$interleaved direct memory accesses (I DMA) which

$~’o~~r, continuously keep the VDG updated with the proper

“%~~+a~% (independently of mode), as well as keeping the‘f$~~;%dynamic memory (used as system memory with the MC6833)

Hence, the data for the first display element must be stable ~Jj “:{$

four or eight periods before the horizontal display wi,~~ow

depending on the display mode selected. This timing +~~~f$-

ment is illustrated in Figure 6. ,.,*.V.“~$.,,,,,:.?;; ~::”..:?

Examination of Figures 21 and 22 reveal t~l~,$~’@isPlaY

elements within major mode 1 are similar w~,~~kQ,~$& within

major mode 2 are largely dissimilar. Theref@~Y~R@’de switch-.<.’:>Y.,~.j.~

ing between alphanumeric modes and %.~Q~%phic modes

can be carried out freely. Care mqS*$~e~$$aken, however,

when performing mode switching i~~rn~~o?srnode 2. The only

compatible modes are betweeqJ&~~~#~ RG 1, and between

CG6 and RG6. Minor mode,sw$~&hl& within the same major

mode in a given element r~w %$ “Be achieved as long as it is

between compatible m~des~~$hould be quite apparent that

major mode switch in~’:!d~an element-by-element basis is im-)&:!\ ,{*practical. It can be’$~~ed, however, at the expense of

added compon&&&~$nt. The element formats in the VDG~\ ‘:..,\

lend themselv~l~}~~ajor mode switching between element,..,,,,,,* “>.,

refreshed. This is done through a IDMA process as well, dur-

ing the time the VDG does not need display data (horizontal

and vertical sync times).

In addition to being a transparent memory access and

dynamic memory controller, the SAM also functions as an

external clock generator for the MC6800/6809E (slight addi-

tional circuitry is required for the MC6800).

MC1372/1373 CHROMA/RF MODULATOR

The MC1372 is a chrominance phase-shift modulator with

built in R F up-converter. The part may be used without the

RF modulator for chroma only, or the RF oscillator may be

defeated and composite chrominance and luminance can be

obtained.

The MC1373 is an RF modulator only (similar to the sec-

ond half of the MC1372) and can be used to up-modulate

separate Iuma and chroma signals at the receiver for high

quality video reception.


22

.-

..

.—.

OUTLINE DIMENSIONS

P SUFFIXPLASTIC PACKAGE

CASE 711-03

IB

I

A~ ,L , .,\gc~_{H~ iGk-F’D

SEA,$NGK -’~M

PLANE

NOTES:

1. DIMENSION mlSDATUM.

2. POSITIONAL TOLERANCE FOR LEAOS:

)$:\:\tt\.\>.~~~i)<3. m IS SEATING PLANE.

s;\ ,,i $“s,\\)* 4. OIMENSION “L”TO CENTER OF LEAOS

l;~,WHEN FORMEO PARALLEL,

5. DIMENSIONING ANOTOLERANCING

PER ANSI Y14.5, 1973.

(M)MOTOROLA Semiconductor Products Inc.25

—

2716 EPROM (supplled by the customer) from the data file

used to create the custom mask to ald n the verification pro-

cess.

ROM VERIFICATION UNITS

Ten MC6W7S containing the customer’s ROM pattern will

be sent for program verification. These units will have beenmade using the custom mask but are tor the purpose of

ROM verification only. For expedience they are usually un-

marked, packaged In ceramic, and tested only at room

temperature and 5 volts. These RVUS are Included in the

mask charge and are not production parts.

FLEXIBLE DISKS

The disk media submitted must be single-sided, single-

densltv, 8-inch, MDOS compatible flopples. The customer

must write the binary file name and company name on the

disk with a felt-tlp pen. The flopples are not to be returned by

Motorola as thev are used for archival storage. The minimum

MDOS svstem files must be on the disk as well as the ab-

solute binary object file (filename. LO type of file). An object

file made from a memorv dump using the ROLLOUT com-

mand is also admissible. Consider submitting a source

listing as well as the following files: filename .LX (EXQR-

ciser@ Ioadable format) and filename SA (ASCII S*~$~~

Code). These files will of course be kept confidentia~~~~~q[e

used 1) to speed up the process in house [f an:~$~~,~?~msarise, and 2) to speed up our customer to fact@~,41R~a~?aCe if

a user finds any software errors and needs a$s’#*&~&e quickly,,1$,,;.Jfrom the factory representatives. .;$ ,,?,b,

‘-?.!0 .MDOS is Motorola’s Disk Operatl~ %“ ‘:* $’,g~$$l~h available on

development systems such as E&{O~W~:@S, or EXORsets,

etc

@ Registered trademark of Motorola lnC.

EXORset is a trademark of Motorola Inc.


24

I~ ,

Pun I

.+,.$,,$ i. +R>t~?

APpENDl~,,.&,,,,..JCUSTOM MCW7 ORDE~lN$’’l~FORMATlONThe following informatl~~~~%$uired when ordering a

custom MCU. This info~~t~~n may be transmitted to

Motorola in the follo~$~.meflla:

PROM(s) MCM2T~’~t&fti CM2708s

MD O S disk f~;~~$c?~j

To initiate.:~,$~~ pattern for the MCU it is necessary to

first cont~i~~y~[ Ibcal field service office, local sales person,

or your l*al Motorola representative.+:$ Q~%:>;,~’~:’: \ ,,,

,@,~~s- The MCM2708 or MCM2716 type PROMS, pro-

gr~%~d with the customer program (positive logic sense

for &ddress and data), may be submitted for pattern genera-

tion. The PROMS must be clearly marked to indicate which

PROM corresponds to which address space (000-3FF HEXI,(400-7FF) or (000-7FF). See Figure 24 for recommended

marking procedure.

After the PROM(s) are marked they should be placed in

conductive IC carriers and securely packed. Do not use

stvrofoam.

FIGURE 24

n000

xxx =

– PROM

Customer

MARKING

I 400

ID

VERIFICATION MEDIA

All original pattern media (PROMS or Floppy Disk) are filed

for contractual purposes and are not returned. A computer

listing of the ROM code will be generated and returned along

with a listing verification form. The Ilstlng should be

thoroughly checked and the verlflcatlon form completed,

signed, and returned to Motorola. The signed verification

form constitutes the contractual agreement for creation of

the customer mask. If desired, Motorola will program a blank


23

NOTES1.2.

3.

4.

5.

OIMENSION-A-IS OATUM.POSITIONAL TOLERANCEFOR LEAOS:

[+ [@o.z5(0.010) @] TIA@]

~ IS SEATING PLANE.

OIMENSION LTO CENTEROF LEAOSWHEN FORMEOPARALLEL.OIMENSIONAANOBIN CLUOES MENISCUS

Motorola reserves the r(ght to make changes to any products herein to Improve reltablllty, functton or design. Motorola does not assume anyilablllty arising

out of the appllcat(on or use of any product or circuit descrtbed herein; neither does tt convey any Ilcense under tts patent rights nor the rights of others

–B MOTOROLA Semiconductor Products Inc.3501 ED BLUESTEIN BLVD AUSTIN, TEXAS 78721 ● A SUBSIDIARY OF MOTOROLA INC. —

r,,,,,-, ,,,.,,, ,. ,,,, 3-8, ,,,,.R, m ,1..” .,0,,5 ,8,,0, “s,8,,,,

.-

—- —.-—- -—.——— —.— —-—_ ———_________ ..,.——. —---- .—

Documents

The DatasheetArchive - Datasheet Search Engine › coco › mc6847_2.pdf · MCW7/MCW7Y VIDEO DISPLAY GENERATOR (VDG) The video display generator (VDG) provides a means of interfacing