The Development of a Capacitance Instrument to Optimize

i

The Development of a Capacitance Instrument to Optimize Capacitor

Bank Placement’s Equipment for Corrective Maintenance

from the Capacitance Value of Capacitor Unit

by

Rachan Chaihan

A thesis submitted in partial fulfillment of the requirements for the

degree of Master of Engineering in

Mechatronics

Examination Committee: Dr. Mongkol Ekpanyapong (Chairperson)

Dr. Manukid Parnichkun

Assoc. Prof. Erik L.J. Bohez

Nationality: Thai

Previous Degree: Bachelor of Science in Mechatronics Engineering

King Mongkut’s University of Technology

North Bangkok, Thailand

Scholarship Donor: Royal Thai Government Fellowship

Asian Institute of Technology

School of Engineering and Technology

Thailand

May 2015

http://www.asdu.ait.ac.th/faculty/FacultyByID.cfm?FacultyID=37

ii

ACKNOWLEDGEMENTS

First of all, I would like to thank to my family for their continuous support in every way

physical and mental which are a very significant motivation for me to complete this thesis.

I am deeply grateful for Dr. Mongkol Ekpanyapong for being my advisor and giving me

a valuable suggestions, inspiration, guidance and interesting lecture. Furthermore, he has

continued giving me stimulation throughout my thesis.

I also would like to express a special thanks to Dr. Manukid Parnichkun and Assoc. Prof.

Erik L.J. Bohez for great advice and suggestions of my thesis and also being my

examination committee.

My special thanks to lab supervisor, Mr. Hoang Hung Manh, senior students, Mr. Sarat

Yoowattana, Mr. Wiput Tuvayanond for special advice and techiques.

Finally, my thesis cannot be finished if I do not have all of helps from senior students,

my friends and also junior students from Mechatronic. This work cannot be done without

help from you.

iii

ABSTRACT

The challenge of the capacitance instrument consist of two main challenges. One

challenge of the capacitance instrument is to be measured the capacitor banks in high

voltage which it can be measured the AC voltage and AC current in high resolution and

high accuracy. Morover, it can be used in the area which contains a lot of harmonic noises

and high temperature. There are many techniques to design the circuit for measuring the

voltage, current, and capacitance. Furthermore, it can be rejected the harmornic noises.

In this thesis, the components of capacitance instrument board are used a high precision

and high resolution such as the resistors have the tolerance about 0.01%, the capacitors

have the tolerance about 5%. Another challenge of the capacitance instrument is to be

found the optimal value of the current unbalance for using the capacitors bank

placement’s equipment. The instrument can be recorded the value such as voltages,

currents, and capacitances. Those data will be recorded in to the tablet for processing the

capacitor banks placement equipment’s of the EGAT in order to find the optimal solution

to place the capacitor banks of each patterns by using ILP sush as the pattern of

capacitoranks 115Kv- 24Mvar-66units and 115Kv-39.6Mvar-99units. These patterns of

the capacitor banks placement connected capacitors to complex circuits.

Keywords: Capacitance Instrument, Capacitor Banks, Capacitor Unit, Integer

Linear Programming (ILP), Electricity Generating Authority of Thailand (EGAT)

iv

TABLE OF CONTENTS

CHAPTER TITLE PAGE

TITLE PAGE i

ACKNOWLEDGEMENTS ii

ABSTRACT iii

TABLE OF CONTENTS iv

LIST OF FIGURES vi

LIST OF TABLES ix

1 INTRODUCTION 1

1.1 Background/Rationale for the thesis 1

1.2 Statement of the problems 1

1.3 Objective of the thesis 2

1.4 Scopes and limitations 2

1.5 Output and expected benefits 2

1.6 Thesis outline 3

2 LITERATURE REVIEW 4

2.1 Capacitance meters 4

2.2 The placement of capacitor banks 6

2.3 Hypothesis and / or Theory 6

2.4 Capacitor banks 9

2.5 The placement of capacitor banks 10

3 METHODOLOGY 13

3.1 Working flowchart 13

3.2 Design and development of electrical system 15

3.2.1 Voltage measurement design 15

3.2.2 Current measurement design 16

3.2.3 ADC delta sigma 24bits circuit design 18

3.2.4 Power supply 20

3.2.5 Router 22

3.2.6 Line filter 22

3.2.7 Low pass filter design 22

3.2.8 Band pass filter design 25

v

3.3 Design and development of embedded system 27

3.3.1 Microcontroller board 27

3.4 Hardware architecture 28

3.5 The real construction of capacitance instrument 29

3.6 Programming 30

3.6.1 The structure of system in Matlab 31

3.7 Design algorithm for capacitor placement 32

3.7.1 The pattern of 24Mvar 33

3.7.2 The pattern of 39.6Mvar 41

3.8 The graphic user interface 50

4 RESULTS AND DISCUSSIONS 56

4.1 Band pass filter for rejection harmonic noises results 56

4.2 Moving average filter results 58

4.3 Calibrations results 60

4.3.1 Finding the equation for calibration of voltage 60

at temperature 28Co

4.3.2 Finding the equation for calibration of current 61

at temperature 28Co

4.4 Temperature compensation results 62

4.4.1 Temperature compensation result of voltage 62

measurement

4.4.2 Temperature compensation result of current 64

measurement

4.5 Experimental results 65

4.5.1 Comparison of the voltage values between 66

digital multimeter and voltage sensor

4.5.2 Comparison of the current values between 67


4.5.3 Comparison of the voltage values between 68


5 CONCLUSION AND FULTURE WORK 69

5.1 Conclusions 69

5.2 Future work 70

REFERENCES 71

vi

LIST OF FIGURES

FIGURE TITLE PAGE

Figure 1.1 Testing measure voltage and current of the capacitor bank 1

Figure 2.1 HV capacitance meter type NCM-20 instrument 4

Figure 2.2 Two probe-type capacitance meters 5

Figure 2.3 The capacitor capacitance digital meter test tester 200pF~20mF 5

Figure 2.4 Capacitance meter principle 6

Figure 2.5 The voltage drop across the capacitor and phasor diagram 6

Figure 2.6 The current proceded voltage as drop across the capacitor about 90o 7

Figure 2.7 The circuit of capacitor 8

Figure 2.8 Simulation to fine the current flowing through capacitor 9

Figure 2.9 The capacitor banks 9

Figure 2.10 Data of the placement capacitor banks from EGAT 10

Figure 2.11 Zig-Zag pattern of the placement capacitor banks from EGAT 11

Figure 2.12 Sequence pattern of the placement capacitor banks from EGAT 11

Figure 2.13 Phase patterns of the placement capacitor banks 12

Figure 3.1 Methodology flow chart 13

Figure 3.2 The overall diagram for measurement and capacitor placement 14

Figure 3.3 Block diagram of voltage measurement sensor 15

Figure 3.4 The voltage measurement sensor circuit 15

Figure 3.5 Amplifier circuit 16

Figure 3.6 Block diagram of current measurement sensor 16

Figure 3.7 The current measurement sensor circuit 17 Figure 3.8 The block diagram of ACS712 17

Figure 3.9 The voltage and current measurement board 18

Figure 3.10 ADC delta sigma 24bits circuit 18

Figure 3.11 The typical performance characteristics of LTC2440 19

Figure 3.12 ADC delta sigma 24bits circuit board 20

Figure 3.13 The power supply 20

Figure 3.14 Voltage regulator circuit 21

Figure 3.15 The capacitance instrument board 21

Figure 3.16 Wireless router 22

Figure 3.17 Line filter 22

Figure 3.18 Properties of the low pass filter 23

Figure 3.19 Active low pass filter 23

Figure 3.20 Low pass filter at frequency cutoff 55 Hz, -3dB 23

Figure 3.21 The output of low pass filter at input voltage 0.5Vrms, 50Hz 24


vii


Figure 3.24 Properties of the band pass filter 25

Figure 3.25 The Bode plot of band pass filter harmonic rejection 25

Figure 3.26 Band pass filter circuit 26

Figure 3.27 Input and output signals of band pass filter at frequency 50Hz 26

Figure 3.28 Mixed-frequency AC input signals at 50Hz and 150Hz 26

Figure 3.29 Mixed-frequency AC input signals at 50Hz and 250Hz 27

Figure 3.30 Microcontroller board 27

Figure 3.31 Hardware architecture 28

Figure 3.32 The real construction of capacitance instrument 29

Figure 3.33 The inside box of capacitance instrument 30

Figure 3.34 The flow chart of capacitance value calculation 30

Figure 3.35 The structure of system in Matlab 31

Figure 3.36 The pattern of 24Mvar 34

Figure 3.37 The result of capacitor placement for pattern 24Mvar 38

Figure 3.38 Designing the location of pattern 24Mvar 38

Figure 3.39 The number and location of capacitors pattern 24Mvar 39

Figure 3.40 The result of ILP to solving the pattern 24Mvar 39

Figure 3.41 The result of capacitors placement by using the EGAT algorithm 41

for pattern 24Mvar

Figure 3.42 The pattern of 39.6Mvar 42

Figure 3.43 The result of capacitor placement for pattern 39.6Mvar 47

Figure 3.44 Designing the location of pattern 39.6Mvar 47

Figure 3.45 The number and location of capacitors pattern 39.6Mvar 47

Figure 3.46 The result of ILP to solving the pattern 39.6Mvar 48

Figure 3.47 The result of capacitors placement by using the EGAT algorithm 50

for pattern 39.6Mvar

Figure 3.48 Default screen of GUI 51

Figure 3.49 The GUI of capacitor measurement 51

Figure 3.50 The GUI of specify for substation details 52

Figure 3.51 The GUI of display voltage, current and capacitance 52

Figure 3.52 The GUI of searching mode 53

Figure 3.53 The example to use searching mode 53

Figure 3.54 The GUI of Installation mode 54

Figure 3.55 The result of capacitor placement Phase A Side A 54

Figure 3.56 The result of capacitor placement Phase A Side B 55

Figure 4.1 The real output signal of band pass filter at frequency 50Hz 56

Figure 4.2 The real output signal of band pass filter mixed-frequency 57

AC input signals at 50Hz with 150Hz

viii





Figure 4.5 The real input and output signal of moving average filter 58

in term of opened circuit

Figure 4.6 The real input and output signals of moving average filter 59

in term of closed circuit

Figure 4.7 Equipment for calibration 59

Figure 4.8 The chart of voltage trend line in linear function 60

Figure 4.9 The chart of voltage trend line in polynomial function 60

Figure 4.10 The chart of current trend line in linear function 61

Figure 4.11 The chart of current trend line in polynomial function 61

Figure 4.12 Comparison between AC voltage from Digital multimeter and 62

AC voltage sensor

Figure 4.13 Temperature curve of the AC input voltage about 200VAC 62

Figure 4.14 Temperature curve of the AC input voltage about 200VAC 63

Figure 4.15 Comparison between AC voltage from Digital multimeter and 63

AC voltage sensor before/after using temperature compensation

Figure 4.16 Temperature curve of the AC input current about 1.9A 64

Figure 4.17 Comparison between AC current from Digital multimeter and 65

AC current sensor before/after using temperature compensation

Figure 4.18 Testing all system to measure the capacitor bank 65

Figure 4.19 The chart of voltage values 66

Figure 4.20 The chart of current values 67

Figure 4.21 The chart of capacitance values 68

ix

LIST OF TABLES

TABLE TITLE PAGE

Table 1.1 SDI Speed/Resolution Programming of LTC2440 19

Table 3.2 The equation of voltage_Fcn1 32

Table 3.3 The equation of current_Fcn2 32

Table 3.4 The capacitances for testing with ILP 34

Table 3.5 The capacitance arrangement Min-Max value for pattern 24Mvar 41

Table 3.6 The capacitance arrangement Min-Max value for pattern 39.6Mvar 50

Table 4.1 The result of voltage values 66

Table 4.2 The result of current values 67

Table 4.3 The result of capacitance values 68

1

CHAPTER 1

INTRODUCTION

1.1 Background/Rationale for the thesis

High voltage system is an important task in construction of high voltage power station.

There are many measuring instruments which have various kinds to measure the electrical

equipment. The digital multimeter is very good to measure the voltage, current, and

resistance since it is very precise but it is unreliable for measuring the capacitance. The

high voltage equipment are different from each other thus, the testing on its properties

will be different. For example, current transformer (CT) must be tested for insulation of

the CT, CT ratio, CT excitation, and etc. Power circuit breaker testing must be

experimented on insulating properties, breaker timing, functions, and etc. Nowadays, the

experiment instruments were developing with high efficiency such as reliability, validity,

precision, and repetition.

Furthermore, the experiment instrument has been developed to be lightweight which it is

suitable for using in outdoor, but some experiment must be application the existing tools.

In this thesis, the capacitance instrument is to measure the voltage 220 VAC and measure

the current flowing through the capacitor bank and after that record those data to calculate

capacitance of the capacitor. However, there are many techniques to measure voltage and

current. This project use EMI filter for eliminates noise before supply voltage to the

capacitor bank and use true RMS-to-DC converter that uses an innovative delta-sigma

computational technique to measure the AC voltage.

1.2 Statement of the problems

In the present, the department team tested of Electricity Generating Authority of Thailand

(EGAT) has not the specialized tools for measure the value of capacitor bank. Therefore,

they use one AC power supply and two digital multimeter for measurement the AC

voltage and current show in the figure1.1.

Figure 1.1 Testing measure voltage and current of the capacitor bank

Since, Electrical engineering must be used their hand for change voltage value of AC

power supply and after that check the value in digital multimeter. When they get the

voltage value, they also will read the current value in digital multimeter and after that

include all data for calculation to determine the capacitance of capacitor bank.

2

There are many problems when using that method. The first problem, it takes a long time

for adjusting the Variac to exact value. User needs to emphasize on amp-meter all the

time in purpose of collection the current and needs to adjust the Variac at the same time.

The second problem is that power supply do not has filter thus when other plant such as

welding plant, drilling plant and testing plant run at the same time, the current will be

inaccurate. The last problem is that after collects data, they need to convert to capacitance.

The commercial price of capacity instrument is about 400,000 baths and the

capacity testing system cannot analyze autonomous statistic capacity. It needs to use on

5 volt. Moreover, after testing plant gets capacitance data, installing plant needs to design

capacitor unit in capacitor bank for balancing in transmitter line.

1.3 Objective of the thesis

The main objective of this thesis is to design hardware and controller in order to measure

the capacitor bank and to design the optimal capacitor placement as following:

To develop the capacitance instrument which it can be measured the voltage,

current and capacitance of the capacitor banks in high resolution, high accuracy

at the high voltage power stations and it can be used in the area which contains a

lot of harmonic noises and high temperature.

To develop the capacitance instrument which it can be helped to find the optimal

capacitor placement for reducing the current unbalance in three phase of power

transmission lines

1.4 Scopes and limitations

This thesis is concerning about some tasks as described as follow:

Design the capacitance instrument in term of digital measurement and stand alone.

Design and develop the capacitance instruments for testing the capacitor banks in

high voltage power station.

Capacitance instrument must has the resolution and precision than the instrument

of EGAT current equipment.

1.5 Output and expected benefits

The instrument prototype will be developed and can be used to design capacitor bank

placement based on measured capacitance from high voltage power stations.

The instrument must be passed the standard of EGAT.

The instrument can be used in the area which contains a lot of electrical noise

The instrument can be reduced the working period and increased efficiency of

experiment

3

The instrument can can be optimized the corrective maintenance of conditional

unbalancing or tripping to change the spare units to reduce phase unbalancing by

automatically calculating within the measuring instrument.

1.6 Thesis outline

The organization of this thesis is as follows:

Chapter 2: This chapter describes previous research and product in commercial relates

to this thesis and also back-ground knowledge.

Chapter 3: This chapter describes the designs and methods used in the system.

Chapter 4: This chapter shows the results and evaluation.

Chapter 5: This chapter gives the conclusion and outlines future work.

4

CHAPTER 2

LITERATURE REVIEW

Instrumental in designing the placement of capacitor bank, there are few researches since

it is specifically for only the power plant. The most of capacitance instrument, those are

available in commercial products.

2.1 Capacitance meters

HV capacitance meter Type NCM-20 instrument of GENTEC Company, it has two

voltage clips in which the current is supplied into the capacitor bank. The voltage output

is short-circuit proof. The current in each capacitor unit is measured with a current clamp

probe to measure the current. As a results, the current value are inaccurate because signal

losses in cables. The Hall Effect current sensor can be connected with series circuit which

can be measured the currents directly. This device will be set the voltage then will be

measured to change the currents and can be calculated the capacitance automatically, but

it cannot record data and show the graph. Finally, this device is very expensive. The

instrument is shown in figure 2.1.

Figure 2.1 HV capacitance meter type NCM-20 instrument

Two probe-type capacitance meters are described, suitable for the measurement of

component and wiring earth capacitances in electronic apparatus. The instruments have a

range of 50 pF and consist of an indicator unit and probe. In the first instrument a

substitution method is used. The unknown capacitance can be read on the dial of a small

variable capacitor contained in the probe. Show in the figure 2.2. (L. Medina, 1954)

5

Figure 2.2 Two probe-type capacitance meters

Capacitor capacitance digital meter test tester 200pF~20mF can be measure high accuracy

of capacitance value but also measure only small capacitors. In this thesis, the instrument

function uses measurement range of estimation up to 30uF. However, it must be used

with the power capacitor (capacitor banks) that is capable of withstand the voltage about

220 VAC.

Figure 2.3 The capacitor capacitance digital meter test tester 200pF~20mF

A capacitance meter based on an oversampling sigma-delta modulator and its application

to capacitive sensor interface used the concept of convert the voltage analog to digital

converter (ADC) with 2 sigma delta ADC. A precision capacitance meter using a second

order sigma delta has been presented. An integrated version of the circuit was built in a

CMOS 0.8um technology of industrial applications on commercial sensors. (R.Gallorini,

& N.Abouchi, 2001)

6

Figure 2.4 Capacitance meter principle

2.2 The placement of capacitor banks

Optimal placement of capacitor bank in distribution network in the present of harmonic

used the fuzzy logic associated with fast decouple load flow (FDLF) SIMULINK and

analysis to analyze the effect of the capacitor against the presence of harmonics in the

distribution system which may cause resonance. Where the capacitor placement and

optimal size were managed and obtained to improve voltage profile, extinguish resonance

and reduce losses in the system due to nonlinear load. (Hablillah Bin Mohd hazim, 2012)

Optimal placement of capacitor banks and distributed generation(DGs) for losses

reduction and voltage THD improvement in distribution networks based on biogeography

based optimization (BBO) algorithm has been implemented to solve both sizing and

optimal placement of capacitor and DGs in order to decreasing radial distribution system

losses, THD (%) problems and improving voltage profile. The result shows that the real

power losses can be reduced by DG installation and capacitor at each bus of system. THD

(%) improvement and Voltage profile is obtained by DG installation and new capacitor

at each bus of system. (K. Valipour, E.Dehghan, M.H. Shariatkhah, 2013)

2.3 Hypothesis and / or Theory

Figure 2.5 The voltage drop across the capacitor and phasor diagram

i

Vc

VacVm C

VC

i

GAIN/TEMPERATURE

CONTROL

2nd ORDER SIGMA DELTA

MODULATOR

LOWPASS

FILTER

COUNTERS

DECIMATOR

SIN3C

Calibration PROM SC

DAC

VOLTAGE OUTPUT

1 BIT BINARY FLOW

PWM/10BITS DATA

10 BITS DATA

BINARY

OUTPUT

FLOW

Vs

Vr

cx

c2

7

The circuit has only one capacitor which the voltage equation is shown as C mV = V sin t.

C m

qV = = V sinωt

C Voltage (2.1)

The current equation is

C m

dqi = = V (ωC)cosωt

dt

mC

V πi = sin(ωt+ )

(1/ωC) 2

Ampere (2.2)

When we compare the equation (2.1), and (2.2), the current is lagging the voltage about

90 degree.

The phasor diagram shows the phase difference of voltage and current show in the figure

2.6 which VC will be pointed to imaginary axis (-y) and it will be pointed to real axis.

Figure 2.6 The current proceded voltage as drop across the capacitor about 90o

Defined, the XC is capacitive reactance = 1/ C .

mC

c

Vi = sin( t+ )

X 2 Ampere (2.3)

When the current flowing through the capacitor, the maximum of current is m m cI = V /X .

Example I:

In the figure 2.7, given the voltage 220 Vac the frequency is 50 Hz and the capacitor

35 uF. Find the current flowing through the capacitor and capacitance value.

IC

VC

IC VC

8

Figure 2.7 The circuit of capacitor

From the equation,

Simulation to find the current flowing through capacitor 35 uF as voltage 220 Vac and

frequency 50 Hz show in the figure 2.8.

C

C -6

Z

C

C

C

Z

1 1X = =

ωC 2πfC

1X =

2π(50H )(35×10 F)

X =90.946Ω

EI=

X

220VI= =2.419A

90.946Ω

1C=

2πfX

1C=

2π(50H )(90.946Ω)

C=34.999uF

9

Figure 2.8 Simulation to fine the current flowing through capacitor

2.4 Capacitor banks

Figure 2.9 The capacitor banks

10

A capacitor banks is a group of several identical capacitors interconnected in series or in

parallel with one another. These groups of capacitors are typically used to correct or

counteract undesirable characteristics, such as phase shifts inherent or power factor lag in

alternating current (AC) electrical power supplies. Capacitor banks may also be used in

direct current (DC) power supplies to improve the ripple current capacity and increase

stored energy of the power supply.

Single capacitors are electronic or electrical components which store electrical energy.

Capacitors consist of two conductors that are separated by dielectric or an insulating

material. When an electrical current is passed through the conductor pair, a static electric

field develops in the dielectric which represents the stored energy. Unlike batteries, this

stored energy is not maintained indefinitely, as the dielectric allows for a certain amount

of current leakage which results in the gradual dissipation of the stored energy.

The energy storing characteristic of capacitors is known as capacitance and is measured

or expressed by the unit farads. This is usually a known, fixed value for each individual

capacitor which allows for considerable flexibility in a wide range of uses such as output

smoothing in DC power supplies, restricting DC current while allowing AC current to

pass, and in the construction of resonant circuits used in radio tuning. These

characteristics also allow capacitors to be used in a group or capacitor banks to absorb

and correct AC power supply faults. (Wisegeek.org, 2003)

2.5 The placement of capacitor banks

The data’s of capacitor banks placement in the figure 2.10 consist of two patterns that are

separated by zig-zag and sequence. The value of each capacitor bank will be arranged in

ascending order show in the figure 2.11 and 2.12.

Figure 2.10 Data of the placement capacitor banks from EGAT

TO REACTOR TO REACTOR

cap 26.7054 26.8009 26.8168 26.8327 26.8486 26.8486 26.9918 26.9759 26.9282

s/n. 620 402 481 538 445 518 504 501 442

C = 17.8725 micro Farad C = 8.9884 micro Farad

cap 27.2465 27.1669 27.1669 26.9123 26.9123 26.8804 26.8804 26.8486 27.0078 27.0237 27.0396 27.0396

s/n. 531 441 393 495 460 517 498 400 457 526 499 522


cap 27.2624 27.3261 27.3420 27.4215 27.4215 27.5170 27.5170 27.6762 27.1192 27.1192 27.0714 27.0714

s/n. 552 564 772 563 551 579 561 547 539 618 192 114


Cta = 4.9280 micro Farad CT.(60C) TO CT UNBALANCE CT.(60C) Ctb = 2.4577 micro Farad

Xct1 = 645.92 Ohm Xct2 = 1295.13 Ohm

http://www.wisegeek.com/what-is-a-capacitor.htm

http://www.wisegeek.com/what-is-power-factor.htm

http://www.wisegeek.com/what-are-the-most-common-applications-for-ac-current.htm

http://www.wisegeek.org/what-are-power-supplies.htm

http://www.wisegeek.com/what-is-a-power-supply.htm

http://www.wisegeek.com/what-is-electrical-energy.htm

http://www.wisegeek.org/what-is-capacitance.htm

11

Figure 2.11 Zig-Zag pattern of the placement capacitor banks from EGAT

Figure 2.12 Sequence pattern of the placement capacitor banks from EGAT

The capacitor banks placement are in several patterns depend on each station of the power

plant. The arrangement has 2 sites which are Site A is left hand side and Site B is right

hand side in figure2.13 while each site has 3 phases consist of phase 0 Co, 120 Co and 240

Co show in the figure 2.13. The main objective is to minimize unbalance value between

Site A and Site B. Unbalance can calculate from difference vector of both current sites.

PHASE A SIDE A

2866 2837 2857 2887 2864 2949 2859 2841

2933 2906 2917 2966 2884 2957 2847 2969 2852 2888 2851 2952 2858 2848 2865 2891

REACTOR

3003 2935 2939 2958 2901 2895 2961 2836 2947 2967 2936 2854 2926 2954 2920 2907

CT UNBALANCE

620 402 481 538 445 518

531 441 393 495 460 517 498 400

REACTOR

552 564 772 563 551 579 561 547

CT UNBALANCE

12

Figure 2.13 Phase patterns of the placement capacitor banks

STEP # 2 SUBSATION : CHIANG MAI 3 Job no. TS11-16-31

Phase A

Phase B

Phase C

I 1 I 3 I 5 I 2 I 4 I 6

178.0400 A. 178.0347 A. 178.0303 A. 88.7940 A. 88.8035 A. 88.8035

0 120 240 0 120 240

Xct1 Xct3 Xct5 Xct2 Xct4 Xct6

645.9222 645.9415 645.9574 1295.133 1294.9944 1294.9939

Ohm Ohm Ohm Ohm Ohm Ohm

I unbalance 17.45802 mA.

13

CHAPTER 3

METHODOLOGY

The research methodology consists of three main processes as shows in the figure 3.1.

The first process is to design the electrical and embedded systems of the capacitance

instrument which include sensors circuit design in order to create a new prototype. The

second process is finding math equations to solve capacitors placement. The last process

is to test all systems. If the system is not standardized, the process must be started from

the beginning.

3.1 Working flowchart

Figure 3.1 Methodology flow chart

From the working flowchart as shown in the figure 3.1, the detail of every stage can be

explained as follows:

Not standardized

Standardized

Electrical system

design

Embedded systems

design

Combine two systems

Testing measurement

capacitor bank

Start

End

Studies related research

Using ILP algorithm to

solve capacitors placement

Finding math equations

Optimal Not optimal

14

Electrical system design

First of all, design the voltage and current sensor circuits by using simulation software to

test the input and output then design the PCB circuits. There are many details for

designing those sensor circuits such as frequency cutoff at 50 Hz of filter circuits,

convertor RMS to DC circuits, amplifiers circuit. All of electronic components have to

have high precision and high resolution.

Embedded system design

The output of capacitance value shows in GUI must have higher resolution and precision.

Therefore, the embedded system use the average moving filter operates by averaging a

number of points from the input signal to produce each point in the output signal.

The placement of capacitor banks will be designed collocation so that both side of

capacitance values are the most similar. In the simplest case, installation of capacitors

bank will be considered in the form of a series pattern. Installation of capacitor patterns,

it can be calculated from the reviser capacitance values.

Finding math equations to solve capacitors placement

In this thesis use the integer linear programming (ILP) to solve capacitor placement which

consist of objective function and constrain for specific condition.

The systems will be measured the voltage and current and then these data to

microcontroller for calculate to find the capacitance and send voltage value, current value,

and capacitance value to android tablet with wireless network.

Finally, the overall diagram for measurement and placement capacitors bank show in

figure 3.2.

Figure 3.2 The overall diagram for measurement and capacitor placement

Circuit to measure

capacitance

Capacitors

Unit

Microcontroller

V

I

Tablet

V I C

15

3.2 Design and development of electrical system

The electrical system design consist of three circuits such as voltage sensor circuit, current

sensor circuit and analog to digital converter.

3.2.1 Voltage measurement design

Figure 3.3 Block diagram of voltage measurement sensor

Principle of the block diagram of voltage measurement sensor. Firstly, using the step-

down transformer for reduce the input voltage from 220 Vac to 7 Vac. Secondly,

calculation the resistor for using in voltage divider from 7 Vac to 0.3 Vac before connect

to band pass filter circuit. Thirdly, using the band pass filter for rejection the harmonic

noise and the output should be still maintain the quality of the signal. Next, using the

RMS to DC for converter the AC voltage into DC voltage and this IC limit the maximum

of input signal about 1 Vac. Finally, using the amplifier circuit to amplify signal from

0.3Vdc to 1.25Vdc. Lastly, using the ADC convertor circuit to convert the analog signal

to digital signal for sending those signal into microcontroller which using SPI interface.

The maximum of input signal is limiting at 2.5Vdc depend on voltage reference circuit.

Figure 3.4 The voltage measurement sensor circuit

GND1

IN12

IN23

NC4

Vout5

RTN6

+V7

EN8

H4

LTC1968

GND

GND

AC

GAC

Voltage sensor

GND

0.1uF

C19

+5V

0.1uFC20

GND

V_sensor

1kR18

1kR19

1kR20

4.99kR21

4.99kR24

GND

1

2 4

3T1

220 to 7Vac

Out A1

-In A2

+In A3

Out B7

-In B6

+In B5 V+4

Out D14

-In D13

+In D12

Out C8

-In C9

+In C10V-11

U2

OPA1654

-5V

0.1uF

C24

1kR26 1kR27BP2

2.2uF

C25

2.2uF

C26

GND

GND

0.1uF

C22

+5V

GND

0.1uF

C23

1kR31 1kR32

2.2uFC29

2.2uFC30

GND

1kR33 1kR34

3.3uFC32

1.5uFC31

GND

VO1

VO1

1kR28 1kR29

4.7uFC28

1uFC27

GND

VO2

VO2

Out A1

-In A2

+In A3

Out B7

-In B6

+In B5 V+4

Out D14

-In D13

+In D12

Out C8

-In C9

+In C10V-11

U3

OPA1654

-5V

1kR35 1kR36

15uF

C35

390n

C36

GND

GND

0.1uF

C33

+5V

GND

0.1uF

C34

33.2kR39

25.5kR40

100n

C40

100n

C39

VO3

VO3

100n

C41

107kR41

VO4

100n

C37

100n

C38

14kR38

147kR37

VO4

O_BP2

11

22

JP4

GND

0RR22

xR23

GND

11

22

JP11

12

2JP2

BP

2

O_BP2 11

22

JP3

xR30

GND

0RR25

12

P7

IN_V

GACAC

ACGAC

GNDGND

10uFC21

Step-down

Transformer

Voltage

Divider

Band pass

Filter

RMS to DC

Amplifier

Analog to

Digital Con.

~220Vac

~7Vac ~0.3Vac ~0.3Vac ~0.3Vdc ~1.25Vdc

u-Controller

SPI

Interface

16

In the figure 3.4 show the voltage measurement sensor, including fore block diagram in

figure 3.3. One circuit for divider AC voltage after step down transfer from 0-10Vac to 0-

1Vac with the frequency of 50 Hz. And this circuit user can set the jumper for selection

band pass filter or connect directly which C20 and C24 have the value 0.1uF for elimination

DC voltage for receive only AC voltage. Second circuit is RMS to DC. This circuit use

LTC1968 from Linear Technology Company for convert AC voltage to DC voltage such

as the input 1 VAC to output 1 VDC for send that voltage to controller. Another circuit is

band pass filter. This circuit use two integrated circuits (IC) OPA1654 for operating filter

harmonic noises which in this IC have four operation amplifiers (op-amp).

Figure 3.5 Amplifier circuit

The last circuit is Amplifier circuit. This circuit use CA3140 to amplify voltage form 0-

1VDC to 0-2.5VDC for transfer voltage to Delta sigma ADC conversions. This circuit,

users can adjust the output voltage for limit value before transfer voltage to ADC

conversion.

3.2.2 Current measurement design

Figure 3.6 Block diagram of current measurement sensor

Principle of the block diagram of current measurement sensor consist of five block. First

block is the Hall Effect current sensor it can limiting the maximum input current signal

about 5A and the output become to 0.5Vac. If the input current equal to 2A, the output of

current sensor become to 0.2Vac. Second block into last block there are the same voltage

measurement sensor and connect into microcontroller another SPI port.

GND1

IN12

IN23

NC4

Vout5

RTN6

+V7

EN8

H1

LTC19680.1uF

C4400V

0.1uF

C3

+5VCC

GND

GND

10uFC6

GND

2k

R10

OFF_N1

IN-2

IN+3

V-4 OFF_N

5OUT

6V+

7STR

8H3

CA3140

0.1uF

C5

GND

+5VCC

2k

R6

4.7uF

C7Cap

GND

ADC2

AC

GAC

OutV

2k

R3

100k

R5

1 2

J2

Jumper

10k

R11

2k

R7

GND100k

R8

2k

R9

100k

R14

Hall Effect

Current

sensor

Band pass

Filter

RMS to DC

Amplifier

Analog to

Digital Con.

~2A

~0.2Vac ~0.2Vac ~0.2Vdc ~1.25Vdc

u-Controller

SPI

Interface

From LTC1968

Amplifier circuit

17

Figure 3.7 The current measurement sensor circuit

Firstly, AC power supply connect to series with current sensor at pin IP+ and IP- show in

figure 3.7. The current sensor use Hall Effect current sensor (ACS712), this device can

measure current in AC and DC. Developer can calculate about filter such as for pin6 use

two capacitor connect with parallel and in figure 3.8. Furthermore, sometime the input

voltage is high current, user can calculate to find the value of resistor R42, R44, R43, and

R45 for limit the current because the maximum of input LTC1968 is 1 VAC. The block

diagram of ACS712 has internal filter resistance (RF) equal to 1.7k. Therefore, we can

design RC Low pass filter for eliminate noise. When the resistor (RF) is 1.7k and CF =

CF1+CF2=1.68uF, the frequency cutoff is 55.73 Hz. Show in figure3.5

Figure 3.8 The block diagram of ACS712

IP1

VIOUT7

IP2

IP-4

IP-3

VCC8

GND5

FILTER6

H5

ACS712

GND

GND

12

P8

IN_AIP+ IP-

IP+IP-

Current sensor

GND1

IN12

IN23

NC4

Vout5

RTN6

+V7

EN8

H6

LTC1968

GND

GND

IP-IP+

150kR42

210kR44

0.1uF

C45

0.1uF

C42

+5V

+5V

GND

0.1uFC43

GND

C_sensor

0.68uF

CF21

12

2JP7

Out A1

-In A2

+In A3

Out B7

-In B6

+In B5 V+4

Out D14

-In D13

+In D12

Out C8

-In C9

+In C10V-11

U4

OPA1654

GND

-5V

2.2uF

C481kR46 1kR47

BP

1

BP1

2.2uF

C49

2.2uF

C50

GND

GND

0.1uF

C46

+5V

GND

0.1uF

C47

1kR50 1kR51

2.2uFC53

2.2uFC54

GND

1kR52 1kR53

3.3uFC56

1.5uFC55

GND

O1

O1

1kR48 1kR49

4.7uFC52

1uFC51

GND

O2

O2

Out A1

-In A2

+In A3

Out B7

-In B6

+In B5 V+4

Out D14

-In D13

+In D12

Out C8

-In C9

+In C10V-11

U5

OPA1654

-5V

1kR54 1kR55

15uF

C59

390n

C60

GND

GND

0.1uF

C57

+5V

GND

0.1uF

C58

33.2kR58

25.5kR59

100n

C64

100n

C63

GNDGND

O3

O3

100n

C65

107kR60

O4

100n

C61

100n

C62

14kR57

147kR56

O4

O_BP1

11

22

JP5

O_BP10RR43

xR45

GND

11

22

JP6

11

22

JP8

10uFC44

1uF

CF1

18

Secondly, the output of current sensor about 0.2Vac when we measure the capacitor bank

at 26.74uF with 220 Vac and then connect to band pass filter circuit, RMS to DC circuit,

Amplifier circuit, and Analog to digital converter circuit respectively.

Figure 3.9 The voltage and current measurement board

In the figure 3.9 show all components of voltage and current sensor circuit board when we

already design and assembly components. This board can measure only AC voltage and

AC current. The advantage of this board is used the high precision of each devices such as

the resistor has tolerance 0.01%, the capacitor has tolerance 5%, and the capacitor has the

tolerance 3%. Therefore, the output are close to the actual voltage and current. Another

advantage of this board is resistant to interference of noise because we used more RC Low

pass filter to eliminate high frequency effect cause by noise. The last advantage can measure

high voltage the range about 0-500 VAC and current about 0-7 Ampere. In this thesis use

voltage estimate 220 VAC and current estimate 2 Ampere.

3.2.3 ADC delta sigma 24bits circuit design

Figure 3.10 ADC delta sigma 24bits circuit

In the figure 3.10 show the circuit of analog to digital converter. The LTC2440 is a high

speed 24bit. It uses proprietary delta-sigma architecture enabling variable speed and

NR1

GND2

Vtrim3

Vout4

NC5

NC6

NC7

Vin8

H1

LT1027

GNDGND

GND1

VCC2

REF+3

REF-4 SCK

13FO14

BUSY15

GND16

IN+5

IN-6

SDI7

GND8

GND9

EXT10CS11SDO12

H3

LTC2440CNG

GND1

VCC2

REF+3

REF-4 SCK

13FO14

BUSY15

GND16

IN+5

IN-6

SDI7

GND8

GND9

EXT10CS11SDO12

H2

LTC2440CNG

GND GND GND GND

1uFC6

1uFC5

9V

5V5V

5V_Ref

5V_Ref 5V_Ref

GND GNDGNDGND

IN+(1) IN+(2)CS1

MISO1SCK1

CS2MISO2

SCK2SCK2MISO2CS2

5V_Ref5V_RefSCK1MISO1CS1

GND GND

1uFC7

GND

Output

Voltage &

Current

Input AC

Current

Input AC

Voltage

Power

Supply

5V

Voltage reference

ADC delta sigma

24bits (For current)

ADC delta sigma

24bits (For voltage)

19

resolution with no latency. This device require the voltage reference at pin3. Therefore, the

LT1027 is support that requirement of reference voltage which the output voltage of

LTC1027 estimate 5.0002 VDC. In this thesis, we use two ADC for measure voltage and

current. The communication of output LTC2440 is Serial Peripheral Interface (SPI) that it

can set the speed, resolution and oversample ratio (OSR) for select effect of RMS noise

shown in table 3.1.

Table 1.1 SDI Speed/Resolution Programming of LTC2440

In this thesis, we set status of the OSR in maximum value of chip for select the conversion

rate 6.875Hz or 145ms because the RMS noise is very small about 200nV. Furthermore,

the conversion time is take a long time but, the effect of noise is small.

Figure 3.11 The typical performance characteristics of LTC2440

In the figure 3.11 show the comparison between effect by noise in 200nV at fOUT = 6.875Hz

and 23uV at fOUT = 3.5 kHz. In addition, if VIN are -0.5-1 volt, the INL error will be stable.

20

The input of ADC can support the maximum voltage to 2.5VDC but, it is stable to 1VDC.

Therefore, we can limiting the input of ADC about 0-1VDC for stabilized.

Figure 3.12 ADC delta sigma 24bits circuit board

ADC delta sigma 24bits can reading the analog input from current and voltage sensor

between 0-2.5 VDC and can convert that data to digital in SPI communication. The

advantage of this board can measuring two channel in 24bits. For example, one channel for

measuring the current and another channel for measuring the voltage. Another advantage

can setting the speed, resolution and oversample rate for eliminate noise when this board

convert those data. The last advantage is that output is high resolution when the

microcontroller receive those data. For example, if the maximum output range show in 0-

220VAC and the reference voltage is 2.5VDC, we can convert the data to that range is show

in the equation (3.1).

When VIN=220VAC;

23 23

DC 23

IN

OUT

2.5×2 2.5×2V = = =2.5VDC

V 2

V =2.5×88=220VAC

(3.1)

3.2.4 Power supply

Figure 3.13 The power supply

SPI

interface Power supply

12V and 5V

Input

signal

Power supply 12V dc, 5A

Voltage regulator 5V dc, 2A, 2 channel

12V dc

21

The power supply 12Vdc, 5A have the specifications thus, Electrical phase 1, Input voltage

85-264V ac, Line regulation ± 0.1%, Load regulation ± 1%, Maximum temperature +70 oC,

Minimum temperature -25 oC, Output current 5A, Output voltage 12V dc, Weight 0.5kg,

and Tipple and Nose 20mV Pk-Pk. The output of this connect to ADC delta sigma 24Bits

circuit board which have the circuit of voltage regulator 5V dc,2A, 2 channel for using it to

the input of microcontroller and voltage & current board. The voltage regulator use

LM340S for regulator voltage from 12Vdc to 5 Vdc. This IC have the specifications thus,

Maximum output current 2.4A, Output voltage 5V, Line regulation 50mV, and Load

regulation 50mV. Show in Figure 3.14.

Figure 3.14 Voltage regulator circuit

The MC7809CD2R4G is voltage regulator has the output 9Vdc for connect to input of

Voltage reference LT1027.

Figure 3.15 The capacitance instrument board

The capacitance instrument board second version are combine all circuit into this board

which consist of seven parts. First part are include more DC power supply 12V, 5V, and

3.3V. Second part are microcontroller module consist of LCD module and ARM cortex

12V IN1

2OUT

3Reg1 MC7809CD2TR4G

IN1

2

OUT3

Reg2 LM340S

1uFC3

1uFC4

1uFC1

1uFC2

GND GND

5V(2)9V 12V

GND GND

12V 9V 12V 5V(2)

IN1

2

OUT3

Reg3 LM340S

1uFC8

1uFC9

GND

5V(1)12V

GND

12V 5V(1)

22

M4. Third part is internet module for connect with wireless. Forth part is USB module

for connect with computer to show data. Fifth part are include two temperature sensors

and two humidity sensors for measuring temperature and humidity inside and outside box.

Next part is voltage sensor for measure high voltage in capacitors bank. Last part is

current sensor for measure the current through capacitors banks.

3.2.5 Router

Figure 3.16 Wireless router

In the figure 3.16 show the Wireless router of Tenda W150M. The specifications of this

Wireless router thus, support AP mode, Client+AP(WiFi Bridge), WDS+AP, WISP,

Wireless router, WiFi b/g/n 150Mbps, security 64/128-bit WEP, WPA, and WPA2,

LAN/WAN 1 channel 10/100Mbps. This router can distribute signal about data of AC

voltage, AC current, and capacitance of capacitor banks to Tablet. The tablet will received

those data for process to find the location of capacitor placement.

3.2.6 Line filter

Figure 3.17 Line filter

Line filter is circuit to eliminate noise caused by the instability of the power supplied to the

electrical equipment which in side of this device has passive low pass filter. This filter can

filter noise at frequency 50-60 Hz.

3.2.7 Low pass filter design

Simulation active low pass filter by using program Multisim for elimination harmonics

noise at frequency 150Hz, 250Hz, and 350Hz. The circuit show in figure 3.17.

R1470kΩ

C10.47µF

C22200pF

C32200pF

C40.47µF

L1

2mH

L2

2mH

V1

220 Vrms

50 Hz

0° LOAD

23

Figure 3.18 Properties of the low pass filter

Figure 3.19 Active low pass filter

In part of designing active low pass filter which it can setting parameter such as pass

frequency = 55 Hz, stop frequency = 70 Hz, pass band gain = -1 dB, stop band gain = -25

dB, filter load = 2 MΩ, and resistance in LP = 100 Ω. This program can use Bode function

to help for finding and display the frequency can pass or cannot pass at -3 dB shown in

figure 3.20.

Figure 3.20 Low pass filter at frequency cutoff 55 Hz, -3dB

Next, using the oscilloscope function to measure the signal show in figure 3.21, 3.22, and

3.23.

V2

0.5 Vrms

50 Hz

0°

100Ω

R11

100Ω

R12

44.13µF

C12

54.69µF

C11

OPAMP_3T_VIRTUAL

X1100Ω

R21

100Ω

R22

17.23µF

C22

74.72µF

C21

OPAMP_3T_VIRTUAL

X2100Ω

R31

100Ω

R32

4.3µF

C32

204.1µF

C31

OPAMP_3T_VIRTUAL

X3

OUTPUT

24

Figure 3.21 The output of low pass filter at input voltage 0.5Vrms, 50Hz

In the figure 3.21, the output signal can pass the frequency at 50Hz and input voltage at

0.5Vrms which the output voltage estimate 1.679Vrms.



In the figure 3.22 and 3.23 show the output signal cannot pass at frequency 150Hz and

250Hz which the output signal is closing to zero.

25

3.2.8 Band pass filter design

The target to design the band pass filter circuit is rejection the harmonic noises at

frequency 150 Hz (3rdharmonic), 250 Hz (5th), and 350Hz (7th) which reference the

properties of band pass filter show in the figure 3.24.

Figure 3.24 Properties of the band pass filter

In part of designing active band pass filter which it can setting essential parameters such as

Low end pass frequency = 35.35 Hz, Low end stop frequency = 30.35 Hz, High end pass

frequency = 64.65 Hz, High end stop frequency = 69.65 Hz, Pass band gain -1dB, Stop

band gain = -3dB, Filter load 2MΩ, Resistance in LP = 1 kΩ, and Capacitance in LP

0.1uF.This software can use Bode function to help for finding and display the frequency

can pass or cannot pass at -3 dB shown in the figure3.27-3.29.

Figure 3.25 The Bode plot of band pass filter harmonic rejection

Finally, the circuit of band pass filter is showing in the figure 3.25 which consist of seven

order to filter harmonic noise. The AC input voltage estimate 7 Vrms connect to the

voltage divider circuit for reducing the signal at 0.1Vrms and connect to the band pass

filter circuit seven order for rejection harmonic noise. The output signal is still similar to

the input.

26

Figure 3.26 Band pass filter circuit

Testing the simulation of band pass filter circuit at amplitude 0.1V and frequency 50Hz.

The output signal is shown in the figure 3.27 which the output signal still similar

sinusoidal waveform but, the starting time will be delayed about 5-10 ms.

Figure 3.27 Input and output signals of band pass filter at frequency 50Hz

Figure 3.28 Mixed-frequency AC input signals at 50Hz and 150Hz

XSC1

A B

Ext Trig+

+

_

_ + _

V1

7 Vrms

50 Hz

0°

V515 Vrms

250 Hz

0°

A2

1 V/V

0 V

A

C

B

V6 5 Vrms

150 Hz

0°

XBP2

IN OUT

1kΩ

R12

2.2µF

C12

2.2µF

C11

1000Ω

R21

1000Ω

R22

1µF

C22

1µF

C21

1000Ω

R31

1000Ω

R32

1.5µF

C32

3.3µF

C31

1000Ω

R41

1000Ω

R42

1µF

C42

10µF

C41

1000Ω

R51

1000Ω

R52

390nF

C52

22µF

C51

100nF

CA11

100nF

CA12

100nF

CA1333.2kΩ

RA12

107kΩ

RA13

25.5kΩ

RA11

100nF

CA21

100nF

CA22147kΩ

RA22

10kΩ

RA21

U15

CA3140M

3

2

4

7

6

51

8

VEE

-5V

VDD

5V

U1

CA3140M

3

2

4

7

6

51

8

VEE

-5V

VDD

5V

U2

CA3140M

3

2

4

7

6

51

8

VEE

-5V

VDD

5V

U3

CA3140M

3

2

4

7

6

51

8

VEE

-5V

VDD

5V

U4

CA3140M

3

2

4

7

6

51

8

VEE

-5V

VDD

5V

U5

CA3140M

3

2

4

7

6

51

8

VEE

-5V

VDD

5V

U11

CA3140M

3

2

4

7

6

51

8

VEE

-5V

VDD

5VR1410kΩ

GND GND GND

GND

GNDGND

GNDGND

XMM2

GND

GND

J3

Key = B

R1100kΩ

1kΩ

R12

Channel A

“Input”

Channel B

“Output”

Channel A

“Input”

Channel B

“Outputt”

27

Figure 3.29 Mixed-frequency AC input signals at 50Hz and 250Hz

In the figure 3.28 and 3.29 show the output of band pass filter when mixing the AC input

signal at frequency 50Hz, 150Hz, 250Hz together. These outputs can rejection harmonic

noises at frequency 150Hz and 250Hz but, it’s still voltages treatment at frequency 50Hz.

3.3 Design and development of embedded system

In this thesis use the microcontroller of Arm Cortex M4 board show in the figure 3.30

which this board can support serial port, USB, and Lan interface.

3.3.1 Microcontroller board

Figure 3.30 Microcontroller board

In the figure 3.30 show the microcontroller board, This board use ARM 7 STM32F4 have

the specifications thus, frequency up to 168MHz, IC chip is STM32F407VGT6 32-bits, 2

x 12-bits D/A convertors, 3 x 12bits A/D convertors, 1 MB of flash memory, 3.6V down to

1.7V VDD, Up to 3 x I2C interfaces (SMBus/PMBus), Up to 4 USARTs, Up to 3 SPIs (42

MB/s), and 2 x CAN interfaces (2.0B Active). The aMG Ethernet INF is module Lan for

aMG Ethernet INF

Lan interface

aMG USB Convertor

Serial interface

ARM 7 STM32F4DISCOVERY

SPI port

LCD

Channel A

“Output”

Channel B

“Input”

28

connect to router. It can transfer signal distribution to tablet. The aMG USB convertor is

module serial port. If user want to know about data, they can connect this module to USB

port in your computer.

3.4 Hardware architecture

Figure 3.31 Hardware architecture

According to the figure 3.31, this shows the hardware architecture. The input 220 VAC

connect with circuit breaker that breaker can protect the overcurrent and then connect with

power supply has the output 12 VDC after that connect the output to ADC 24Bits board.

The ADC board can convert the signal from Analog to Digital in high precision and it can

regulator the voltage from 12Vdc to 5Vdc for connect to voltage and current board, and

Microcontroller board. The output interface of this board use Serial Peripheral Interface

(SPI) connect to Microcontroller board and ADC board can receive the input signal from

voltage & current board. The Voltage & Current board can measure AC voltage and AC

current. The output of voltage & current board are dc voltage connect to input signal of

Capacitor banks

Switch

Line filter

Input ~220 Vac

220 Vac

Power supply

Circuit

Breaker

Microcontroller

Router

Tablet

5V

29

ADC board and input of this board connect to capacitor bank and it is controlled by switch

when we would like to measure the capacitance. The microcontroller board connect with

router and ADC board for receive the digital signal.

3.5 The real construction of capacitance instrument

Figure 3.32 The real construction of capacitance instrument

In the figure 3.32 show the real construction of capacitance instrument consist of more

components such as wireless module, switch measure when users would like to measure

capacitance in capacitor banks, external temperature and humidity sensors, LCD display,

and breaker. When the circuit breaker turn on, the all of component boards are ready to

use. The user can connect AC voltage input about 100-250Vac for power source of

capacitor banks. When user would like to measure the capacitance, they can push the

measure switch when that switch turn on the AC voltage will connect to the capacitor

banks. Furthermore, the voltage and current board will measured the voltage and current

and then transfer those voltage to ADC delta sigma 24bits board for convert those analog

signal to digital signal and the interface of this board use SPI connect with microcontroller

board for process and calculate to find the capacitance value. The LCD display can show

about the AC voltage, AC current, and capacitance value on real time.

Connector for

connect with

Capacitor bank

AC voltage

input

30

Figure 3.33 The inside box of capacitance instrument

In the figure 3.33 show inside box of capacitance instrument consist of main components

such as line filter, DC power supply, capacitance instrument board, and cooling fun.

3.6 Programming

The program to display the value of capacitor bank on LCD is written in ARM cortex M4

were as follows.

Figure 3.34 The flow chart of capacitance value calculation

Turn on ARM board

and circuit

Calculate the

value of voltage

Transfe

r

Get the analog

value of

Volt

Finish

Display all of parameters on

LCD

Finish

Get

the analog

value of

Amp

Calculate the value of current

Compute the value

of capacitor

Finish

Finish

Transfer

31

3.6.1 The structure of system in Matlab

Figure 3.35 The structure of system in Matlab

The structure of program in Matlab which is compiled later to ARM board is show in the

figure 3.35.

A0 is parameter configuration of ARM board such as compiler, USART, and SPI.

A1, A2 is setting channel, and data read count of SPI1 for current and SPI3 for voltage.

B1, B2 is functions to read and convert data of SPI 24bits.

C1, C2 is moving average filter.

Fcn1 is equation to convert and calibrate data for voltage.

Fcn2 is equation to convert and calibrate data for current.

D is function for calculate to find the capacitance value.

E is function for display the parameters on serial port.

F is function for display the parameters on LCD.

G is setting the ADC delta sigma 24bits to low noise.

A0

Fcn1

A1

A2

B1

B2

C1

C2

D E

F

G

32

Table 3.2 The equation of voltage_Fcn1

Parameter Value

Expression U(1)*476.21780+34.01544

Sampling Time 0.01s

Table 3.3 The equation of current_Fcn2

Parameter Value

Expression U(1)*6.39621-0.01812

Sampling Time 0.01s

In the table 3.2 and 3.3 show the equations for real voltage and current value when

measuring the AC voltage and AC current. These equation will be converted the value

from ADC to new value which these new value should approximate or equivalent digital

multimeter. The equations reference from the figure 4.8 to figure 4.11.

Finally, the value of capacitor bank calculated bases on two equations.

(3.2)

(3.3)

3.7 Design algorithm for capacitor placement

The integer linear programming consist of two function; first function is objective function

that have the expression to be maximized or minimized. Another function is constraints

function. The inequalities Ax ≥ b and x ≤ 0 are the constraints function which specify a

convex polytope over which the objective function is to be optimized.

The algorithm for capacitor placement use the integer linear programming (ILP) to balance

between phase A, B, C side A and phase A, B, C side B for decrease the current unbalance

these phase which as follows.

Objective function:

Minimize z (3.4)

Constraints function:

Summation the capacitance of each phase and each side.

i C, j A,A xij = CAA for i = 1,2,…..,n,

i C, j A,B xij = CAB for j = 1,2,…..,m,

i C, j A,C xij = CAC (3.5)

i C, j B,A xij = CBA

i C, j B,B xij = CBB

Fcn2 C

C

EX =

I

1C=

2×π×50×X

33

i C, j B,C xij = CBC

Comparison between the capacitance phase A side A and phase A side B.

z + CAA – CAB ≥ 0 for b = 0,0.01,…..,p,

z + CAA – CAB ≤ b (3.6)

Comparison between the capacitance phase B side A and phase B side B.

z + CBA – CBB ≥ 0

z + CBA – CBB ≤ b (3.7)

Comparison between the capacitance phase A side A and phase A side B.

z + CCA – CCB ≥ 0

z + CCA – CCB ≤ b (3.8)

The equation 3.14 is forcing the capacitors can be placed for each one location.

j A U B xij = 1 (3.9)

Xij is capacitor number i and position j

CAA is summation of capacitor phase A side A

CAB is summation of capacitor phase A side B

CAC is summation of capacitor phase A side C

CBA is summation of capacitor phase B side A

CBB is summation of capacitor phase B side B

CBC is summation of capacitor phase B side C

b is the variable to limit boundary

z is the optimal value of capacitance between side A and side B

The data pattern to placement capacitors bank from EGAT consist of two patterns such

as 24Mvar and 39.6Mvar

3.7.1 The pattern of 24Mvar

The data pattern 24Mvar is separate into 6 groups show in the figure 3.35

34

Figure 3.36 The pattern of 24Mvar

Those capacitors connect to series and separate into 6 groups which those groups have

to balance between capacitor phase A, B, and C side A and phase A, B, and C side B.

Therefore, using the algorithm ILP to solve this pattern as follows.

Assume the capacitance 18 values;

Table 3.4 The capacitances for testing with ILP

Numbers Capacitances Numbers Capacitances

1 25.1258 9 25.8856

2 25.2487 10 26.5582

3 28.4456 11 28.3354

4 28.1523 12 27.7512

5 27.4489 13 24.5542

6 26.2254 14 26.8879

7 26.9984 15 29.4584

8 27.6251 16 24.9457

The equation as follows,

Minimize z

A side A A side B

A B C

B side A B side B C side A C side B

AA1

AA2

AA3

BA1

BA2

BA3

CA1

CA2

CA3

AB1

AB2

AB3

BB1

BB2

BB3

CB1

CB2

CB3

35

25.1258x1,1 + 25.2487x2,1 + 28.4456x3,1 + 28.1523x4,1 + 27.4489x5,1 + 26.2254x6,1 + 26.9984x7,1 + 27.6251x8,1

+ 25.8856x9,1 + 26.5582x10,1 + 28.3354x11,1 + 27.7512x12,1 + 24.5542x13,1 + 26.8879x14,1 + 29.4584x15,1 +

24.9457x16,1 + 25.6678x17,1 + 29.2245x18,1 - AA1 = 0

25.1258x1,2 + 25.2487x2,2 + 28.4456x3,2 + 28.1523x4,2 + 27.4489x5,2 + 26.2254x6,2 + 26.9984x7,2 + 27.6251x8,2

+ 25.8856x9,2 + 26.5582x10,2 + 28.3354x11,2 + 27.7512x12,2 + 24.5542x13,2 + 26.8879x14,2 + 29.4584x15,2 +

24.9457x16,2 + 25.6678x17,2 + 29.2245x18,2 - BA1 = 0

25.1258x1,3 + 25.2487x2,3 + 28.4456x3,3 + 28.1523x4,3 + 27.4489x5,3 + 26.2254x6,3 + 26.9984x7,3 + 27.6251x8,3

+ 25.8856x9,3 + 26.5582x10,3 + 28.3354x11,3 + 27.7512x12,3 + 24.5542x13,3 + 26.8879x14,3 + 29.4584x15,3 +

24.9457x16,3 + 25.6678x17,3 + 29.2245x18,3 - CA1 = 0

25.1258x1,4 + 25.2487x2,4 + 28.4456x3,4 + 28.1523x4,4 + 27.4489x5,4 + 26.2254x6,4 + 26.9984x7,4 + 27.6251x8,4

+ 25.8856x9,4 + 26.5582x10,4 + 28.3354x11,4 + 27.7512x12,4 + 24.5542x13,4 + 26.8879x14,4 + 29.4584x15,4 +

24.9457x16,4 + 25.6678x17,4 + 29.2245x18,4 - AB1 = 0

25.1258x1,5 + 25.2487x2,5 + 28.4456x3,5 + 28.1523x4,5 + 27.4489x5,5 + 26.2254x6,5 + 26.9984x7,5 + 27.6251x8,5

+ 25.8856x9,5 + 26.5582x10,5 + 28.3354x11,5 + 27.7512x12,5 + 24.5542x13,5 + 26.8879x14,5 + 29.4584x15,5 +

24.9457x16,5 + 25.6678x17,5 + 29.2245x18,5 - BB1 = 0

25.1258x1,6 + 25.2487x2,6 + 28.4456x3,6 + 28.1523x4,6 + 27.4489x5,6 + 26.2254x6,6 + 26.9984x7,6 + 27.6251x8,6

+ 25.8856x9,6 + 26.5582x10,6 + 28.3354x11,6 + 27.7512x12,6 + 24.5542x13,6 + 26.8879x14,6 + 29.4584x15,6 +

24.9457x16,6 + 25.6678x17,6 + 29.2245x18,6 - CB1 = 0

25.1258x1,7 + 25.2487x2,7 + 28.4456x3,7 + 28.1523x4,7 + 27.4489x5,7 + 26.2254x6,7 + 26.9984x7,7 + 27.6251x8,7

+ 25.8856x9,7 + 26.5582x10,7 + 28.3354x11,7 + 27.7512x12,7 + 24.5542x13,7 + 26.8879x14,7 + 29.4584x15,7 +

24.9457x16,7 + 25.6678x17,7 + 29.2245x18,7 - AA2 = 0

25.1258x1,8 + 25.2487x2,8 + 28.4456x3,8 + 28.1523x4,8 + 27.4489x5,8 + 26.2254x6,8 + 26.9984x7,8 + 27.6251x8,8

+ 25.8856x9,8 + 26.5582x10,8 + 28.3354x11,8 + 27.7512x12,8 + 24.5542x13,8 + 26.8879x14,8 + 29.4584x15,8 +

24.9457x16,8 + 25.6678x17,8 + 29.2245x18,8 - BA2 = 0

25.1258x1,9 + 25.2487x2,9 + 28.4456x3,9 + 28.1523x4,9 + 27.4489x5,9 + 26.2254x6,9 + 26.9984x7,9 + 27.6251x8,9

+ 25.8856x9,9 + 26.5582x10,9 + 28.3354x11,9 + 27.7512x12,9 + 24.5542x13,9 + 26.8879x14,9 + 29.4584x15,9 +

24.9457x16,9 + 25.6678x17,9 + 29.2245x18,9 - CA2 = 0

25.1258x1,10 + 25.2487x2,10 + 28.4456x3,10 + 28.1523x4,10 + 27.4489x5,10 + 26.2254x6,10 + 26.9984x7,10 +

27.6251x8,10 + 25.8856x9,10 + 26.5582x10,10 + 28.3354x11,10 + 27.7512x12,10 + 24.5542x13,10 + 26.8879x14,10

+ 29.4584x15,10 + 24.9457x16,10 + 25.6678x17,10 + 29.2245x18,10 - AB2 = 0

25.1258x1,11 + 25.2487x2,11 + 28.4456x3,11 + 28.1523x4,11 + 27.4489x5,11 + 26.2254x6,11 + 26.9984x7,11 +

27.6251x8,11 + 25.8856x9,11 + 26.5582x10,11 + 28.3354x11,11 + 27.7512x12,11 + 24.5542x13,11 + 26.8879x14,11

+ 29.4584x15,11 + 24.9457x16,11 + 25.6678x17,11 + 29.2245x18,11 - BB2 = 0

25.1258x1,12 + 25.2487x2,12 + 28.4456x3,12 + 28.1523x4,12 + 27.4489x5,12 + 26.2254x6,12 + 26.9984x7,12 +

27.6251x8,12 + 25.8856x9,12 + 26.5582x10,12 + 28.3354x11,12 + 27.7512x12,12 + 24.5542x13,12 + 26.8879x14,12

+ 29.4584x15,12 + 24.9457x16,12 + 25.6678x17,12 + 29.2245x18,12 - CB2 = 0

25.1258x1,13 + 25.2487x2,13 + 28.4456x3,13 + 28.1523x4,13 + 27.4489x5,13 + 26.2254x6,13 + 26.9984x7,13 +

27.6251x8,13 + 25.8856x9,13 + 26.5582x10,13 + 28.3354x11,13 + 27.7512x12,13 + 24.5542x13,13 + 26.8879x14,13

+ 29.4584x15,13 + 24.9457x16,13 + 25.6678x17,13 + 29.2245x18,13 - AA3 = 0

25.1258x1,14 + 25.2487x2,14 + 28.4456x3,14 + 28.1523x4,14 + 27.4489x5,14 + 26.2254x6,14 + 26.9984x7,14 +

27.6251x8,14 + 25.8856x9,14 + 26.5582x10,14 + 28.3354x11,14 + 27.7512x12,14 + 24.5542x13,14 + 26.8879x14,14

+ 29.4584x15,14 + 24.9457x16,14 + 25.6678x17,14 + 29.2245x18,14 - BA3 = 0

25.1258x1,15 + 25.2487x2,15 + 28.4456x3,15 + 28.1523x4,15 + 27.4489x5,15 + 26.2254x6,15 + 26.9984x7,15 +

27.6251x8,15 + 25.8856x9,15 + 26.5582x10,15 + 28.3354x11,15 + 27.7512x12,15 + 24.5542x13,15 + 26.8879x14,15

+ 29.4584x15,15 + 24.9457x16,15 + 25.6678x17,15 + 29.2245x18,15 - CA3 = 0

25.1258x1,16 + 25.2487x2,16 + 28.4456x3,16 + 28.1523x4,16 + 27.4489x5,16 + 26.2254x6,16 + 26.9984x7,16 +

27.6251x8,16 + 25.8856x9,16 + 26.5582x10,16 + 28.3354x11,16 + 27.7512x12,16 + 24.5542x13,16 + 26.8879x14,16

+ 29.4584x15,16 + 24.9457x16,16 + 25.6678x17,16 + 29.2245x18,16 - AB3 = 0

36

25.1258x1,17 + 25.2487x2,17 + 28.4456x3,17 + 28.1523x4,17 + 27.4489x5,17 + 26.2254x6,17 + 26.9984x7,17 +

27.6251x8,17 + 25.8856x9,17 + 26.5582x10,17 + 28.3354x11,17 + 27.7512x12,17 + 24.5542x13,17 + 26.8879x14,17

+ 29.4584x15,17 + 24.9457x16,17 + 25.6678x17,17 + 29.2245x18,17 - BB3 = 0

25.1258x1,18 + 25.2487x2,18 + 28.4456x3,18 + 28.1523x4,18 + 27.4489x5,18 + 26.2254x6,18 + 26.9984x7,18 +

27.6251x8,18 + 25.8856x9,18 + 26.5582x10,18 + 28.3354x11,18 + 27.7512x12,18 + 24.5542x13,18 + 26.8879x14,18

+ 29.4584x15,18 + 24.9457x16,18 + 25.6678x17,18 + 29.2245x18,18 - CB3 = 0

The average of summation the capacitance of each Phase side A

AA1+AA2+AA3 -3PAA = 0

BA1+BA2+BA3 -3PBA = 0 (3.10)

CA1+CA2+CA3 -3PCA = 0

The average of summation the capacitance of each Phase side B

AB1+AB2+AB3 -3PAB = 0

BB1+BB2+BB3 -3PBB = 0 (3.11)

CB1+CB2+CB3 -3PCB = 0

Comparison between Phase A Side A and Phase A Side B

z+PAA-PAB >= 0 (3.12)

z+PAA-PAB <= 0.045

Comparison between Phase A Side B and Phase B Side B

z+PBA-PBB >= 0 (3.13)

z+PBA-PBB <= 0.045

Comparison between Phase C Side A and Phase C Side B

z+PCA-PCB >= 0 (3.14)

z+PCA-PCB <= 0.045

x1,1 + x2,1 + x3,1 + x4,1 + x5,1 + x6,1 + x7,1 + x8,1 + x9,1 + x10,1 + x11,1 + x12,1 + x13,1 +

x14,1 + x15,1 + x16,1 + x17,1 + x18,1 = 1

x1,2 + x2,2 + x3,2 + x4,2 + x5,2 + x6,2 + x7,2 + x8,2 + x9,2 + x10,2 + x11,2 + x12,2 + x13,2 +

x14,2 + x15,2 + x16,2 + x17,2 + x18,2 = 1

x1,3 + x2,3 + x3,3 + x4,3 + x5,3 + x6,3 + x7,3 + x8,3 + x9,3 + x10,3 + x11,3 + x12,3 + x13,3 +

x14,3 + x15,3 + x16,3 + x17,3 + x18,3 = 1

x1,4 + x2,4 + x3,4 + x4,4 + x5,4 + x6,4 + x7,4 + x8,4 + x9,4 + x10,4 + x11,4 + x12,4 + x13,4 +

x14,4 + x15,4 + x16,4 + x17,4 + x18,4 = 1

x1,5 + x2,5 + x3,5 + x4,5 + x5,5 + x6,5 + x7,5 + x8,5 + x9,5 + x10,5 + x11,5 + x12,5 + x13,5 +

x14,5 + x15,5 + x16,5 + x17,5 + x18,5 = 1

x1,6 + x2,6 + x3,6 + x4,6 + x5,6 + x6,6 + x7,6 + x8,6 + x9,6 + x10,6 + x11,6 + x12,6 + x13,6 +

x14,6 + x15,6 + x16,6 + x17,6 + x18,6 = 1

x1,7 + x2,7 + x3,7 + x4,7 + x5,7 + x6,7 + x7,7 + x8,7 + x9,7 + x10,7 + x11,7 + x12,7 + x13,7 +

x14,7 + x15,7 + x16,7 + x17,7 + x18,7 = 1

x1,8 + x2,8 + x3,8 + x4,8 + x5,8 + x6,8 + x7,8 + x8,8 + x9,8 + x10,8 + x11,8 + x12,8 + x13,8 +

x14,8 + x15,8 + x16,8 + x17,8 + x18,8 = 1

x1,9 + x2,9 + x3,9 + x4,9 + x5,9 + x6,9 + x7,9 + x8,9 + x9,9 + x10,9 + x11,9 + x12,9 + x13,9 +

x14,9 + x15,9 + x16,9 + x17,9 + x18,9 = 1

37

x1,10 + x2,10 + x3,10 + x4,10 + x5,10 + x6,10 + x7,10 + x8,10 + x9,10 + x10,10 + x11,10 + x12,10 +

x13,10 + x14,10 + x15,10 + x16,10 + x17,10 + x18,10 = 1

x1,11 + x2,11 + x3,11 + x4,11 + x5,11 + x6,11 + x7,11 + x8,11 + x9,11 + x10,11 + x11,11 + x12,11 +

x13,11 + x14,11 + x15,11 + x16,11 + x17,11 + x18,11 = 1

x1,12 + x2,12 + x3,12 + x4,12 + x5,12 + x6,12 + x7,12 + x8,12 + x9,12 + x10,12 + x11,12 + x12,12 +

x13,12 + x14,12 + x15,12 + x16,12 + x17,12 + x18,12 = 1

x1,13 + x2,13 + x3,13 + x4,13 + x5,13 + x6,13 + x7,13 + x8,13 + x9,13 + x10,13 + x11,13 + x12,13 +

x13,13 + x14,13 + x15,13 + x16,13 + x17,13 + x18,13 = 1

x1,14 + x2,14 + x3,14 + x4,14 + x5,14 + x6,14 + x7,14 + x8,14 + x9,14 + x10,14 + x11,14 + x12,14 +

x13,14 + x14,14 + x15,14 + x16,14 + x17,14 + x18,14 = 1

x1,15 + x2,15 + x3,15 + x4,15 + x5,15 + x6,15 + x7,15 + x8,15 + x9,15 + x10,15 + x11,15 + x12,15 +

x13,15 + x14,15 + x15,15 + x16,15 + x17,15 + x18,15 = 1

x1,16 + x2,16 + x3,16 + x4,16 + x5,16 + x6,16 + x7,16 + x8,16 + x9,16 + x10,16 + x11,16 + x12,16 +

x13,16 + x14,16 + x15,16 + x16,16 + x17,16 + x18,16 = 1

x1,17 + x2,17 + x3,17 + x4,17 + x5,17 + x6,17 + x7,17 + x8,17 + x9,17 + x10,17 + x11,17 + x12,17 +

x13,17 + x14,17 + x15,17 + x16,17 + x17,17 + x18,17 = 1

x1,18 + x2,18 + x3,18 + x4,18 + x5,18 + x6,18 + x7,18 + x8,18 + x9,18 + x10,18 + x11,18 + x12,18 +

x13,18 + x14,18 + x15,18 + x16,18 + x17,18 + x18,18 = 1

x1,1 + x1,2 + x1,3 + x1,4 + x1,5 + x1,6 + x1,7 + x1,8 + x1,9 + x1,10 + x1,11 + x1,12 + x1,13 +

x1,14 + x1,15 + x1,16 + x1,17 + x1,18 = 1

x2,1 + x2,2 + x2,3 + x2,4 + x2,5 + x2,6 + x2,7 + x2,8 + x2,9 + x2,10 + x2,11 + x2,12 + x2,13 +

x2,14 + x2,15 + x2,16 + x2,17 + x2,18 = 1

x3,1 + x3,2 + x3,3 + x3,4 + x3,5 + x3,6 + x3,7 + x3,8 + x3,9 + x3,10 + x3,11 + x3,12 + x3,13 +

x3,14 + x3,15 + x3,16 + x3,17 + x3,18 = 1

x4,1 + x4,2 + x4,3 + x4,4 + x4,5 + x4,6 + x4,7 + x4,8 + x4,9 + x4,10 + x4,11 + x4,12 + x4,13 +

x4,14 + x4,15 + x4,16 + x4,17 + x4,18 = 1

x5,1 + x5,2 + x5,3 + x5,4 + x5,5 + x5,6 + x5,7 + x5,8 + x5,9 + x5,10 + x5,11 + x5,12 + x5,13 +

x5,14 + x5,15 + x5,16 + x5,17 + x5,18 = 1

x6,1 + x6,2 + x6,3 + x6,4 + x6,5 + x6,6 + x6,7 + x6,8 + x6,9 + x6,10 + x6,11 + x6,12 + x6,13 +

x6,14 + x6,15 + x6,16 + x6,17 + x6,18 = 1

x7,1 + x7,2 + x7,3 + x7,4 + x7,5 + x7,6 + x7,7 + x7,8 + x7,9 + x7,10 + x7,11 + x7,12 + x7,13 +

x7,14 + x7,15 + x7,16 + x7,17 + x7,18 = 1

x8,1 + x8,2 + x8,3 + x8,4 + x8,5 + x8,6 + x8,7 + x8,8 + x8,9 + x8,10 + x8,11 + x8,12 + x8,13 +

x8,14 + x8,15 + x8,16 + x8,17 + x8,18 = 1

x9,1 + x9,2 + x9,3 + x9,4 + x9,5 + x9,6 + x9,7 + x9,8 + x9,9 + x9,10 + x9,11 + x9,12 + x9,13 +

x9,14 + x9,15 + x9,16 + x9,17 + x9,18 = 1

x10,1 + x10,2 + x10,3 + x10,4 + x10,5 + x10,6 + x10,7 + x10,8 + x10,9 + x10,10 + x10,11 + x10,12 +

x10,13 + x10,14 + x10,15 + x10,16 + x10,17 + x10,18 = 1

x11,1 + x11,2 + x11,3 + x11,4 + x11,5 + x11,6 + x11,7 + x11,8 + x11,9 + x11,10 + x11,11 + x11,12 +

x1,13 + x11,14 + x11,15 + x11,16 + x11,17 + x11,18 = 1

x12,1 + x12,2 + x12,3 + x12,4 + x12,5 + x12,6 + x12,7 + x12,8 + x12,9 + x12,10 + x12,11 + x12,12 +

x1,13 + x12,14 + x12,15 + x12,16 + x12,17 + x12,18 = 1

x13,1 + x13,2 + x13,3 + x13,4 + x13,5 + x13,6 + x13,7 + x13,8 + x13,9 + x13,10 + x13,11 + x13,12 +

x13,13 + x13,14 + x13,15 + x13,16 + x13,17 + x13,18 = 1

x14,1 + x14,2 + x14,3 + x14,4 + x14,5 + x14,6 + x14,7 + x14,8 + x14,9 + x14,10 + x14,11 + x14,12 +

x14,13 + x14,14 + x14,15 + x14,16 + x14,17 + x14,18 = 1

x15,1 + x15,2 + x15,3 + x15,4 + x15,5 + x15,6 + x15,7 + x15,8 + x15,9 + x15,10 + x15,11 + x15,12 +

x15,13 + x15,14 + x15,15 + x15,16 + x15,17 + x15,18 = 1

x16,1 + x16,2 + x16,3 + x16,4 + x16,5 + x16,6 + x16,7 + x16,8 + x16,9 + x16,10 + x16,11 + x16,12 +

x16,13 + x16,14 + x16,15 + x16,16 + x16,17 + x16,18 = 1

x17,1 + x17,2 + x17,3 + x17,4 + x17,5 + x17,6 + x17,7 + x17,8 + x17,9 + x17,10 + x17,11 + x17,12 +

x17,13 + x17,14 + x17,15 + x17,16 + x17,17 + x17,18 = 1

x18,1 + x18,2 + x18,3 + x18,4 + x18,5 + x18,6 + x18,7 + x18,8 + x18,9 + x18,10 + x18,11 + x18,12 +

x18,13 + x18,14 + x18,15 + x18,16 + x18,17 + x18,18 = 1

38

Using program IPsolve to solve this pattern the result show in the figure 3.37.

Figure 3.37 The result of capacitor placement for pattern 24Mvar

After calculation, the location of capacitor placement shown in the figure 3.38.

Figure 3.38 Designing the location of pattern 24Mvar

From the result, we can placement the capacitors which x[i,j] are capacitors number i at

location j.

b

1

7

2

8

5

11

6

12

3

9

4

10

13 14 17 18 15 16

39

Figure 3.39 The number and location of capacitors pattern 24Mvar

When the capacitors are placed, the result show below.

Figure 3.40 The result of ILP to solving the pattern 24Mvar

Finally, calculation to find the capacitances of each groups the result as follows.

1

2

3

1C = =9.2766 uF

1 1 1+ +

27.6251 26.5582 29.4584

1C = =8.8289 uF

1 1 1+ +

24.9457 25.6687 29.2245

1C = =8.7452 uF

1 1 1+ +

27.4489 26.8879 24.5542

4

5

5

1C = =9.2837 uF

1 1 1+ +

28.1523 26.9984 28.4456

1C = =8.8473 uF

1 1 1+ +

25.2487 26.2254 28.3354

1C = =8.7362 uF

1 1 1+ +

25.1258 25.8856 27.7512

Calculation to find the current unbalance as follows,

The impedances of each phases each sides can calculated.

1

1

2

2

3

3

1 1PhaseA,SideA; xct = = =343.1326Ω

2π50C 2×π×50×9.2766

1 1PhaseB,SideA; xct = = =360.5313Ω

2π50C 2×π×50×8.8289

1 1PhaseC,SideA; xct = = =363.9842Ω

2π50C 2×π×50×8.7452

b

x8,1

x10,7

x16,2

x17,8

x2,5

x6,11

x1,6

x9,12

x5,3

x14,9

x4,4

x7,10

x15,13 x18,14 x11,17 x12,18 x13,15 x3,16

b

27.6251uF

26.5582uF

24.9457uF

25.6687uF

25.2487uF

26.2254uF

25.1258uF

25.8856uF

27.4489uF

26.8879uF

28.1523uF

26.9984uF

29.4584uF 29.2245uF 28.3354uF 27.7512uF 24.5542uF 28.4456uF

C1 C2 C3 C4 C5 C6

40

4

4

5

5

6

6

1 1PhaseA,SideB; xct = = =342.8679Ω

2π50C 2×π×50×9.2837

1 1PhaseB,SideB; xct = = =319.6389Ω

2π50C 2×π×50×8.8473


2π50C 2×π×50×8.7362

(3.15)

Next, calculation to find the current of each phases each sides.

1

1

2

2

3

3

115000I = =335.1474A

xct

115000I = =318.9737A

xct

115000I = =315.9478A

xct

,

4

4

5

5

6

6

115000I = =335.4061A

xct

115000I = =319.6389A

xct

115000I = =315.6256A

xct

(3.16)

Cos0 = 1

Cos120 = -0.5

Cos240 = -0.5

,

Sin0 = 0

Sin120 = 0.866

Sin240 = -0.866

Next, calculation to find the current of each phases each sides.

AAc 1

BAc 2

CAc 3

I I cos(0) =335.1474A

I I cos(120)=-159.4868A

I I cos(240)=-157.9739A

=

=

=

, AAs 1

BAs 2

CAs 3

I I sin(0) =0A

I I sin(120)=276.2393A

I I sin(240)=-273.6188A

=

=

=

ABc 4

BBc 5

CBc 6

I I cos(0) =335.4061A

I I cos(120)=-159.8195A

I I cos(240)=-157.8128A

=

=

=

, ABs 4

BBs 5

CBs 6

I I sin(0) =0A

I I sin(120)=276.8154A

I I sin(240)=-273.3398A

=

=

=

AAc BAc CAc

AAs BAs CAs

A

A

sum(I c)

sum(I s)

I I I I =17.6867A

I I I I =2.6205A

= + +

= + +

ABc BBc CBc

ABs BBs CBs

B

B

sum(I c)

sum(I s)

I I I I =17.7738A

I I I I =3.4756A

= + +

= + +

The current of side A and side B,

41

a

b

BA

BA

sum(I c) sum(I c)

sum(I s) sum(I s)

I =I I =17.6867-17.7738=-0.0872A

I =I I =2.6205-3.4756=-0.8551A

-

-

Finally, the result of current unbalance is;

2 2 2 2

unbalance a b

unbalance

I I I (-0.0872) +(-0.8551)

I 860mA

= + =

= (3.17)

Using EGAT algorithm to find the capacitors placement as follows,

Firstly, rearrange the numbers of capacitance to Min-Max values

Table 3.5 The capacitance arrangement Min-Max value for pattern 24Mvar

Min-Max Min-Max

24.5542 26.8879

24.9457 26.9984

25.1258 27.4489

25.2487 27.7512

25.6678 28.1523

25.8856 28.3354

26.2254 28.4456

26.5582 29.2245

26.8879 29.4584

Secondly, arrangement all of the capacitances from left to right and right to left.

Figure 3.41 The result of capacitors placement by using the EGAT algorithm for

pattern 24Mvar

Finally, calculation to find the current unbalance the result is 5.1876A.

Therefore, the result of current unbalance by ILP algorithm better than EGAT algorithm.

3.7.2 The pattern of 39.6Mvar

The data pattern of 39.6Mvar is separated into 6 groups show in the figure 3.42

b

24.5542uF

27.6251uF

24.9457uF

27.4489uF

25.6687uF

26.5582uf

25.2487uF

26.8879uF

25.1258uF

26.9984uF

25.8856uF

26.2254uF

27.7512uF 28.1523uF 29.2245uF 28.4456uF 28.3354uF 29.4584uF

C1 C2 C3 C4 C5 C6

42

Figure 3.42 The pattern of 39.6Mvar

The equation as follows,

Minimize z

25.1258x1,1 + 25.1258x1,2 + 25.2487x2,1 + 25.2487x2,2 + 28.4456x3,1 + 28.4456x3,2 + 28.1523x4,1

+ 28.1523x4,2 + 27.4489x5,1 + 27.4489x5,2 + 26.2254x6,1 + 26.2254x6,2 + 26.9984x7,1 + 26.9984x7,2

+ 27.6251x8,1 + 27.6251x8,2 + 25.8856x9,1 + 25.8856x9,2 + 26.5582x10,1 + 26.5582x10,2 +

28.3354x11,1 + 28.3354x11,2 + 27.7512x12,1 + 27.7512x12,2 + 24.5542x13,1 + 24.5542x13,2 +

26.8879x14,1 + 26.8879x14,2 + 29.4584x15,1 + 29.4584x15,2 + 24.9457x16,1 + 24.9457x16,2 +

25.6678x17,1 + 25.6678x17,2 + 29.2245x18,1 + 29.2245x18,2 - 2AA1 = 0

25.1258x1,3 + 25.1258x1,4 + 25.2487x2,3 + 25.2487x2,4 + 28.4456x3,3 + 28.4456x3,4 + 28.1523x4,3

+ 28.1523x4,4 + 27.4489x5,3 + 27.4489x5,4 + 26.2254x6,3 + 26.2254x6,4 + 26.9984x7,3 + 26.9984x7,4

+ 27.6251x8,3 + 27.6251x8,4 + 25.8856x9,3 + 25.8856x9,4 + 26.5582x10,3 + 26.5582x10,4 +

28.3354x11,3 + 28.3354x11,4 + 27.7512x12,3 + 27.7512x12,4 + 24.5542x13,3 + 24.5542x13,4 +

26.8879x14,3 + 26.8879x14,4 + 29.4584x15,3 + 29.4584x15,4 + 24.9457x16,3 + 24.9457x16,4 +

25.6678x17,3 + 25.6678x17,4 + 29.2245x18,3 + 29.2245x18,4 - 2BA1 = 0

25.1258x1,5 + 25.1258x1,6 + 25.2487x2,5 + 25.2487x2,6 + 28.4456x3,5 + 28.4456x3,6 + 28.1523x4,5

+ 28.1523x4,6 + 27.4489x5,5 + 27.4489x5,6 + 26.2254x6,5 + 26.2254x6,6 + 26.9984x7,5 + 26.9984x7,6

+ 27.6251x8,5 + 27.6251x8,6 + 25.8856x9,5 + 25.8856x9,6 + 26.5582x10,5 + 26.5582x10,6 +

28.3354x11,5 + 28.3354x11,6 + 27.7512x12,5 + 27.7512x12,6 + 24.5542x13,5 + 24.5542x13,6 +

26.8879x14,5 + 26.8879x14,6 + 29.4584x15,5 + 29.4584x15,6 + 24.9457x16,5 + 24.9457x16,6 +

25.6678x17,5 + 25.6678x17,6 + 29.2245x18,5 + 29.2245x18,6 - 2CA1 = 0

25.1258x1,7 + 25.1258x1,8 + 25.2487x2,7 + 25.2487x2,8 + 28.4456x3,7 + 28.4456x3,8 + 28.1523x4,7

+ 28.1523x4,8 + 27.4489x5,7 + 27.4489x5,8 + 26.2254x6,7 + 26.2254x6,8 + 26.9984x7,7 + 26.9984x7,8

A side A A side B

A B C

B side A B side B C side A C side B

AA1

AA2

BA1

BA2

CA1

CA2

AB

BB

CB

43

+ 27.6251x8,7 + 27.6251x8,8 + 25.8856x9,7 + 25.8856x9,8 + 26.5582x10,7 + 26.5582x10,8 +

28.3354x11,7 + 28.3354x11,8 + 27.7512x12,7 + 27.7512x12,8 + 24.5542x13,7 + 24.5542x13,8 +

26.8879x14,7 + 26.8879x14,8 + 29.4584x15,7 + 29.4584x15,8 + 24.9457x16,7 + 24.9457x16,8 +

25.6678x17,7 + 25.6678x17,8 + 29.2245x18,7 + 29.2245x18,8 - 2AA2 = 0

25.1258x1,9 + 25.1258x1,10 + 25.2487x2,9 + 25.2487x2,10 + 28.4456x3,9 + 28.4456x3,10 +

28.1523x4,9 + 28.1523x4,10 + 27.4489x5,9 + 27.4489x5,10 + 26.2254x6,9 + 26.2254x6,10 +

26.9984x7,9 + 26.9984x7,10 + 27.6251x8,9 + 27.6251x8,10 + 25.8856x9,9 + 25.8856x9,10 +

26.5582x10,9 + 26.5582x10,10 + 28.3354x11,9 + 28.3354x11,10 + 27.7512x12,9 + 27.7512x12,10 +

24.5542x13,9 + 24.5542x13,10 + 26.8879x14,9 + 26.8879x14,10 + 29.4584x15,9 + 29.4584x15,10 +

24.9457x16,9 + 24.9457x16,10 + 25.6678x17,9 + 25.6678x17,10 + 29.2245x18,9 + 29.2245x18,10 -

2BA2 = 0

25.1258x1,11 + 25.1258x1,12 + 25.2487x2,11 + 25.2487x2,12 + 28.4456x3,11 + 28.4456x3,12 +

28.1523x4,11 + 28.1523x4,12 + 27.4489x5,11 + 27.4489x5,12 + 26.2254x6,11 + 26.2254x6,12 +

26.9984x7,11 + 26.9984x7,12 + 27.6251x8,11 + 27.6251x8,12 + 25.8856x9,11 + 25.8856x9,12 +

26.5582x10,11 + 26.5582x10,12 + 28.3354x11,11 + 28.3354x11,12 + 27.7512x12,11 + 27.7512x12,12 +

24.5542x13,11 + 24.5542x13,12 + 26.8879x14,11 + 26.8879x14,12 + 29.4584x15,11 + 29.4584x15,12 +

24.9457x16,11 + 24.9457x16,12 + 25.6678x17,11 + 25.6678x17,12 + 29.2245x18,11 + 29.2245x18,12 -

2CA2 = 0

25.1258x1,13 + 25.1258x1,14 + 25.2487x2,13 + 25.2487x2,14 + 28.4456x3,13 + 28.4456x3,14 +

28.1523x4,13 + 28.1523x4,14 + 27.4489x5,13 + 27.4489x5,14 + 26.2254x6,13 + 26.2254x6,14 +

26.9984x7,13 + 26.9984x7,14 + 27.6251x8,13 + 27.6251x8,14 + 25.8856x9,13 + 25.8856x9,14 +

26.5582x10,13 + 26.5582x10,14 + 28.3354x11,13 + 28.3354x11,14 + 27.7512x12,13 + 27.7512x12,14 +

24.5542x13,13 + 24.5542x13,14 + 26.8879x14,13 + 26.8879x14,14 + 29.4584x15,13 + 29.4584x15,14 +

24.9457x16,13 + 24.9457x16,14 + 25.6678x17,13 + 25.6678x17,14 + 29.2245x18,13 + 29.2245x18,14 -

2AB = 0

25.1258x1,15 + 25.1258x1,16 + 25.2487x2,15 + 25.2487x2,16 + 28.4456x3,15 + 28.4456x3,16 +

28.1523x4,15 + 28.1523x4,16 + 27.4489x5,15 + 27.4489x5,16 + 26.2254x6,15 + 26.2254x6,16 +

26.9984x7,15 + 26.9984x7,16 + 27.6251x8,15 + 27.6251x8,16 + 25.8856x9,15 + 25.8856x9,16 +

26.5582x10,15 + 26.5582x10,16 + 28.3354x11,15 + 28.3354x11,16 + 27.7512x12,15 + 27.7512x12,16 +

24.5542x13,15 + 24.5542x13,16 + 26.8879x14,15 + 26.8879x14,16 + 29.4584x15,15 + 29.4584x15,16 +

24.9457x16,15 + 24.9457x16,16 + 25.6678x17,15 + 25.6678x17,16 + 29.2245x18,15 + 29.2245x18,16 -

2BB = 0

25.1258x1,17 + 25.1258x1,18 + 25.2487x2,17 + 25.2487x2,18 + 28.4456x3,17 + 28.4456x3,18 +

28.1523x4,17 + 28.1523x4,18 + 27.4489x5,17 + 27.4489x5,18 + 26.2254x6,17 + 26.2254x6,18 +

26.9984x7,17 + 26.9984x7,18 + 27.6251x8,17 + 27.6251x8,18 + 25.8856x9,17 + 25.8856x9,18 +

26.5582x10,17 + 26.5582x10,18 + 28.3354x11,17 + 28.3354x11,18 + 27.7512x12,17 + 27.7512x12,18 +

24.5542x13,17 + 24.5542x13,18 + 26.8879x14,17 + 26.8879x14,18 + 29.4584x15,17 + 29.4584x15,18 +

24.9457x16,17 + 24.9457x16,18 + 25.6678x17,17 + 25.6678x17,18 + 29.2245x18,17 + 29.2245x18,18 -

2CB = 0

Comparison between phase A and B side A and phase C side A for row number 1.

z+AA1-BA1 >= 0

z+AA1-BA1 <= 0.104

z+AA1-CA1 >= 0

z+AA1-CA1 <= 0.104 (3.18)

z+BA1-CA1 >= 0

z+BA1-CA1 <= 0.104

Comparison between phase A and B side A and phase C side A for row number 2.

z+AA2-BA2 >= 0

44

z+AA2-BA2 <= 0.08

z+AA2-CA2 >= 0

z+AA2-CA2 <= 0.08 (3.19)

z+BA2-CA2 >= 0

z+BA2-CA2 <= 0.08

Comparison between phase A and B side A and phase C side B for row number 1.

z+AB-BB >= 0

z+AB-BB <= 0.07

z+AB-CB >= 0

z+AB-CB <= 0.07 (3.20) z+BB-CB >= 0

z+BB-CB <= 0.07

x1,1 + x2,1 + x3,1 + x4,1 + x5,1 + x6,1 + x7,1 + x8,1 + x9,1 + x10,1 + x11,1 + x12,1 + x13,1 +

x14,1 + x15,1 + x16,1 + x17,1 + x18,1 = 1

x1,2 + x2,2 + x3,2 + x4,2 + x5,2 + x6,2 + x7,2 + x8,2 + x9,2 + x10,2 + x11,2 + x12,2 + x13,2 +

x14,2 + x15,2 + x16,2 + x17,2 + x18,2 = 1

x1,3 + x2,3 + x3,3 + x4,3 + x5,3 + x6,3 + x7,3 + x8,3 + x9,3 + x10,3 + x11,3 + x12,3 + x13,3 +

x14,3 + x15,3 + x16,3 + x17,3 + x18,3 = 1

x1,4 + x2,4 + x3,4 + x4,4 + x5,4 + x6,4 + x7,4 + x8,4 + x9,4 + x10,4 + x11,4 + x12,4 + x13,4 +

x14,4 + x15,4 + x16,4 + x17,4 + x18,4 = 1

x1,5 + x2,5 + x3,5 + x4,5 + x5,5 + x6,5 + x7,5 + x8,5 + x9,5 + x10,5 + x11,5 + x12,5 + x13,5 +

x14,5 + x15,5 + x16,5 + x17,5 + x18,5 = 1

x1,6 + x2,6 + x3,6 + x4,6 + x5,6 + x6,6 + x7,6 + x8,6 + x9,6 + x10,6 + x11,6 + x12,6 + x13,6 +

x14,6 + x15,6 + x16,6 + x17,6 + x18,6 = 1

x1,7 + x2,7 + x3,7 + x4,7 + x5,7 + x6,7 + x7,7 + x8,7 + x9,7 + x10,7 + x11,7 + x12,7 + x13,7 +

x14,7 + x15,7 + x16,7 + x17,7 + x18,7 = 1

x1,8 + x2,8 + x3,8 + x4,8 + x5,8 + x6,8 + x7,8 + x8,8 + x9,8 + x10,8 + x11,8 + x12,8 + x13,8 +

x14,8 + x15,8 + x16,8 + x17,8 + x18,8 = 1

x1,9 + x2,9 + x3,9 + x4,9 + x5,9 + x6,9 + x7,9 + x8,9 + x9,9 + x10,9 + x11,9 + x12,9 + x13,9 +

x14,9 + x15,9 + x16,9 + x17,9 + x18,9 = 1

x1,10 + x2,10 + x3,10 + x4,10 + x5,10 + x6,10 + x7,10 + x8,10 + x9,10 + x10,10 + x11,10 + x12,10 +

x13,10 + x14,10 + x15,10 + x16,10 + x17,10 + x18,10 = 1

x1,11 + x2,11 + x3,11 + x4,11 + x5,11 + x6,11 + x7,11 + x8,11 + x9,11 + x10,11 + x11,11 + x12,11 +

x13,11 + x14,11 + x15,11 + x16,11 + x17,11 + x18,11 = 1

x1,12 + x2,12 + x3,12 + x4,12 + x5,12 + x6,12 + x7,12 + x8,12 + x9,12 + x10,12 + x11,12 + x12,12 +

x13,12 + x14,12 + x15,12 + x16,12 + x17,12 + x18,12 = 1

x1,13 + x2,13 + x3,13 + x4,13 + x5,13 + x6,13 + x7,13 + x8,13 + x9,13 + x10,13 + x11,13 + x12,13 +

x13,13 + x14,13 + x15,13 + x16,13 + x17,13 + x18,13 = 1

x1,14 + x2,14 + x3,14 + x4,14 + x5,14 + x6,14 + x7,14 + x8,14 + x9,14 + x10,14 + x11,14 + x12,14 +

x13,14 + x14,14 + x15,14 + x16,14 + x17,14 + x18,14 = 1

x1,15 + x2,15 + x3,15 + x4,15 + x5,15 + x6,15 + x7,15 + x8,15 + x9,15 + x10,15 + x11,15 + x12,15 +

x13,15 + x14,15 + x15,15 + x16,15 + x17,15 + x18,15 = 1

x1,16 + x2,16 + x3,16 + x4,16 + x5,16 + x6,16 + x7,16 + x8,16 + x9,16 + x10,16 + x11,16 + x12,16 +

x13,16 + x14,16 + x15,16 + x16,16 + x17,16 + x18,16 = 1

x1,17 + x2,17 + x3,17 + x4,17 + x5,17 + x6,17 + x7,17 + x8,17 + x9,17 + x10,17 + x11,17 + x12,17 +

x13,17 + x14,17 + x15,17 + x16,17 + x17,17 + x18,17 = 1

x1,18 + x2,18 + x3,18 + x4,18 + x5,18 + x6,18 + x7,18 + x8,18 + x9,18 + x10,18 + x11,18 + x12,18 +

x13,18 + x14,18 + x15,18 + x16,18 + x17,18 + x18,18 = 1

x1,1 + x1,2 + x1,3 + x1,4 + x1,5 + x1,6 + x1,7 + x1,8 + x1,9 + x1,10 + x1,11 + x1,12 + x1,13 +

x1,14 + x1,15 + x1,16 + x1,17 + x1,18 = 1

x2,1 + x2,2 + x2,3 + x2,4 + x2,5 + x2,6 + x2,7 + x2,8 + x2,9 + x2,10 + x2,11 + x2,12 + x2,13 +

x2,14 + x2,15 + x2,16 + x2,17 + x2,18 = 1

45

x3,1 + x3,2 + x3,3 + x3,4 + x3,5 + x3,6 + x3,7 + x3,8 + x3,9 + x3,10 + x3,11 + x3,12 + x3,13 +

x3,14 + x3,15 + x3,16 + x3,17 + x3,18 = 1

x4,1 + x4,2 + x4,3 + x4,4 + x4,5 + x4,6 + x4,7 + x4,8 + x4,9 + x4,10 + x4,11 + x4,12 + x4,13 +

x4,14 + x4,15 + x4,16 + x4,17 + x4,18 = 1

x5,1 + x5,2 + x5,3 + x5,4 + x5,5 + x5,6 + x5,7 + x5,8 + x5,9 + x5,10 + x5,11 + x5,12 + x5,13 +

x5,14 + x5,15 + x5,16 + x5,17 + x5,18 = 1

x6,1 + x6,2 + x6,3 + x6,4 + x6,5 + x6,6 + x6,7 + x6,8 + x6,9 + x6,10 + x6,11 + x6,12 + x6,13 +

x6,14 + x6,15 + x6,16 + x6,17 + x6,18 = 1

x7,1 + x7,2 + x7,3 + x7,4 + x7,5 + x7,6 + x7,7 + x7,8 + x7,9 + x7,10 + x7,11 + x7,12 + x7,13 +

x7,14 + x7,15 + x7,16 + x7,17 + x7,18 = 1

x8,1 + x8,2 + x8,3 + x8,4 + x8,5 + x8,6 + x8,7 + x8,8 + x8,9 + x8,10 + x8,11 + x8,12 + x8,13 +

x8,14 + x8,15 + x8,16 + x8,17 + x8,18 = 1

x9,1 + x9,2 + x9,3 + x9,4 + x9,5 + x9,6 + x9,7 + x9,8 + x9,9 + x9,10 + x9,11 + x9,12 + x9,13 +

x9,14 + x9,15 + x9,16 + x9,17 + x9,18 = 1

x10,1 + x10,2 + x10,3 + x10,4 + x10,5 + x10,6 + x10,7 + x10,8 + x10,9 + x10,10 + x10,11 + x10,12 +

x10,13 + x10,14 + x10,15 + x10,16 + x10,17 + x10,18 = 1

x11,1 + x11,2 + x11,3 + x11,4 + x11,5 + x11,6 + x11,7 + x11,8 + x11,9 + x11,10 + x11,11 + x11,12 +

x1,13 + x11,14 + x11,15 + x11,16 + x11,17 + x11,18 = 1

x12,1 + x12,2 + x12,3 + x12,4 + x12,5 + x12,6 + x12,7 + x12,8 + x12,9 + x12,10 + x12,11 + x12,12 +

x1,13 + x12,14 + x12,15 + x12,16 + x12,17 + x12,18 = 1

x13,1 + x13,2 + x13,3 + x13,4 + x13,5 + x13,6 + x13,7 + x13,8 + x13,9 + x13,10 + x13,11 + x13,12 +

x13,13 + x13,14 + x13,15 + x13,16 + x13,17 + x13,18 = 1

x14,1 + x14,2 + x14,3 + x14,4 + x14,5 + x14,6 + x14,7 + x14,8 + x14,9 + x14,10 + x14,11 + x14,12 +

x14,13 + x14,14 + x14,15 + x14,16 + x14,17 + x14,18 = 1

x15,1 + x15,2 + x15,3 + x15,4 + x15,5 + x15,6 + x15,7 + x15,8 + x15,9 + x15,10 + x15,11 + x15,12 +

x15,13 + x15,14 + x15,15 + x15,16 + x15,17 + x15,18 = 1

x16,1 + x16,2 + x16,3 + x16,4 + x16,5 + x16,6 + x16,7 + x16,8 + x16,9 + x16,10 + x16,11 + x16,12 +

x16,13 + x16,14 + x16,15 + x16,16 + x16,17 + x16,18 = 1

x17,1 + x17,2 + x17,3 + x17,4 + x17,5 + x17,6 + x17,7 + x17,8 + x17,9 + x17,10 + x17,11 + x17,12 +

x17,13 + x17,14 + x17,15 + x17,16 + x17,17 + x17,18 = 1

x18,1 + x18,2 + x18,3 + x18,4 + x18,5 + x18,6 + x18,7 + x18,8 + x18,9 + x18,10 + x18,11 + x18,12 +

x18,13 + x18,14 + x18,15 + x18,16 + x18,17 + x18,18 = 1

x1,1 + x2,1 + x3,1 + x4,1 + x5,1 + x6,1 + x7,1 + x8,1 + x9,1 + x10,1 + x11,1 + x12,1 + x13,1 +

x14,1 + x15,1 + x16,1 + x17,1 + x18,1 = 1

x1,2 + x2,2 + x3,2 + x4,2 + x5,2 + x6,2 + x7,2 + x8,2 + x9,2 + x10,2 + x11,2 + x12,2 + x13,2 +

x14,2 + x15,2 + x16,2 + x17,2 + x18,2 = 1

x1,3 + x2,3 + x3,3 + x4,3 + x5,3 + x6,3 + x7,3 + x8,3 + x9,3 + x10,3 + x11,3 + x12,3 + x13,3 +

x14,3 + x15,3 + x16,3 + x17,3 + x18,3 = 1

x1,4 + x2,4 + x3,4 + x4,4 + x5,4 + x6,4 + x7,4 + x8,4 + x9,4 + x10,4 + x11,4 + x12,4 + x13,4 +

x14,4 + x15,4 + x16,4 + x17,4 + x18,4 = 1

x1,5 + x2,5 + x3,5 + x4,5 + x5,5 + x6,5 + x7,5 + x8,5 + x9,5 + x10,5 + x11,5 + x12,5 + x13,5 +

x14,5 + x15,5 + x16,5 + x17,5 + x18,5 = 1

x1,6 + x2,6 + x3,6 + x4,6 + x5,6 + x6,6 + x7,6 + x8,6 + x9,6 + x10,6 + x11,6 + x12,6 + x13,6 +

x14,6 + x15,6 + x16,6 + x17,6 + x18,6 = 1

x1,7 + x2,7 + x3,7 + x4,7 + x5,7 + x6,7 + x7,7 + x8,7 + x9,7 + x10,7 + x11,7 + x12,7 + x13,7 +

x14,7 + x15,7 + x16,7 + x17,7 + x18,7 = 1

x1,8 + x2,8 + x3,8 + x4,8 + x5,8 + x6,8 + x7,8 + x8,8 + x9,8 + x10,8 + x11,8 + x12,8 + x13,8 +

x14,8 + x15,8 + x16,8 + x17,8 + x18,8 = 1

x1,9 + x2,9 + x3,9 + x4,9 + x5,9 + x6,9 + x7,9 + x8,9 + x9,9 + x10,9 + x11,9 + x12,9 + x13,9 +

x14,9 + x15,9 + x16,9 + x17,9 + x18,9 = 1

x1,10 + x2,10 + x3,10 + x4,10 + x5,10 + x6,10 + x7,10 + x8,10 + x9,10 + x10,10 + x11,10 + x12,10 +

x13,10 + x14,10 + x15,10 + x16,10 + x17,10 + x18,10 = 1

x1,11 + x2,11 + x3,11 + x4,11 + x5,11 + x6,11 + x7,11 + x8,11 + x9,11 + x10,11 + x11,11 + x12,11 +

x13,11 + x14,11 + x15,11 + x16,11 + x17,11 + x18,11 = 1

x1,12 + x2,12 + x3,12 + x4,12 + x5,12 + x6,12 + x7,12 + x8,12 + x9,12 + x10,12 + x11,12 + x12,12 +

x13,12 + x14,12 + x15,12 + x16,12 + x17,12 + x18,12 = 1

46

x1,13 + x2,13 + x3,13 + x4,13 + x5,13 + x6,13 + x7,13 + x8,13 + x9,13 + x10,13 + x11,13 + x12,13 +

x13,13 + x14,13 + x15,13 + x16,13 + x17,13 + x18,13 = 1

x1,14 + x2,14 + x3,14 + x4,14 + x5,14 + x6,14 + x7,14 + x8,14 + x9,14 + x10,14 + x11,14 + x12,14 +

x13,14 + x14,14 + x15,14 + x16,14 + x17,14 + x18,14 = 1

x1,15 + x2,15 + x3,15 + x4,15 + x5,15 + x6,15 + x7,15 + x8,15 + x9,15 + x10,15 + x11,15 + x12,15 +

x13,15 + x14,15 + x15,15 + x16,15 + x17,15 + x18,15 = 1

x1,16 + x2,16 + x3,16 + x4,16 + x5,16 + x6,16 + x7,16 + x8,16 + x9,16 + x10,16 + x11,16 + x12,16 +

x13,16 + x14,16 + x15,16 + x16,16 + x17,16 + x18,16 = 1

x1,17 + x2,17 + x3,17 + x4,17 + x5,17 + x6,17 + x7,17 + x8,17 + x9,17 + x10,17 + x11,17 + x12,17 +

x13,17 + x14,17 + x15,17 + x16,17 + x17,17 + x18,17 = 1

x1,18 + x2,18 + x3,18 + x4,18 + x5,18 + x6,18 + x7,18 + x8,18 + x9,18 + x10,18 + x11,18 + x12,18 +

x13,18 + x14,18 + x15,18 + x16,18 + x17,18 + x18,18 = 1

x1,1 + x1,2 + x1,3 + x1,4 + x1,5 + x1,6 + x1,7 + x1,8 + x1,9 + x1,10 + x1,11 + x1,12 + x1,13 +

x1,14 + x1,15 + x1,16 + x1,17 + x1,18 = 1

x2,1 + x2,2 + x2,3 + x2,4 + x2,5 + x2,6 + x2,7 + x2,8 + x2,9 + x2,10 + x2,11 + x2,12 + x2,13 +

x2,14 + x2,15 + x2,16 + x2,17 + x2,18 = 1

x3,1 + x3,2 + x3,3 + x3,4 + x3,5 + x3,6 + x3,7 + x3,8 + x3,9 + x3,10 + x3,11 + x3,12 + x3,13 +

x3,14 + x3,15 + x3,16 + x3,17 + x3,18 = 1

x4,1 + x4,2 + x4,3 + x4,4 + x4,5 + x4,6 + x4,7 + x4,8 + x4,9 + x4,10 + x4,11 + x4,12 + x4,13 +

x4,14 + x4,15 + x4,16 + x4,17 + x4,18 = 1

x5,1 + x5,2 + x5,3 + x5,4 + x5,5 + x5,6 + x5,7 + x5,8 + x5,9 + x5,10 + x5,11 + x5,12 + x5,13 +

x5,14 + x5,15 + x5,16 + x5,17 + x5,18 = 1

x6,1 + x6,2 + x6,3 + x6,4 + x6,5 + x6,6 + x6,7 + x6,8 + x6,9 + x6,10 + x6,11 + x6,12 + x6,13 +

x6,14 + x6,15 + x6,16 + x6,17 + x6,18 = 1

x7,1 + x7,2 + x7,3 + x7,4 + x7,5 + x7,6 + x7,7 + x7,8 + x7,9 + x7,10 + x7,11 + x7,12 + x7,13 +

x7,14 + x7,15 + x7,16 + x7,17 + x7,18 = 1

x8,1 + x8,2 + x8,3 + x8,4 + x8,5 + x8,6 + x8,7 + x8,8 + x8,9 + x8,10 + x8,11 + x8,12 + x8,13 +

x8,14 + x8,15 + x8,16 + x8,17 + x8,18 = 1

x9,1 + x9,2 + x9,3 + x9,4 + x9,5 + x9,6 + x9,7 + x9,8 + x9,9 + x9,10 + x9,11 + x9,12 + x9,13 +

x9,14 + x9,15 + x9,16 + x9,17 + x9,18 = 1

x10,1 + x10,2 + x10,3 + x10,4 + x10,5 + x10,6 + x10,7 + x10,8 + x10,9 + x10,10 + x10,11 + x10,12 +

x10,13 + x10,14 + x10,15 + x10,16 + x10,17 + x10,18 = 1

x11,1 + x11,2 + x11,3 + x11,4 + x11,5 + x11,6 + x11,7 + x11,8 + x11,9 + x11,10 + x11,11 + x11,12 +

x1,13 + x11,14 + x11,15 + x11,16 + x11,17 + x11,18 = 1

x12,1 + x12,2 + x12,3 + x12,4 + x12,5 + x12,6 + x12,7 + x12,8 + x12,9 + x12,10 + x12,11 + x12,12 +

x1,13 + x12,14 + x12,15 + x12,16 + x12,17 + x12,18 = 1

x13,1 + x13,2 + x13,3 + x13,4 + x13,5 + x13,6 + x13,7 + x13,8 + x13,9 + x13,10 + x13,11 + x13,12 +

x13,13 + x13,14 + x13,15 + x13,16 + x13,17 + x13,18 = 1

x14,1 + x14,2 + x14,3 + x14,4 + x14,5 + x14,6 + x14,7 + x14,8 + x14,9 + x14,10 + x14,11 + x14,12 +

x14,13 + x14,14 + x14,15 + x14,16 + x14,17 + x14,18 = 1

x15,1 + x15,2 + x15,3 + x15,4 + x15,5 + x15,6 + x15,7 + x15,8 + x15,9 + x15,10 + x15,11 + x15,12 +

x15,13 + x15,14 + x15,15 + x15,16 + x15,17 + x15,18 = 1

x16,1 + x16,2 + x16,3 + x16,4 + x16,5 + x16,6 + x16,7 + x16,8 + x16,9 + x16,10 + x16,11 + x16,12 +

x16,13 + x16,14 + x16,15 + x16,16 + x16,17 + x16,18 = 1

x17,1 + x17,2 + x17,3 + x17,4 + x17,5 + x17,6 + x17,7 + x17,8 + x17,9 + x17,10 + x17,11 + x17,12 +

x17,13 + x17,14 + x17,15 + x17,16 + x17,17 + x17,18 = 1

x18,1 + x18,2 + x18,3 + x18,4 + x18,5 + x18,6 + x18,7 + x18,8 + x18,9 + x18,10 + x18,11 + x18,12 +

x18,13 + x18,14 + x18,15 + x18,16 + x18,17 + x18,18 = 1

47

Using program IPsolve to solve this pattern the result show in figure 3.43.

Figure 3.43 The result of capacitor placement for pattern 39.6Mvar

After calculation, the location of capacitor placement is shown below.

Figure 3.44 Designing the location of pattern 39.6Mvar

From the result, we can placed the capacitors which x[i,j] are capacitors number i and

location j.

Figure 3.45 The number and location of capacitors pattern 39.6Mvar

b

13

14

15

16

17

18

1

7

2

8

3

9

4

10

5

11

6

12

b

x14,13

x11,14

x15,15

x17,16

x18,17

x9,18

x2,1

x5,7

x8,2

x6,8

x13,3

x1,9

x4,4

x3,10

x16,5

x10,11

x12,6

x7,12

48

When the capacitors placed, the result show in the figure 3.46.

Figure 3.46 The result of ILP to solving the pattern 39.6Mvar

Finally, calculation to find the capacitances of each groups the result as follows.

1

2

3

1C = =26.6355 uF

1 1+

25.2487+27.6251 27.4489+26.2254

1C = =26.5677 uF

1 1+

24.5542+28.1523 25.1258+28.4456

1C = =26.5616 uF

1 1+

27.7512+24.9457 26.5582+26.9984

4

5

6

1C = =13.7963 uF

1 1+

26.8879 28.3354

1C = =13.7164 uF

1 1+

29.4584 25.6678

1C = =13.7270 uF

1 1+

29.2245 25.8856

Calculation to find the current unbalance,

The impedance of each phase each side it can calculate as follows,

3

3

1

1

2

2

1 1PhaseA,SideA; xct = = =119.5058Ω

2π50C 2×π×50×26.2254

1 1PhaseB,SideA; xct = = =119.8108Ω

2π50C 2×π×50×28.4456

1 1PhaseC,SideA; xct = = =119.8382Ω

2π50C 2×π×50×26.5616

C1 C2 C3 C4 C5 C6 b

26.8879uF

28.3354uF

29.4584uF

25.6678uF

29.2245uF

25.8856uF

25.2487uF

27.4489uF

27.6251uF

26.2254uF

24.5542uF

25.1258uF

28.1523uF

28.4456uF

27.7512uF

26.5582uF

24.9457uF

26.9984uF

49

4

4

5

5

6

6

1 1PhaseA,SideB; xct = = =230.7205Ω

2π50C 2×π×50×13.7963


2π50C 2×π×50×13.7164


2π50C 2×π×50×13.7270

Next, calculation to find the current of each phases each side.

1

1

2

2

3

3

115000I = =962.2965A

xct

115000I = =959.8468A

xct

115000I = =959.6272A

xct

,

4

5

4

5

6

6

115000I = =498.4385A

xct

115000I = =495.5500A

xct

115000I = =495.9317A

xct

Where;

Cos0 = 1

Cos120 = -0.5

Cos240 = -0.5

,

Sin0 = 0

Sin120 = 0.866

Sin240 = -0.866

AAc 1

BAc 2

CAc 3

I I cos(0) =962.2965A

I I cos(120)=-479.9234A

I I cos(240)=-479.8136A

=

=

=

, AAs 1

BAs 2

CAs 3

I I sin(0) =0A

I I sin(120)=831.2517A

I I sin(240)=-831.0615A

=

=

=

ABc 4

BBc 5

CBc 6

I I cos(0) =498.4385A

I I cos(120)=-247.7750A

I I cos(240)=-250.6635A

=

=

=

, ABs 4

BBs 5

CBs 6

I I sin(0) =0A

I I sin(120)=429.1589A

I I sin(240)=-429.4894A

=

=

=

AAc BAc CAc

AAs BAs CAs

ABc BBc CBc

ABs BBs CBs

A

A

B

B

sum(I c)

sum(I s)

sum(I c)

sum(I s)

I I I I =2.5595A

I I I I =0.1902A

I I I I =2.6977A

I I I I =-0.3306A

= + +

= + +

= + +

= + +

The current of each side A and side B

a

b

BA

BA

sum(I c) sum(I c)

sum(I s) sum(I s)

I =I I =2.5595-2.6977=-0.1382A

I =I I =0.1902-(-0.3306)=0.5207A

-

-

50

Finally, the result of current unbalance is;

2 2 2 2

unbalance a b

unbalance

I I I (-0.1382) +(0.5207)

I 540mA

= + =

= (3.21)

Using EGAT algorithm to the capacitors placement as follows,

Firstly, rearrange the number of capacitance to Min-Max values

Table 3.6 The capacitance arrangement Min-Max value for pattern 39.6Mvar

Min-Max Min-Max

24.5542 26.8879

24.9457 26.9984

25.1258 27.4489

25.2487 27.7512

25.6678 28.1523

25.8856 28.3354

26.2254 28.4456

26.5582 29.2245

26.8879 29.4584

Secondly, arrangement all the numbers from left to right and right to left.

Figure 3.47 The result of capacitors placement by using the EGAT algorithm for

pattern 39.6Mvar

Finally, calculation to find the current unbalance the result is 5.6190A.Therefore, the

result of current unbalance by using ILP algorithm better than EGAT algorithm.

3.8 The graphic user interface

In part of communication with Android has a graphic user interface (GUI) show in figure

3.48 which this figure show the default screen for selection mode to placement the

capacitors bank. For the measurement mode show in the figure 3.49 which user can enter

data such as job number, substation, capacitor serial number, alias and the user can

command device for read the capacitance value, voltage, current to send those data to

Tablet with Protocol HTTP. In the figure 3.50 and 3.51 are example when user use the

measurement mode. The figure 3.52 and 3.53 are example when user use the searching

C1 C2 C3 C4 C5 C6 b

26.2254uF

27.6251uF

26.5582uF

27.4489uF

26.8879uF

26.9984uf

24.5542uF

27.7512uF

25.8856uF

29.4584uF

24.9457uF

28.1523uF

25.6678uF

29.2245uF

25.1258uF

28.3354uF

25.4587uF

28.4456uF

51

mode for search details about each substations as the user recorded. In part of capacitor

placement, users have to select the pattern of capacitor placement that can choose the

database for record data shown in figure 3.54. In part of the result after placement the

capacitor bank that show the number and location of capacitors should placement shown

in figure 3.55 and 3.56.

Figure 3.48 Default screen of GUI

The graphic user interface consist of three part; first part is capacitor measurement which

the user can command device to read data and send those data to Tablet with protocol

HTTP shown in the figure 3.48.

Figure 3.49 The GUI of capacitor measurement

The data that is necessary to enter such as job number, substation, and level voltage that

are used a reference for the task. Rated, Capacitor Serial No and Alias are the information

a reference for the capacitor shown in figure 3.49.

52

Figure 3.50 The GUI of specify for substation details

The user can pushing the start measuring button for read data from device to display on

GUI.

Figure 3.51 The GUI of display voltage, current and capacitance

If user would like to use the values their user can pushing “Add capacitor” button for

record those data in to this application.

Second past is searching mode, the user can enter job number to find the detail of each

substations shown in the figure 3.52.

53

Figure 3.52 The GUI of searching mode

If the user would like to search some information about egat, their user can enter egat in

“Search by Job Number”. The result will be shown the job number only name egat show

the example in figure 3.53.

Figure 3.53 The example to use searching mode

Third part is installation mode, the user can choosing the pattern that want to placement the

capacitor bank.

54

Figure 3.54 The GUI of Installation mode

After use the installation mode and selection the pattern of configuration, the result will be

shown about number and location of each capacitors should be placed.

Figure 3.55 The result of capacitor placement Phase A Side A

The user can using the slide function picture for change to new pictures shown in the figure

3.56.

55

.

Figure 3.56 The result of capacitor placement Phase A Side B

56

CHAPTER 4

RESULTS AND DISCUSSIONS

In this chapter, the results will be separated in five parts; first part is the result of band

pass filter for rejection harmonic noises second part is the result when using the moving

average filter third part is the calibrations result to find the equation of voltage and current

sensors forth part is the result of temperature compensate and the last part is the

experimental result of comparison voltage, current, and capacitance value between

capacitance instrument and digital multimeter.

4.1 Band pass filter for rejection harmonic noises results

In the figure 4.1 show the results of band pass filter circuit when testing AC input signals

at frequency 50Hz namely the starting time of output signal is slower than input signal

about 5ms wherewith using more components in band pass filter such as resistors, and

capacitors, op-amps. Those components always using the time to process. The output

signal is similarly the input signal but, the amplitude of output signal less than the input

signal about 18 mV when the input signal estimate 226mV.

Figure 4.1 The real output signal of band pass filter at frequency 50Hz

In the figures 4.2, 4.3, and 4.4 show the results of the band pass filter when mix frequency

AC inputs signal between 50Hz with 150Hz, 50Hz with 250Hz, 50Hz with 350Hz

respectively. The band pass filter can rejection the harmonic noises and it is still maintain

the quality of the signal.

Channel 2

“Output”

Channel 1

“Input”

57

Figure 4.2 The real output signal of band pass filter mixed-frequency AC input

signals at 50Hz with 150Hz





Channel 2

“Output”

Channel 1

“Input”

Channel 2

“Output”

Channel 1

“Input”

Channel 2

“Output”

Channel 1

“Input”

58

4.2 Moving average filter results

The moving average filter can reducing the real noise while retaining a sharp step

response. Using the technique to record the data at the sampling time, these data of each

sampling time processed by moving average function

The formula of moving average filter show in the equation 4.1.

1

0

1[ ] [ ]

M

j

y i x i jM

(4.1)

The meaning parameters of the moving average filter. In equation 4.1,

x[] is the input signal

y[] is the output signal

M is the number of points used in the moving average

In this thesis uses the number of points in the moving average filter about 100 points.

For example in 5 points;

[78] [79] [80] [81] [82]

[80]5

x x x x xy

(4.2)

Figure 4.5 The real input and output signal of moving average filter in term of

opened circuit

“Output”

“Input”

Time

AD

C v

alu

e (1

0 b

its)

59

Figure 4.6 The real input and output signals of moving average filter in term of

closed circuit

In the figure 4.5 and 4.6 show the results when using the moving average filter to filter

ADC signals. In this thesis used the discrete (Finite Impulse Response) FIR filter block in

Matlab Simulink and used the number of points of the moving average filter about 100

points and it always reduce noises and maintain quality of the signals. If the number of

points is higher than 100points, the signal results are delay because it take a long time to

process.

Figure 4.7 Equipment for calibration

The figure 4.7 show the equipment for calibration voltage and current sensors board which

used the OMICRON auto power supply from EGAT and used the digital multimeter to

measure the voltage and current as well.

“Output”

“Input”

Time

AD

C v

alu

e (1

0 b

its)

60

4.3 Calibrations results

4.3.1 Finding the equation for calibration of voltage at temperature 28Co

Figure 4.8 The chart of voltage trend line in linear function

In the figure 4.8 show the chart of voltage trend line in linear function when we measured

the AC voltage compare with data on capacitance instrument and use the excel program to

solve to find linear equation show in equation (4.3) and R-squared value show in equation

(4.4).

(4.3)

(4.4)

Figure 4.9 The chart of voltage trend line in polynomial function

In the figure 4.9 show the chart when we measure the AC voltage compare with data on

capacitance instrument and use the excel program to solve to find polynomial equation

show in equation (4.5) and R-squared value show in equation (4.6).

(4.5)

(4.6)

y = 483.3288x + 32.0590R² = 0.9999

205

210

215

220

225

230

235

240

245

0.36 0.37 0.38 0.39 0.4 0.41 0.42 0.43 0.44

AC

volt

ag

e (V

AC

)

Data from u-controller in 10bits

y = -322.0338x2 + 740.7178x - 19.2677

R² = 1.0000

205

210

215

220

225

230

235

240

245

0.36 0.37 0.38 0.39 0.4 0.41 0.42 0.43 0.44

AC

volt

ag

e (V

AC

)


2

2

322.0338 740.7178 19.2677

1.00000

y x x

R

2

483.3288 32.0590

0.9999

y x

R

61

4.3.2 Finding the equation for calibration of current at temperature 28Co

Figure 4.10 The chart of current trend line in linear function

The figure 4.10 show the chart compare the current value between data from digital

multimeter and capacitance instrument. The linear function and R-squared show in equation

(4.7) and (4.8) respectively.

(4.7)

(4.8)

Figure 4.11 The chart of current trend line in polynomial function

In the figure 4.11 show the chart compare the current value between data from digital

multimeter and capacitance instrument. The polynomial function and R-squared show in

equation (4.9) and (4.10) respectively.

(4.9)

(4.10)

y = 6.3058x - 0.0147R² = 0.9999

0

0.5

1

1.5

2

2.5

3

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

AC

Cu

rren

t (

A)


y = -0.2511x2 + 6.4108x - 0.0226

R² = 0.9999

0

0.5

1

1.5

2

2.5

3

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

AC

Cu

rren

t (

A)


2

6.3058 0.0147

0.9999

y x

R

2

2

0.2511 6.4108 0.0226

0.9999

y x x

R

62

4.4 Temperature compensation results

The problem of temperature effect on electronics components that it lead to low accuracy

on voltage and current measurement show in the figure 4.12.

Figure 4.12 Comparison between AC voltage from Digital multimeter and AC

voltage sensor

In the figure 4.12 show the problem of temperature effect when comparison between AC

voltage from Digital multimeter and AC voltage sensor. In this thesis, we calibrate the

circuit at temperature 28 Co. The results have approximate to AC digital multimeter but,

the temperature are increasing the results have a tendency increasing as well.

4.4.1 Temperature compensation result of voltage measurement

Figure 4.13 Temperature curve of the AC input voltage about 200VAC

In addition, this thesis use the temperature sensor to help compensation the error between

the standard measurement and capacitance instrument. The temperatures have

approximate to exponential curve when increasing the temperature up to 65Coshow in the

figure 4.13.

194

196

198

200

202

204

206

208

210

27

.92

8.0

28

.12

8.2

28

.52

8.8

29

.73

1.4

32

.03

2.3

32

.33

2.9

33

.03

3.6

34

.73

5.7

36

.73

7.3

38

.03

9.1

39

.94

1.0

42

.04

3.1

44

.64

7.9

49

.65

1.1

53

.45

5.9

58

.76

1.9

AC

vo

lta

ge

Temperature Co

Volt_Meter

Volt_u-Controller

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

2 5 7 91

21

41

61

92

12

42

62

83

13

33

53

84

04

24

54

74

95

25

45

65

96

16

36

66

87

17

37

57

88

0

Tem

per

atu

re C

o

Time (min)

63

Figure 4.14 Temperature curve of the AC input voltage about 200VAC

In the figure 4.14 show the graph of the error between AC voltage from digital multimeter

and capacitance instrument tested at 220VAC that the error have a tendency increase

when the temperature are increasing. On the other hand, the error are increasing at

temperature 28.5 Co but, the error become to zero at temperature between 27 Co – 28Co.

Plot the curve by using the polynomial function in two degree show in the equation 4.11.

20.0036 0.1526 1.4658y x x (4.11)

Using the equation 4.11 to compensate the error cause by temperature, the result show in

the figure 4.15.

Figure 4.15 Comparison between AC voltage from Digital multimeter and AC

voltage sensor before/after using temperature compensation

y = 0.0036x2 - 0.1526x + 1.4658

-1

0

1

2

3

4

5

6

7

8

9

0 10 20 30 40 50 60 70 80

Volt

ag

e er

ror

(Vac)

Temperature Co

194

196

198

200

202

204

206

208

210

27

.92

8.0

28

.12

8.3

28

.62

9.2

30

.53

2.0

32

.33

2.2

32

.83

3.1

33

.73

5.3

36

.33

7.0

37

.83

8.7

39

.84

1.0

42

.14

3.4

45

.64

8.4

50

.35

2.4

55

.15

8.2

61

.7

AC

vo

lta

ge

Temperature Co

Volt_Meter

Voltage before comp.

Voltage after comp.

64

In the figure 4.15 show the result of AC voltage when comparison between standard

measurement and capacitance instrument before/after using temperature compensation.

The result of temperature compensation has the value approximate the value of standard

measurement when comparison the old value before using the temperature compensation

technique.

4.4.2 Temperature compensation result of current measurement

Figure 4.16 Temperature curve of the AC input current about 1.9A

In the figure 4.16 show the graph of the error between AC current from digital multimeter

and capacitance instrument tested at 1.9A that the errors have a tendency when the

temperature are increasing. On the other hand, the error are increasing at temperature 31

Co but, the error become to zero at temperature between 28 Co –30Co. Plot the curve by

using the polynomial function in two degree show in the equation 4.12.

29 05 0.0052 0.075y E x x (4.12)

Using the equation 4.12 to compensate the error cause by temperature, the result show in

the figure 4.17.

y = 9E-05x2 - 0.0052x + 0.075

-0.005

0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.0 10.0 20.0 30.0 40.0 50.0 60.0

Cu

rren

t er

ror

(A)

Temperature Co

65

Figure 4.17 Comparison between AC current from Digital multimeter and AC

current sensor before/after using temperature compensation

On above figure show the result of AC current when comparison between standard

measurement and capacitance instrument before/after using temperature compensation.

The result of temperature compensation has the value approximate the value of standard

measurement when comparison the old value before using the temperature compensation

technique. In the temperature effect on the current sensor, the current sensor is very

sensitive to temperature effect such as when the temperature increase suddenly in short

time, the current sensor are fluctuation let show at the temperature 32.9Co.

4.5 Experimental results

This chapter illustrates some of achieved results when we test the sensors circuit board,

Analog to conversion board, and Microcontroller board with real capacitor bank from

EGAT.

Figure 4.18 Testing all system to measure the capacitor bank

1.86

1.88

1.9

1.92

1.94

1.96

1.98

28

.22

8.7

29

.12

9.6

30

.03

0.4

30

.83

1.1

31

.43

1.7

31

.93

3.7

34

.03

4.2

34

.53

5.0

35

.43

6.1

36

.93

7.5

38

.74

0.0

41

.44

3.2

45

.34

8.0

51

.45

5.9

62

.7

Cu

rren

t (A

)

Temperature Co

Current after Comp.

Current before comp.

Amp Meter

66

4.5.1 Comparison of the voltage values between digital multimeter and

voltage sensor

Table 4.1 The result of voltage values

Devices

Numbers

Digital

multimeter (V)

Voltage sensor

(V)

Error (V)

1 210.1 210.15 0.024

2 210.9 211.03 0.062

3 212.1 212.19 0.042

4 212.9 213.01 0.052

5 214.2 214.33 0.061

6 215.2 215.21 0.005

7 216.1 216.15 0.023

8 217.5 217.58 0.037

9 218.2 218.26 0.027

10 219.0 219.06 0.027

11 219.9 219.94 0.018

12 221.3 221.37 0.032

13 222.0 222.07 0.032

14 223.1 223.07 -0.013

15 224.5 224.49 -0.004

16 225.3 225.31 0.004

17 225.8 225.95 0.066

18 227.2 227.07 -0.057

19 228.5 228.32 -0.079

Average error 0.019 Vac

The figure 4.18 show the result of AC voltage values when comparison between digital

multimeter and capacitance instrument which those values use the equation 3.3 to calculate.

the average error of voltage sensor about 0.019Vac show in the table 4.1

Figure 4.19 The chart of voltage values

205

210

215

220

225

230

0 5 10 15 20

Vo

lga

te (V

ac)

Number of tesing points

Digital multimeter Voltage sensor

67

4.5.2 Comparison of the current values between digital multimeter and

voltage sensor

Table 4.2 The result of current values

Devices

Numbers

Digital

multimeter (A)

Current sensor

(A)

Error

1 1.878 1.878 0.000

2 1.885 1.886 0.053

3 1.896 1.897 0.053

4 1.903 1.904 0.053

5 1.913 1.914 0.052

6 1.921 1.921 0.000

7 1.929 1.93 0.052

8 1.941 1.943 0.103

9 1.946 1.948 0.103

10 1.952 1.954 0.102

11 1.959 1.961 0.102

12 1.971 1.973 0.101

13 1.977 1.979 0.101

14 1.986 1.988 0.101

15 1.998 2.001 0.150

16 2.006 2.008 0.100

17 2.011 2.014 0.149

18 2.023 2.026 0.148

19 2.033 2.035 0.098

Average error 0.085A

The figure 4.19 show the result of AC current values compare between digital multimeter

and capacitance instrument which those values use the equation 3.3 to calculate. The

average error of current sensor about 0.085A show in the table 4.3

Figure 4.20 The chart of current values

The figure 4.20 show the result of current values when compare between digital multimeter

and capacitance instrument.

1.86

1.88

1.9

1.92

1.94

1.96

1.98

2

2.02

2.04

2.06

0 5 10 15 20

Cu

rren

t (A

)

Number of testing points

Digital multimeter Current sensor

68

4.5.3 Comparison of the voltage values between digital multimeter

and voltage sensor

Table 4.3 The result of capacitance values

Devices

Numbers

Digital multimeter

(uF)

Capacitance

instrument (uF) Error

1 28.446 28.4525 -0.024

2 28.448 28.4502 -0.009

3 28.457 28.4543 0.010

4 28.452 28.4520 0.001

5 28.426 28.4280 -0.008

6 28.413 28.4142 -0.005

7 28.422 28.4137 0.029

8 28.425 28.4064 0.066

9 28.410 28.3882 0.075

10 28.393 28.3717 0.075

11 28.381 28.3569 0.084

12 28.370 28.3502 0.070

13 28.367 28.3468 0.070

14 28.368 28.3354 0.114

15 28.373 28.3289 0.155

16 28.368 28.3413 0.095

17 28.372 28.3490 0.083

18 28.401 28.3425 0.206

19 28.371 28.3205 0.177

Average error 0.067uF

Figure 4.21 The chart of capacitance values

In the table4.3 and figure 4.21 show the result of capacitance values which those value

calculate from voltage and current that measure from digital multimeter and capacitance

instrument by using the equation 3.2 and 3.3. The capacitance values measured from

capacitance instrument are greater than the values from digital multimeter because the

effect of current sensors. The average error of capacitance instrument about 0.067uF.

28.3000

28.3200

28.3400

28.3600

28.3800

28.4000

28.4200

28.4400

28.4600

28.4800

0 5 10 15 20

Ca

pa

cita

nce

(u

F)

Number of testing points

Digital multimeter Capacitance instrument

69

CHAPTER 5

CONCLUSION AND FULTURE WORK

5.1 Conclusions

The challenge of the capacitance instrument consist of two main challenges. One

challenge of the capacitance instrument is to be measured the capacitor banks in high

voltage which it can be measured the AC voltage and the AC current in high resolution and high accuracy. Morover, it can be used in the area which contains a lot of harmonic

noises and high temperature. There are many techniques to design the circuit to measure

the voltage, current, capacitance, and rejection the harmornic noises. In this thesis, the

components of capacitance instrument board are used the high precision and high

resolution such as the resistors have the tolerance about 0.01%, the capacitors have the

tolerance about 5%. Another challenge of the capacitance instrument is to be found the

optimal value of the current unbalance for using the capacitors bank placement’s

equipment. The instrument can be recorded the value such as voltage, current, and

capacitance value. Those data will be recorded in to the tablet for processing the capacitor

banks placement equipment of the EGAT in order to find the optimal solution to place

the capacitor banks of each patterns sush as the pattern of capacitor banks 115Kv-

24Mvar-66units, 115Kv-39.6Mvar-99units,and 115Kv-52.8Kv-132units. These patterns

of the capacitor banks placement connect the capacitors to complex circuits.

Designing of voltage measurement board consist of .6 steps. The first step is using the

stepdown transformer to reduce high voltage to low voltage. The second step is using the

voltage divider circuit to reduce voltage to low voltage depend on limiting of input op-

amp. The third step is using the bandpass filter to reject the harmonic noises. The forth

step is using the RMS to DC circuit to convet the AC voltage to DC voltage. The next

step is using the amplifier circuit to amplify the voltage which it depend on the input of

ADC circuit. The last step is using the ADC circuit for convert the analog signal to digital

signal before send these to microcontroller.

Desining of the current measurement board consist of 5 steps. The first step is using the

Hall effect current sensor circuit for measurement the current. The second step is using

the bandpass filter to reject the harmonic noises. The third step is using the RMS to DC

circuit to convet the AC voltage to DC voltage. The next step is using the amplifier circuit

to amplify the voltage which it depend on the input of ADC circuit. The last step is using

the ADC circuit for convert the analog signal to digital signal before send these to

microcontroller.

There are two main problems when we mesured the capacitance in substations of the

EGAT.The one problem is the harmornic noise effect in power line as the result of using

more appliances such as welding machines, cutting machines, and electric grinding

machines. Another problem is the temperture effect on resolution and accuracy of voltage

and current sensors.

There are two solution to solve the problem of harmornic noises. The first solution is

using the banpass filter circuit to reject the harmornic noises. Another solution is using

70

the Voltage stabilizer or Inverter to supply the voltage to capacitor banks. The solution to

solve the ploblem of temperature is using the temperature compensation.

In conclusion, there are many problem to design the voltage and current measurement in

high resolution and high accuracy such as the problem of calibration sensors, the problem

of temperature compensation, and the problem of electronic noises. There are many

technique to design the instrument in high resolution and high accuracy. In this thesis,

One the the technique is selected the components of instrument in high precision. Second

techinque is using the high resolution of analog to digital converter. Next techinque is

using the moving average filter to reduce flicker of the data. Another technique is using

the temperature compesation. The capacitance instrument can be measured the capacitor

banks in high voltage and it can be measured the voltage and current in high resolution

but, the accuray still less than to the stardard instrument. In the capacitace placement, this

this use the Integer linear programming technique to solve the current unbalance of each

pattern of the EGAT, but this technique take a long time to find the optimal solution.

5.2 Future work

The capacitance instrument can be supported the engineers of the EGAT for measurement

the voltage, current, and capacitance in each substations and it can be reduced the time to

record those data in to the computer. Moreover, it can be solved the current unblance of

each patterns of the EGAT.

71

REFERENCES

[1] L.Medina (1954), Two Probe-type Capacitance Meters, Journal of the British

Institution of Radio Engineers, Vol. 1, pp. 233-236

[2] R.Gallorini, and N.Abouchi (2001), A Capacitance Meter based on an

Oversampling Sigma-Delta Modulator and Its Application to Capacitive

Sensor Interface, International Conference, Vol. 3, pp. 1537-1540.

[3] GENTEC Company, Capacitance Meter,[homepage on the Internet], Cannada.

Available from: http://www.gentec.ca

[4] K.Valipour, E.Dehghan, and M.H. Shariatkhah (2013), Optimal Placement of

Capacitor Banks and Distributed Generation for Losses Reduction and Voltage

THD Improvement in distribution Networks Based on BBO Algorithm , IRJABS,

vol. 4(7), pp. 1663-1670.

[5] Hblillah Bin Mohd hazim(2012), Optimal Placement of Capacitor Bank in

Distribution Network in the Presint of Harmonic, Master of Engineering,

University Technology of Malaysia,pp. 1-20.

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