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The First Integration Test of the ATLAS End-cap Muon Level 1 Trigger System. Introduction Overview of ATLAS End-cap Muon Level1 Trigger TGC electronics (Level1 Trigger + TGC Readout) Slice Test Setup Test Results Summary. Chikara Fukunaga Tokyo Metropolitan University - PowerPoint PPT Presentation
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The First Integration Test of the ATLASEnd-cap Muon Level 1 Trigger System
IntroductionOverview of ATLAS End-cap Muon Level1 TriggerTGC electronics (Level1 Trigger + TGC Readout)Slice Test SetupTest ResultsSummary
Chikara FukunagaTokyo Metropolitan University
On behalf of the ATLAS TGC electronics group
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Introduction
3 main ASICs out of total 7 have been made with full specifications. Stand-alone tests of ASICs have been finished.An overall integrated test has been required with all these ASICs in one test bed →Slice test (SLT) system.C++ based trigger simulation program has been needed and developed, and it could give the test patterns and answers to the SLT system.Integration test started in Sept.,’01, all the components have been installed in Aug.,’02.
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Overview of ATLAS End-cap Muon Level1 Trigger
M1M2 M3
Thin Gap Chamber (TGC)
1.05 η 2.70, z = ±14m
r (wire)- (strip) readout
Total 150 K channels for Trigger
Total 7 layers (M1,M2 and M3)
Low-pT Trigger, pT ≥ 6 GeV
M1(3) triplet: 2 out of 1, 1out of 2
M2(2) vs. M3(2) doublets: 3 out of 4
Hi-pT Trigger, pT ≥ 20 GeV
M1 vs. doublets (M2&M3)
Sector Logic (SL)
R- coincidence, Highest pT tracks
To Muon Central Trigger Proc. I/F
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TGC electronics (Level1 Trigger + TGC Readout)
M3
M2
M1
On detector part Off detector part
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Slice Test (SLT) Setup
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SLT Components I– PS Board & ASICs
SLB ASIC
0.35m
250K gates
Low-pT Trigger
Readout buffer
PP ASIC
0.6 → 0.35m
50K gates
Analog+digital
LVDSrx
Fine delay
Bunch Crossing ID
Trigger (Hi-pT)
Readout (SSW)
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SLT Components II - Hi-pT board & ASIC
LVDS inFrom PS board
G-link outTo SL
Hi-pT ASIC
0.35mm
80Kgates
Hi-pT trigger
Hitachi BGA
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SLT Components III – Readout System
LVDS inFrom PS board (SLB)
G-link outTo ROD
Star Switch (SSW)
Read Out Driver (ROD)
G-link inFrom SSW
FIFOSDRAM
CPU
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SLT Components IV – Software systemIntegrated control software based on the ATLAS online SW framework
SLT requires initialization and module/ASIC configuration at beginning
Run control for run start/stop Run Control GUI & Status Window
Configuration DataBase Editor Window
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SLT Results I – Trigger Part Logic
Verification of Trigger Logic (Simulation vs. HW)The same trigger hit patterns used for the simulation were inputted to PPG (pulse Pattern generators), and compared outputs of the SLT system with one of the simulation:
Generated Trigger Hit patterns, and comparison with the simulation
1 track (~20000) → No error found.
2 tracks (~20000) → No error found.
≥ 3 tracks (~15000) → No error found.
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SLT Results II - Trigger Latency
StageSLT
MeasurementRequired
upper limit
TGC, ASD 160 175
PP ASIC 43 50
SLB ASIC 49 75
LVDS Tx,Rx 83 75
Cable 15m 75 75
Hi-pT ASIC 55 75
G-link Tx,Rx 105 75
Cable (90m) 450 450
SL 160 175
Cable (5m) 25 25
Total 1205 1250
Latency Measurement =Actual Measurement(PS board, HiPT and SL) ANDCable length Estimation
1205ns (SLT) < 1250ns (RUL)
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SLT Results III – Readout test
Since SSW has been delivered in this summer, full test of PS-board→SSW→ROD has not been done.
PS-board→PT4(SSW alternative)→ROD has been checked in 2001 with long run tests.
400 clock counts (40MHz) can be used for SLB or SSW readout if Level 1 rate is 100KHz. SLB uses 218 counts. If TGC occupancy is 4%, SSW needs 160 counts. SSW will not be bottle neck. (TGC Occupancy ~ 1%)
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SLT Results - ROD
ROD (Read Out Buffer) has several problems.4 bytes access to internal bus takes 0.2s.SSW No hits = 4bytesSSW Hits = 40bytes If all 13 SSWs have no hits,
14s, if all hits, 30s.One ROD with 13 SSWs
can be done with 30~70KHz (< 100KHz).We need design modification.
ROD Structure
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Summary
Block Test Status
Trigger PartIntegration@40MHz Done, pattern check OK
Latency OK 1205s<1250s
Readout Part
Integration Not yet, stand-alone
Readout Rate SSW OK 100KHz
Readout Rate ROD 30~70KHz
SoftwareOnline DAQ OK, will be used for beam
Trigger Logic Simulation Need improvements
Control System HSC-CCI OK for config. ASIC