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The The GigaFitter GigaFitter for Fast Track Fitting for Fast Track Fitting based on based on FPGA DSP Arrays FPGA DSP Arrays Pierluigi Catastini Pierluigi Catastini (Universita (Universita di Siena - INFN Pisa) di Siena - INFN Pisa) For the SVT Collaboration For the SVT Collaboration

The GigaFitter for Fast Track Fitting based on FPGA DSP Arrays

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The The GigaFitter GigaFitter for Fast Track Fittingfor Fast Track Fittingbased onbased on

FPGA DSP Arrays FPGA DSP Arrays

Pierluigi CatastiniPierluigi Catastini(Universita(Universita’’ di Siena - INFN Pisa) di Siena - INFN Pisa)

For the SVT CollaborationFor the SVT Collaboration

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 22

SVT: A Success for CDFSVT: A Success for CDF•• SVT provides SVT provides offline quality 2D trackingoffline quality 2D trackingat Level 2 Trigger of CDFat Level 2 Trigger of CDF combining silicon combining silicondetector and drift chamber information.detector and drift chamber information.

•• It allows to implement It allows to implement selections on theselections on theimpact parameter of the tracks at triggerimpact parameter of the tracks at triggerlevel to look for long living particles:level to look for long living particles: b- b-quark, c-quark enriched samples withoutquark, c-quark enriched samples withoutlepton requirements! (first time at lepton requirements! (first time at hadronhadroncolliderscolliders))•• Thanks to SVT : Thanks to SVT :

35µm ⊕ 33µmresol ⊕ beam⇒ σ = 48µm

B→h h

Bs MixingBs MixingBB→→hhhh

On-line Plot !

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 33

On-Line Tracking: the SVT wayOn-Line Tracking: the SVT way

RoadsRoads1.1. Find Find low resolutionlow resolutiontrack track candidatescandidatescalled called ““roadsroads””..Solve most of theSolve most of thepattern recognitionpattern recognition

Super Bin (SB)Super Bin (SB)

Pattern Pattern RecognitionRecognition

(AM)(AM)

2.2. Then fit tracksThen fit tracksinside roads.inside roads.Thanks to 1Thanks to 1stst

step it is muchstep it is mucheasiereasier

Track Track FittingFitting(TF)(TF)

A two steps AlgorithmA two steps Algorithm

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 44

Track Fitter AlgorithmTrack Fitter Algorithm•• Linear expansion in the hit positions x Linear expansion in the hit positions xi i reduces track fitting toreduces track fitting toscalar productsscalar products::

•• ppii : track parameters (P : track parameters (Ptt, , φφ00 and Impact Par. and Impact Par.))•• ffii , , qqii: know constants.: know constants.•• x x : vector of hit positions: vector of hit positions

• hit hit →→ 18 bits 18 bits..••Old FPGA Old FPGA →→ at maximum 8x8 multipliers at maximum 8x8 multipliers. . →→ Large Memory corrections Large Memory corrections•• Scalar products Scalar products splitted splitted in two terms:in two terms:

Pre-calculated term: Pre-calculated term: One for each RoadOne for each Road

On-line evaluated withOn-line evaluated with8x8 bit multipliers8x8 bit multipliers

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 55

The The GigaFitter GigaFitter corecore•• Technology improves, of course Technology improves, of course……•• Today new FPGAs equipped with many 25x18 bit Today new FPGAs equipped with many 25x18 bitmultipliers are available, like the:multipliers are available, like the:

Xilinx VIRTEX 5: 65 nm- 550 MHz devices XC5VSX95T: 160 x 46 CLB Array (Row x Col)

244 39kbits BlockRams or Fifos+ 640DSP Slices (organized in columns)

It allows to It allows to come back to the original scalar productcome back to the original scalar productwith the full hit positions using 18x18 bit multiplierswith the full hit positions using 18x18 bit multipliers

No need for pre-calculatedNo need for pre-calculatedtermsterms (stored in big memories) (stored in big memories)

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 66

DSP SlicesDSP Slices

46

160

CLBCLB: : ““AndAnd””, FF,, FF,and look-up tablesand look-up tables

DSPDSP: dedicated: dedicatedarithmetic logicarithmetic logic

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 77

Old Track FitterOld Track Fitter

2.5 cm

10.6 cm• The CDF Silicon Vertex (SVX) isThe CDF Silicon Vertex (SVX) isorganized in 12 phi wedges.organized in 12 phi wedges.•• For For each wedgeeach wedge, a TF (implemented in, a TF (implemented ina Pulsar board) is coupled to thea Pulsar board) is coupled to thecorresponding AM.corresponding AM.

12 Pulsars, one for each TF

Pre-Calculated termsPre-Calculated termsmemoriesmemories

Pulsar BoardPulsar Board (general (generalpurpose board used inpurpose board used inthe CDF Trigger/DAQ )the CDF Trigger/DAQ )

X12 !

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 88

The Full New System for SVTThe Full New System for SVT

FPGA JTAG

4 wedge connectors on each4 wedge connectors on eachmezzanine mezzanine →→ possible up to possible up to6x4=24 fits in parallel6x4=24 fits in parallel

3 mezzanines = 123 mezzanines = 12wedgeswedges44thth mezzanine mezzanine →→ large largememory for non-linearitymemory for non-linearitycorrectionscorrections

Pulsar BoardPulsar Board

Only 1 !Only 1 !

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 99

AdvantagesAdvantages•• Shorter processing Time Shorter processing Time

•• Deleted one location per pattern memories Deleted one location per pattern memories →→ Associative AssociativeMemories potentially unlimited, Memories potentially unlimited, many more Patterns for:many more Patterns for:

High Pt PhysicsHigh Pt Physics:: enlarge lepton acceptanceenlarge lepton acceptance B Physics:B Physics: improve track P improve track Ptt and Impact Parameter acceptance and Impact Parameter acceptance

•• Many constant setsMany constant sets: improve tracking efficiency.: improve tracking efficiency.

•• Simultaneous fits of different layer configurations Simultaneous fits of different layer configurations: improve: improveefficiency.efficiency.•• Very Very compactcompact system. (1 board instead of 12 !) system. (1 board instead of 12 !)

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 1010

ConclusionsConclusions•• The The GigaFitter GigaFitter is an upgraded Track Fitteris an upgraded Track Fitter, based on , based on newnewgeneration FPGA DSP arraysgeneration FPGA DSP arrays..

•• An important An important step forwardstep forward for dedicated powerful for dedicated powerfulprocessors for on-line track reconstruction at processors for on-line track reconstruction at hadron collidershadron colliders,,following the following the strategy successfully implementedstrategy successfully implemented by the SVT at by the SVT atCDF.CDF.

•• The The GigafitterGigafitter is expected to upgrade the SVT system in theis expected to upgrade the SVT system in thelast data taking period of the CDF experiment, BUTlast data taking period of the CDF experiment, BUT……

•• …… the the GigaFitter GigaFitter is in general is in general a very powerful processor toa very powerful processor tobe used wherever many scalar productsbe used wherever many scalar products at high workingat high workingfrequency are needed.frequency are needed.

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 1111

BACKUPBACKUP

XCIII XCIII CongressoCongresso SIF, Pisa SIF, Pisa P.P. CatastiniCatastini 1212

The The GigaFitterGigaFitter

SVT FiFo35 MHz

II FiFo70 MHz

Lay0-Ram or SR

Lay1 - Ram or SR

La y2 - R am or SR

Lay 3- Ram o r SR

Lay 4- Ram o r SR

XFT- Ram

o r SRC om

b - Fi Fo

7 Mult+7 Σ

6 Mult+6 Σ

6 Mult+6 Σ

6 Mult+6 Σ

6 Mult+6 Σ

6 Mult+6 Σ

4/5 silicon 5/5 silicon

6x6x5 + 7x7= 229 DSP slicesChoose best chi**2

6 input LUTInside Slices

BLock RAMs

Choo se th e best chi **2