The Shift Register

The Shift Register

The Shift Register

TheShift Registeris another type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers and then "shifts" the data out once every clock cycle, hence the name "shift register". It basically consists of several single bit "D-Type Data Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. The data bits may be fed in or out of the register serially, i.e. one after the other from either the left or the right direction, or in parallel, i.e. all together. The number of individual data latches required to make up a singleShift Registeris determined by the number of bits to be stored with the most common being 8-bits wide, i.e. eight individual data latches.

The Shift Register is used for data storage or data movement and are used in calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. The individual data latches that make up a single shift register are all driven by a common clock (Clk) signal making them synchronous devices. Shift register IC's are generally provided with aclearorresetconnection so that they can be "SET" or "RESET" as required.

Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register being:

Serial-in to Parallel-out (SIPO)- the register is loaded with serial data, one bit at a time, with the stored data being available in parallel form.

Serial-in to Serial-out (SISO)- the data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a left or right direction under clock control.

Parallel-in to Serial-out (PISO)- the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.

Parallel-in to Parallel-out (PIPO)- the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.

The effect of data movement from left to right through a shift register can be presented graphically as:

Also, the directional movement of the data through a shift register can be either to the left, (left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same register thereby making itbidirectional. In this tutorial it is assumed that all the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO)

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops (FFAtoFFD) have just been RESET (CLEAR input) and that all the outputsQAtoQDare at logic level "0" i.e, no parallel data output. If a logic "1" is connected to theDATAinput pin ofFFAthen on the first clock pulse the output ofFFAand therefore the resultingQAwill be set HIGH to logic "1" with all the other outputs still remaining LOW at logic "0". Assume now that theDATAinput pin ofFFAhas returned LOW again to logic "0" giving us one data pulse or 0-1-0.

The second clock pulse will change the output ofFFAto logic "0" and the output ofFFBandQBHIGH to logic "1" as its inputDhas the logic "1" level on it fromQA. The logic "1" has now moved or been "shifted" one place along the register to the right as it is now atQA. When the third clock pulse arrives this logic "1" value moves to the output ofFFC(QC) and so on until the arrival of the fifth clock pulse which sets all the outputsQAtoQDback again to logic level "0" because the input toFFAhas remained constant at logic level "0".

The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of0-0-0-1is stored in the register. This data value can now be read directly from the outputs ofQAtoQD. Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic "1" through the register from left to right as follows.

Basic Movement of Data through a Shift Register

Clock Pulse NoQAQBQCQD

00000

11000

20100

30010

40001

50000

Note that after the fourth clock pulse has ended the 4-bits of data (0-0-0-1) are stored in the register and will remain there provided clocking of the register has stopped. In practice the input data to the register may consist of various combinations of logic "1" and "0". Commonly availableSIPOIC's include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO)

Thisshift registeris very similar to the SIPO above, except were before the data was read directly in a parallel form from the outputsQAtoQD, this time the data is allowed to flow straight through the register and out of the other end. Since there is only one output, theDATAleaves the shift register one bit at a time in a serial pattern, hence the nameSerial-in to Serial-Out Shift RegisterorSISO.

The SISO shift register is one of the simplest of the four configurations as it has only three connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

You may think what's the point of a SISO shift register if the output data is exactly the same as the input data. Well this type ofShift Registeralso acts as a temporary storage device or as a time delay device for the data, with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC's include the 74HC595 8-bit Serial-in/Serial-out Shift Register all with 3-state outputs.

Parallel-in to Serial-out (PISO)

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The data is loaded into the register in a parallel format i.e. all the data bits enter their inputs simultaneously, to the parallel input pinsPAtoPDof the register. The data is then read out sequentially in the normal shift-right mode from the register atQrepresenting the data present atPAtoPD. This data is outputted one bit at a time on each clock cycle in a serial format. It is important to note that with this system a clock pulse is not required to parallel load the register as it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format, it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line. Commonly available IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO)

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above. The data is presented in a parallel format to the parallel input pinsPAtoPDand then transferred together directly to their respective output pinsQAtoQAby the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections, the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the sequencing clock signal (Clk).

Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses. Also, in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required.

Universal Shift Register

Today, high speed bi-directional "universal" typeShift Registerssuch as the TTL 74LS194, 74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, and as a parallel-to-parallel multifunction data register, hence the name "Universal". These devices can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to pre-load and reset the device.

4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond to operations that require some form of temporary memory, delay information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format. Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division.

Summary of Shift Registers

Then to summarise.

A simpleShift Registercan be made using only D-type flip-Flops, one flip-Flop for each data bit.

The output from each flip-Flop is connected to theDinput of the flip-flop at its right.

Shift registers hold the data in their memory which is moved or "shifted" to their required positions on each clock pulse.

Each clock pulse shifts the contents of the register one bit position to either the left or the right.

The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded simultaneously in a parallel configuration (PI).

Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO).

One application of shift registers is converting between serial and parallel data.

Shift registers are identified as SIPO, SISO, PISO, PIPO, and universal shift registers.

In the next tutorial aboutSequential Logic Circuits, we will look at what happens when the output of the last flip-flop in a shift register is connected directly back to the input of the first flip-flop producing a closed loop circuit that constantly recirculates the data around the loop. This then produces another type of sequential logic circuit called aRing Counterthat are used as decade counters and dividers.

http://www.electronics-tutorials.ws/sequential/seq_5.htmlBand Resistor Calculator

Calculate the resistance of a 4 band resistor

EEWebResistance Calculator

Choose Type

4 Band

5 Band

6 Band4 Band Resistor

1st Digit

2nd Digit

Multiplier

Tolerance

Black

00

Brown

1

1

x10

1%

Red

2

2

x100

2%

Orange

3

3

x1K

3%

Yellow

4

4

x10K

4%

Green

5

5

x100K

0.5%

Blue

6

6

x1M

0.25%

Violet

7

7

x10M

0.10%

Grey

8

8

x100M

0.05%

White

9

9

x1G

Gold

10

5%

Silver

100

10%

Outputs

Resistance:

5.60kohms

Tolerance:

5%

IntroductionA resistor is a perhaps the most common building block used in circuits. Resistors come in many shapes and sizes this tool is used to decode information for color banded axial lead resistors.

4 Band DescriptionThe number of bands is important because the decoding changes based upon the number of color bands. There are three common types: 4 band, 5 band, and 6 band resistors. For the 4 band resistor:

Band 1 First significant digit.Band 2 Second significant digitBand 3 MultiplierBand 4 Tolerance

Resistance ValueThe first 4 bands make up the resistance nominal value. The first 2 bands make up the significant digits where:black 0brown 1red 2orange 3yellow 4green 5blue 6violet 7grey 8white 9The 3rd band or multiplier band is color coded as follows:black x1brown x10red x100orange x1Kyellow x10Kgreen x100Kblue x1Mviolet x10Mgrey x100Mwhite x1Ggold .1silver .01An example of a resistance value is:

band 1 = orange = 3,band 2 = yellow = 4,band 3 = blue = 1M

value = 34*1M = 34 Mohm

Resistance ToleranceThe fourth band is the tolerance and represents the worst case variation one might expect from the nominal value. The color code for tolerance is as follows:brown 1%red 2%orange 3%yellow 4%green .5%blue .25%violet .1%gray .05%gold 5%silver 10%An example calculating the range of a resistor value is:

If the nominal value was 345 Ohm and the 4th band of the resistor was gold (5%) the value range would be nominal +/- 5% = 32.3 to 35.7


Choose Type

4 Band

5 Band


1st Digit

2nd Digit

3rd Digit

Multiplier

Tolerance

Black

0

0

x1

Brown

1

1

1

x10

1%

Red

2

2

2

x100

2%

Orange

3

3

3

x1K

3%

Yellow

4

4

4

x10K

4%

Green

5

5

5

x100K

0.5%

Blue

6

6

6

x1M

0.25%

Violet

7

7

7

x10M

0.10%

Grey

8

8

8

x100M

0.05%

White

9

9

9

x1G

Gold

10

5%

Silver

100

10%

Outputs

Resistance:

56.00kohms

Tolerance:

5%



Band 1 First significant digit.Band 2 Second significant digitBand 3 Third significant digitBand 4 MultiplierBand 5 Tolerance

Resistance ValueThe first 4 bands make up the resistance nominal value. The first 3 bands make up the significant digits where:black 0brown 1red 2orange 3yellow 4green 5blue 6violet 7grey 8white 9The 4th band or multiplier band is color coded as follows:black x1brown x10red x100orange x1Kyellow x10Kgreen x100Kblue x1Mviolet x10Mgrey x100Mwhite x1Ggold .1silver .01An example of a resistance value is:

band 1 = orange = 3,band 2 = yellow = 4,band 3 = green = 5,band 4 = blue = 1M


Resistance ToleranceThe fifth band is the tolerance and represents the worst case variation one might expect from the nominal value. The color code for tolerance is as follows:brown 1%red 2%orange 3%yellow 4%green .5%blue .25%violet .1%gray .05%gold 5%silver 10%An example calculating the range of a resistor value is:


Band Resistor Calculator

Calculate the resistance of a 6 band resistor


Choose Type

4 Band

5 Band


1st Digit

2nd Digit

3rd Digit

Multiplier

Tolerance

Tempco

Black

0

0

x1

Brown

1

1

1

x10

1%

100

Red

2

2

2

x100

2%

50

Orange

3

3

3

x1K

3%

15

Yellow

4

4

4

x10K

4%

25

Green

5

5

5

x100K

0.5%

Blue

6

6

6

x1M

0.25%

10

Violet

7

7

7

x10M

0.10%

5

Grey

8

8

8

x100M

0.05%

White

9

9

9

x1G

Gold

10

5%

Silver

100

10%

Outputs

Resistance:

56.00kohms

Tolerance:

5%

Tempco:

25ppm/C



Band 1 first significant digit.Band 2 second significant digitBand 3 third significant digitBand 4 MultiplierBand 5 ToleranceBand 6 Temperature Coefficient (Tempco)

Resistance ValueThe first 4 bands make up the resistance nominal value. The first 3 bands make up the significant digits where:black 0brown 1red 2orange 3yellow 4green 5blue 6violet 7grey 8white 9The multiplier band is color coded as follows:black x1brown x10red x100orange x1Kyellow x10Kgreen x100Kblue x1Mviolet x10Mgrey x100Mwhite x1Ggold .1silver .01An example of a resistance value is:

band 1 = orange = 3,band 2 = yellow = 4,band 3 = green = 5,band 4 = blue = 1M


Resistance ToleranceThe fifth band is the tolerance and represents the worst case variation one might expect from the nominal value. The color code for tolerance is as follows:brown 1%red 2%orange 3%yellow 4%green .5%blue .25%violet .1%gray .05%gold 5%silver 10%An example calculating the range of a resistor value is:


Resistance Temperature CoefficientResistors values can change with temperature. The 6th band represents the temperature coefficient or tempco and is represents the amount the resistance value will change with temperature. It is in units of ppm/degree C. The band colors represents the following:

brown 100 ppm/degreeCred 50 ppm/degreeCorange 15 ppm/degreeCyellow 25 ppm/degreeCblue 10 ppm/degreeCviolet 5 ppm/degreeCAn example if a resistor had a nominal value of 1K ohm and a tempco of 100 ppm/degreeC and we wanted to know how much a resitor would change of 25degreeC.

100*25/1e6*1K= 2.5 ohm variation over 25degreeC.

What are a Half Adder and a Full Adder

(http://www.trivology.com/articles/518/what-are-a-half-adder-and-a-full-adder.html)Half Adder is a digital combinational circuit that is used for the addition of two bits and provides an output in the form of a sum bit and a carry bit. The logical functional equations that relate the outputs S and C of a half adder circuit to the input bits are given below:-

Sum(S) = A ex-OR B Carry(C) = A.B

Logic Symbol

SchematicThus a half adder circuit can easily be synthesized by using 1 ex-OR gate and 1 AND gate. Since a half adder circuit can only be used to add two bits, it becomes obsolete in case of multi-bit addition in practical applications.

A Full adder circuit is the one that is used for addition of three bits. It is more complex than a half adder circuit. Let A,B and C be the input bits of a full adder and S and C be the output bits, then the logical equations that relates the outputs to the inputs are:-S= A (ex-OR) B (ex-OR) C C= AB + C (A+B)

Logic Symbol

SchematicThus two ex-OR gates, two AND gates and two OR gates can be used for the hardware synthesis of the circuit. These full adder circuits are the ones that can be used for multi bit addition of numbers.

In addition of multiple bits, the carry output from a full adder being used for the addition of bits at ones place isfedas an input bit to the full adder being used for the addition of the bits at the next significant place and so on. The sum bits from all the full adders along with the carry bit from the full adder dealing with the most significant bits is available to the user as an output. The carry input to the full adder dealing with the least significant place should be made 0 by the user.

In market, only 4 bit full adders and 8 bit full adders are available in IC form and they need to be combined for addition of higher number of bits such as 16 and 32. The biggest disadvantage of a multi-bit full adder is the large propagation delay that is encountered in the transmission of carry bits from one adder block to the other. That is the reason why these have been replaced by more sophisticated designs such a look ahead carry adder in practical computational systems.Half Adder and Full Adder Circuit

Half Adder and Full Adder circuits is explained with their truth tables in this article. Design of Full Adder using Half Adder circuit is also shown.Single-bit Full Adder circuit and Multi-bit addition using Full Adder is also shown.Half AdderWith the help of half adder, we can design circuits that are capable of performing simple addition with the help of logic gates.

Let us first take a look at the addition of single bits.

0+0 = 0

0+1 = 1

1+0 = 1

1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this problem can be solved with the help of an EXOR Gate, if you do care about the output, the sum result must be re-written as a 2-bit output.

Thus the above equations can be written as

0+0 = 00

0+1 = 01

1+0 = 01

1+1 = 10

Here the output 1of 10 becomes the carry-out. The result is shown in a truth-table below. SUM is the normal output and CARRY is the carry-out.

INPUTS OUTPUTSA B SUM CARRY0 0 0 0

0 1 1 0

1 0 1 01 1 0 1

From the equation it is clear that this 1-bit adder can be easily implemented with the help of EXOR Gate for the output SUM and an AND Gate for the carry. Take a look at the implementation below.

Half Adder Circuit

For complex addition, there may be cases when you have to add two 8-bit bytes together. This can be done only with the help of full-adder logic.

Full AdderThis type of adder is a little more difficult to implement than a half-adder. The main difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry designated as CIN. When a full adder logic is designed we will be able to string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.

The output carry is designated as COUT and the normal output is designated as S. Take a look at the truth-table.

INPUTS OUTPUTSA B CIN COUT S0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

From the above truth-table, the full adder logic can be implemented. We can see that the output S is an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We must also note that the COUT will only be true if any of the two inputs out of the three are HIGH.

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will half adder will be used to add A and B to produce a partial Sum. The second half adder logic can be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit shown below.

Full Adder Circuit

Though the implementation of larger logic diagrams is possible with the above full adder logic a simpler symbol is mostly used to represent the operation. Given below is a simpler schematic representation of a one-bit full adder.

Single-bit Full Adder

With this type of symbol, we can add two bits together taking a carry from the next lower order of magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit blocks. The addition of two 4-bit numbers is shown below.

Multi-Bit Addition using Full Adder

(http://www.circuitstoday.com/half-adder-and-full-adder)

Flip Flops

hareBasic Flip Flops

This article deals with the basic flip flop circuits like S-R Flip Flop, J-K Flip Flop, D Flip Flop, and T Flip Flop along with truth tables and their corresponding circuit symbols.Before going to the topic it is important that you get knowledge of its basics. Click on the links below for more information.

Flip flops are actually an application of logic gates. With the help of Boolean logic you can create memory with them. Flip flops can also be considered as the most basic idea of a Random Access Memory [RAM]. When a certain input value is given to them, they will be remembered and executed, if the logic gates are designed correctly. A higher application of flip flops is helpful in designing better electronic circuits.

The most commonly used application of flip flops is in the implementation of a feedback circuit. As a memory relies on the feedback concept, flip flops can be used to design it.

There are mainly four types of flip flops that are used in electronic circuits. They are

1. The basic Flip Flop or S-R Flip Flop2. Delay Flip Flop [D Flip Flop]3. J-K Flip Flop4. T Flip Flop1. S-R Flip FlopThe SET-RESET flip flop is designed with the help of two NOR gates and also two NAND gates. These flip flops are also called S-R Latch.

S-R Flip Flop using NOR GateThe design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are also two outputs, Q and Q. The diagram and truth table is shown below.

S-R Flip Flop using NOR Gate

From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0Q=1, Q=0This state is also called the SET state.

S=0, R=1Q=0, Q=1This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the value of Q follows the value of S.

S=0, R=0Q & Q = RememberIf both the values of S and R are switched to 0, then the circuit remembers the value of S and R in their previous state.

S=1, R=1Q=0, Q=0 [Invalid]This is an invalid state because the values of both Q and Q are 0. They are supposed to be compliments of each other. Normally, this state must be avoided.

S-R Flip Flop using NAND GateThe circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

S-R Flip Flop using NAND Gate

Like the NOR Gate S-R flip flop, this one also has four states. They are

S=1, R=0Q=0, Q=1This state is also called the SET state.

S=0, R=1Q=1, Q=0This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the value of Q follows the compliment value of S.

S=0, R=0Q=1, & Q =1 [Invalid]If both the values of S and R are switched to 0 it is an invalid state because the values of both Q and Q are 1. They are supposed to be compliments of each other. Normally, this state must be avoided.

S=1, R=1Q & Q= RememberIf both the values of S and R are switched to 1, then the circuit remembers the value of S and R in their previous state.

Clocked S-R Flip FlopIt is also called a Gated S-R flip flop.

The problems with S-R flip flops using NOR and NAND gate is the invalid state. This problem can be overcome by using a bistable SR flip-flop that can change outputs when certain invalid states are met, regardless of the condition of either the Set or the Reset inputs. For this, a clocked S-R flip flop is designed by adding two AND gates to a basic NOR Gate flip flop. The circuit diagram and truth table is shown below.

Clocked S-R Flip Flop

A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is 0, the outputs of both the AND Gates remain 0. As soon as a pulse is given the value of CP turns 1. This makes the values at S and R to pass through the NOR Gate flip flop. But when the values of both S and R values turn 1, the HIGH value of CP causes both of them to turn to 0 for a short moment. As soon as the pulse is removed, the flip flop state becomes intermediate. Thus either of the two states may be caused, and it depends on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse. Thus the invalid states can be eliminated.

2. D Flip FlopThe circuit diagram and truth table is given below.

D Flip Flop

D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From the figure you can see that the D input is connected to the S input and the complement of the D input is connected to the R input. The D input is passed on to the flip flop when the value of CP is 1. When CP is HIGH, the flip flop moves to the SET state. If it is 0, the flip flop switches to the CLEAR state.

To know more about the triggering of flip flop click on the link below.

TAKE A LOOK :TRIGGERING OF FLIP FLOPSTAKE A LOOK :MASTER-SLAVE FLIP FLOP CIRCUIT3. J-K Flip FlopThe circuit diagram and truth-table of a J-K flip flop is shown below.

J-K Flip Flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is that the intermediate state is more refined and precise than that of a S-R flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.

The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back as a feedback to the input of the AND along with other inputs like K and clock pulse [CP]. So, if the value of CP is 1, the flip flop gets a CLEAR signal and with the condition that the value of Q was earlier 1. Similarly output Q of the flip flop is given as a feedback to the input of the AND along with other inputs like J and clock pulse [CP]. So the output becomes SET when the value of CP is 1 only if the value of Q was earlier 1.

The output may be repeated in transitions once they have been complimented for J=K=1 because of the feedback connection in the JK flip-flop. This can be avoided by setting a time duration lesser than the propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction.

4. T Flip FlopThis is a much simpler version of the J-K flip flop. Both the J and K inputs are connected together and thus are also called a single input J-K flip flop. When clock pulse is given to the flip flop, the output begins to toggle. Here also the restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction. Take a look at the circuit and truth table below.

T Flip Flop

(http://www.circuitstoday.com/flip-flops)

Transformer

JOHNDECEMBER - 23 - 2011

8 COMMENTS6ShareMost of the electronic circuits used in Circuitstoday.com have different applications of the transformer. Therefore, it is important to know the working principle, construction and types of transformers used in different analog circuits.

Transformer Working PrincipleA transformer can be defined as a static device which helps in the transformation of electric power in one circuit to electric power of the same frequency in another circuit. The voltage can be raised or lowered in a circuit, but with a proportional increase or decrease in the current ratings.

The main principle of operation of a transformer is mutual inductance between two circuits which is linked by a common magnetic flux. A basic transformer consists of two coils that are electrically separate and inductive, but are magnetically linked through a path of reluctance. The working principle of the transformer can be understood from the figure below.

Transformer Working

As shown above the transformer has primary and secondary windings. The core laminations are joined in the form of strips in between the strips you can see that there are some narrow gaps right through the cross-section of the core. These staggered joints are said to be imbricated. Both the coils have high mutual inductance. A mutual electro-motive force is induced in the transformer from the alternating flux that is set up in the laminated core, due to the coil that is connected to a source of alternating voltage. Most of the alternating flux developed by this coil is linked with the other coil and thus produces the mutual induced electro-motive force. The so produced electro-motive force can be explained with the help of Faradays laws of Electromagnetic Induction as

e=M*dI/dt

If the second coil circuit is closed, a current flows in it and thus electrical energy is transferred magnetically from the first to the second coil.

The alternating current supply is given to the first coil and hence it can be called as the primary winding. The energy is drawn out from the second coil and thus can be called as the secondary winding.

In short, a transformer carries the operations shown below:

1. Transfer of electric power from one circuit to another.

2. Transfer of electric power without any change in frequency.

3. Transfer with the principle of electromagnetic induction.

4. The two electrical circuits are linked by mutual induction.

Transformer ConstructionFor the simple construction of a transformer, you must need two coils having mutual inductance and a laminated steel core. The two coils are insulated from each other and from the steel core. The device will also need some suitable container for the assembled core and windings, a medium with which the core and its windings from its container can be insulated.

In order to insulate and to bring out the terminals of the winding from the tank, apt bushings that are made from either porcelain or capacitor type must be used.

In all transformers that are used commercially, the core is made out of transformer sheet steel laminations assembled to provide a continuous magnetic path with minimum of air-gap included. The steel should have high permeability and low hysteresis loss. For this to happen, the steel should be made of high silicon content and must also be heat treated. By effectively laminating the core, the eddy-current losses can be reduced. The lamination can be done with the help of a light coat of core plate varnish or lay an oxide layer on the surface. For a frequency of 50 Hertz, the thickness of the lamination varies from 0.35mm to 0.5mm for a frequency of 25 Hertz.

Types of TransformersThe types of transformers differ in the manner in which the primary and secondary coils are provided around the laminated steel core. According to the design, transformers can be classified into two:

1.Core- Type TransformerIn core-type transformer, the windings are given to a considerable part of the core. The coils used for this transformer are form-wound and are of cylindrical type. Such a type of transformer can be applicable for small sized and large sized transformers. In the small sized type, the core will be rectangular in shape and the coils used are cylindrical. The figure below shows the large sized type. You can see that the round or cylindrical coils are wound in such a way as to fit over a cruciform core section. In the case of circular cylindrical coils, they have a fair advantage of having good mechanical strength. The cylindrical coils will have different layers and each layer will be insulated from the other with the help of materials like paper, cloth, micarta board and so on. The general arrangement of the core-type transformer with respect to the core is shown below. Both low-voltage (LV) and high voltage (HV) windings are shown.

Core Type Transformer Cruciform Section

Core Type Transformers

The low voltage windings are placed nearer to the core as it is the easiest to insulate. The effective core area of the transformer can be reduced with the use of laminations and insulation.

2.Shell-Type TransformerIn shell-type transformers the core surrounds a considerable portion of the windings. The comparison is shown in the figure below.

Core Type and Shell Type Transformer Winding

The coils are form-wound but are multi layer disc type usually wound in the form of pancakes. Paper is used to insulate the different layers of the multi-layer discs. The whole winding consists of discs stacked with insulation spaces between the coils. These insulation spaces form the horizontal cooling and insulating ducts. Such a transformer may have the shape of a simple rectangle or may also have a distributed form. Both designs are shown in the figure below:

Shell Type Transformers Rectangular Form

Shell Type Transformers Distributed Form

A strong rigid mechanical bracing must be given to the cores and coils of the transformers. This will help in minimizing the movement of the device and also prevents the device from getting any insulation damage. A transformer with good bracing will not produce any humming noise during its working and will also reduce vibration.

A special housing platform must be provided for transformers. Usually, the device is placed in tightly-fitted sheet-metal tanks filled with special insulating oil. This oil is needed to circulate through the device and cool the coils. It is also responsible for providing the additional insulation for the device when it is left in the air.

There may be cases when the smooth tank surface will not be able to provide the needed cooling area. In such cases, the sides of the tank are corrugated or assembled with radiators on the sides of the device. The oil used for cooling purpose must be absolutely free from alkalis, sulphur and most importantly moisture. Even a small amount of moistures in the oil will cause a significant change in the insulating property of the device, as it lessens the dielectric strength of the oil to a great extent. Mathematically speaking, the presence of about 8 parts of water in 1 million reduces the insulating quality of the oil to a value that is not considered standard for use. Thus, the tanks are protected by sealing them air-tight in smaller units. When large transformers are used, the air tight method is practically difficult to implement. In such cases, chambers are provided for the oil to expand and contract as its temperature increases and decreases. These breathers form a barrier and resists the atmospheric moisture from contact with oil. Special care must also be taken to avoid sledging. Sledging occurs when oil decomposes due to over exposure to oxygen during heating. It results in the formation of large deposits of dark and heavy matter that clogs the cooling ducts in the transformer.

The quality, durability and handling of these insulating materials decide the life of the transformer. All the transformer leads are brought out of their cases through suitable bushings. There are many designs of these, their size and construction depending on the voltage of the leads. Porcelain bushings may be used to insulate the leads, for transformers that are used in moderate voltages. Oil-filled or capacitive-type bushings are used for high voltage transformers.

The selection between the core and shell type is made by comparing the cost because similar characteristics can be obtained from both types. Most manufacturers prefer to use shell-type transformers for high-voltage applications or for multi-winding design. When compared to a core type, the shell type has a longer mean length of coil turn. Other parameters that are compared for the selection of transformer type are voltage rating, kilo-volt ampere rating, weight, insulation stress, heat distribution and so on.

Transformers can also be classified according to the type of cooling employed. The different types according to these classifications are:

1.Oil Filled Self-Cooled TypeOil filled self cooled type uses small and medium-sized distribution transformers. The assembled windings and core of such transformers are mounted in a welded, oil-tight steel tanks provided with a steel cover. The tank is filled with purified, high quality insulating oil as soon as the core is put back at its proper place. The oil helps in transferring the heat from the core and the windings to the case from where it is radiated out to the surroundings. For smaller sized transformers the tanks are usually smooth surfaced, but for large size transformers a greater heat radiation area is needed, and that too without disturbing the cubical capacity of the tank. This is achieved by frequently corrugating the cases. Still larger sizes are provided with radiation or pipes.

2.Oil Filled Water Cooled TypeThis type is used for much more economic construction of large transformers, as the above told self cooled method is very expensive. The same method is used here as well- the windings and the core are immersed in the oil. The only difference is that a cooling coil is mounted near the surface of the oil, through which cold water keeps circulating. This water carries the heat from the device. This design is usually implemented on transformers that are used in high voltage transmission lines. The biggest advantage of such a design is that such transformers do not require housing other than their own. This reduces the costs by a huge amount. Another advantage is that the maintenance and inspection of this type is only needed once or twice in a year.

3.Air Blast TypeThis type is used for transformers that use voltages below 25,000 volts. The transformer is housed in a thin sheet metal box open at both ends through which air is blown from the bottom to the top.

E.M.F Equation of a Transformer

Transformer EMF Equation

Let,

NA=Number of turns in primary

NB= Number of turns in secondary

max= Maximum flux in the core in webers = BmaxX A

f = Frequency of alternating current input in hertz (HZ)

As shown in figure above, the core flux increases from its zero value to maximum value max in one quarter of the cycle , that is in frequency second.

Therefore, average rate of change of flux = max/ f = 4f maxWb/s

Now, rate of change of flux per turn means induced electro motive force in volts.

Therefore, average electro-motive force induced/turn = 4f maxvolt

If flux varies sinusoidally, then r.m.s value of induced e.m.f is obtained by multiplying the average value with form factor.

Form Factor = r.m.s. value/average value = 1.11

Therefore, r.m.s value of e.m.f/turn = 1.11 X 4f max= 4.44f maxNow, r.m.s value of induced e.m.f in the whole of primary winding

= (induced e.m.f./turn) X Number of primary turns

Therefore,

EA= 4.44f NAmax= 4.44fNABmA

Similarly, r.m.s value of induced e.m.f in secondary is

EB= 4.44f NBmax= 4.44fNBBmA

In an ideal transformer on no load,

VA= EAand VB= EB, where VBis the terminal voltage

Voltage Transformation Ratio (K)From the above equations we get

EB/ EA= VB/ VA= NB/NA= K

This constant K is known as voltage transformation ratio.

(1) If NB>NA, that is K>1 , then transformer is called step-up transformer.

(2) If NB

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