The SLHC CMS L1 Pixel Trigger & Detector Layout

Wu, JinyuanFermilab

April 2006

Preference on Detector Layout• Pixel planes are expensive in terms of material, cost, data volume,

power, cooling etc. (C3: Cost, Cable, Cooling)• If N layers of pixel detector planes are affordable, normally spaced

configurations like (b) is more preferable for data analysis stage.• Pattern recognition for (b) is more difficult .• From BTeV works, the pattern recognition for (b) is not as hard as we

thought several years ago .

(a) (b)

Brief History of Tracking

• Long time ago, tracking was done by:– Finding 2-point candidates (doublets) and then– Finding the third point.

• Before BTeV, it was known:– Triplet can be found in one step.

• During BTeV, we learnt how to do triplet finding in FPGA fast and cheaply. (e. g. Tiny Triplet Finder)

Circular Tracks from Collision Pointon Cylindrical Detectors

• For a given hit on layer 3, the coincident between a layer 2 and a layer 1 hit satisfying coincident map signifies a valid circular track.

• A track segment has 2 free parameters, i.e., a triplet.• The coincident map is invariant of rotation.

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1-3)+64

2-

3)+6

4

Tiny Triplet FinderReuse Coincident Logic via Shifting Hit Patterns

C1

C2

C3

One set of coincident logic is implemented.

For an arbitrary hit on C3, rotate, i.e., shift the hit patterns for C1 and C2 to search for coincidence.

Tiny Triplet Finder for Circular Tracks

*R1/R3

*R2/R3

Triplet Map Output To Decoder

Bit

Arr

ay

Shifter

Bit

Arr

ay

ShifterBit-wise Coincident Logic

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1. Fill the C1 and C2 bit arrays. (n1 clock cycles)

2. Loop over C3 hits, shift bit arrays and check for coincidence. (n3 clock cycles)

Also works with more than 3 layers

Question: How can data fromdifferent layers merge together?

• Total data rates from pixel layer @ 10cm are: 3.125, 5 or 12 Gb/s/cm2.

• To send full data over large distance is difficult. (The good side of stacked layer ideas is the possibility of doing coincident locally.)

• Difficult, yes, but there are several possibilities.

Possibility 1

Pre-trigger

From LHC to SLHC

• The total L1 latency for SLHC has been increased to 6.4 us.

• Total L1 rate is kept the same (100kHz).

• Consider a pre-trigger of 1MHz @ 3.2 us.

• Use pre-trigger to dump data from pixel.

• Data rate: 1/80 or 1/40.

BX=40MHzL=1034

BX=80MHzL=1035

Latency3.2 s

Current LHC CMS L1:

<100 kHz

SLHC CMS pre-trigger?

<1MHz

Latency6.4 s

SLHC CMS L1:

<100 kHz

Sending Data to Triplet Finder:

The Pre-trigger

• ECAL (or any other) generates coarse pre-trigger and sends to global L1.• The pre-trigger is distributed to all (or 1/2, 1/4 of all) readout chips at 3.2 us. The

distribution lines are original L1 trigger signal lines.• The ROC output data and the tracker trigger generates trigger primitives.• The L1 system makes final global T1.• Pre-triggered data stored in Tracker Trigger during the second 3.2 us are sent to

HLT/DAQ. ROC has shorter pipeline in this operation mode.• Worst case: two round trips. Better if one round trip can be eliminated.

ECAL

ROC

ROC

ROC

ROC

TripletFinder

L1

ECAL Pre-trigger ECAL finer trigger

Cable L1 PT Cable

Cable L1 trigger Cable

Cable L1 trigger Cable

ROC out

Triplet Trigger

3.2us

HLTDAQ

Some Numbers• Assume: ECAL generates up to 1MHz pre-trigger with

3.2us latency.• Use the hit rate 4hits/(1.28cm)2/BX @ R=8cm.• Total data rate: 4hits x 16 bits/hit x 1MHz = 64 Mb/s.• Assume each (1.28cm2) ROC output Cu pairs @ 160

Mb/s.

ECAL

ROC

ROC

ROC

ROC

L1

ECAL Pre-trigger ECAL finer trigger

Cable L1 PT Cable

Cable L1 trigger Cable

Cable L1 trigger Cable

ROC out

3.2us

HLTDAQ

R (cm) [hits]/(1.28cm)2/BX[Foundas]

Data Rate(Mb/s/ROC) (assume 16 bits/hit)

# of 160 Mb/s Cu pairs/ROC

Output Capacity (Mb/s/ROC)

5

10 4 [ @ 8cm] 64 1 or 2 160 or 320

20 1.6 [ @ 14cm] 25 1 160

30 0.8 [est.] 13 1 160

TripletFinder

Triplet Trigger

Possibility 1+

Pre-trigger + Stacked layers for high PT

tracks

High PT Doublet Finding, If Needed

• The system supports both ECAL pre-trigger mode and high PT doublet finding mode.

• The ROC at 300mm and 295mm communicate to each other.• High PT doublets are found in ROC.• The doublets point the searching windows on 200 and 100mm

layers and hits in the window are enabled to be readout.• One set of stack layers, rather than 3.

ECAL

ROC 300

ROC 295 TripletFinder

&Readout

L1

HLTDAQ

R=300mm

R=295mm

R=200mm

R=100mm

R=50mm

ROC 200

ROC 100

ROC 50Readout

Only

Stack Layers: 1mm or 5mm• Pixel pitch: u in , v in z.• Layer separation: (r2-r1).• Measurement error:

– = u / (r2-r1)

– = v / (r2-r1)

• Power Consumption:– P = P0 A /(u u).

• Therefore:– P = P0 A / (r2-r1)2.

• When the layer separation increases from 1mm to 5mm, P reduces by factor of 25.

1mm 5mm

Pixel Pitch 20m()200m(z)

50m()200m(z)

PowerP0 =10W

2.5KW/m2 1KW/m2

Sharing Mech. Support & Cooling

? Yes

Straw Man Stack Layers (r-z view)

• The two stack layers share same mechanical support and cooling layer.• ROC in two layers overlap to each other in z direction. Hits from 1/4 of chip at both end are

sent to opposite chips for coincident.• Questions: overlapping in phi direction?

Sensor

Readout Chip

Mechanical Support,Cooling, interconnection

Readout Chip

Sensor

Seeding Hits

Coincident Range

Straw-Man Readout Chip -- Backend

Column Logic &Zero Suppression Pipeline

6.4us3.2us1.0us

High PT SegmentCorrelation

CS10HDA CS10AHDB

From/to Stack Layer ROC

DOUT

CS64 CS32

T1orPT

From L1

Pipeline and CS32/64

Column Logic &Zero Suppression Pipeline

6.4us3.2us1.0us

DOUT

CS64 CS32

T1orPT From L1

• The hit data are stored in the pipeline.• After 3.2 us, when the pre-trigger comes (signal T1orPT), the ROC

sends data out for triplet trigger.• After 6.4 us, when the L1 comes, the ROC sends data of the BX out.

High PT Correlation

• The OR-AND coincident logic accepts high PT doubles.• Set the Bit Enable Register to change PT cut and correct offset on pixel

alignment.• The OR gate is replaced with a priority encoder in real implementation.

BitEnable

Register

Plane A

Plane B

1 Copy, Not 256 Copies in real implementation

• Some design may use N copies of coincident logic. (N=256 here.)• The design here uses 1 copy.• Note that Plane A is local in the ROC and Plane B is another ROC. The data

from Plane B are column coordinate of hits.• The priority encoder output represents track angle.

Plane A

Plane B

Logarithmic Shifter

Priority Encoder

About This Work• It is extremely interesting since it is still in

detector layout stage. There are not so many chances one can work at this stage in ones life time.

• Simulation, simulation, simulation.• Time is tight. (TDR around ’07, ’08)

The EndThanks

Analysis

• Track reconstruction:– Impact parameter.– Transverse momentum.

• Fake track rejection• Compare configuration (a) and (c) when

silicon strip tracker data are also included.

(a) (b)

(c)