32
THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis Institut d ’Electronique et de Institut d ’Electronique et de Microélectronique Microélectronique du Nord, UMR CNRS 9929 du Nord, UMR CNRS 9929 D. Deschacht D. Deschacht , G. Servel , G. Servel Laboratoire Laboratoire d’Informatique, de Robotique d’Informatique, de Robotique et de et de Microélectronique, UMR CNRS 5506. Microélectronique, UMR CNRS 5506. SLIP ’2000, San Diego, April 8-9th. SLIP ’2000, San Diego, April 8-9th.

THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

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Page 1: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

THEORETICAL LIMITS FOR SIGNAL

REFLECTIONS DUE TO INDUCTANCE

FOR ON-CHIP INTERCONNECTIONS

F. Huret, E. Paleczny, P. KennisF. Huret, E. Paleczny, P. Kennis

Institut d ’Electronique et de Microélectronique Institut d ’Electronique et de Microélectronique

du Nord, UMR CNRS 9929du Nord, UMR CNRS 9929

D. DeschachtD. Deschacht, G. Servel, G. Servel

Laboratoire d’Informatique, de RobotiqueLaboratoire d’Informatique, de Robotique

et de Microélectronique, UMR CNRS 5506.et de Microélectronique, UMR CNRS 5506.

SLIP ’2000, San Diego, April 8-9th.SLIP ’2000, San Diego, April 8-9th.

Page 2: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

OUTLINE OF THE TALK

Introduction

Theoretical limits

Electromagnetic analysis :- Methodology- Application

Limits between RLC and RC models

Illustration of the theoretical limits :- in frequency-domain- in time domain

Comparison with previous work

Conclusion

Page 3: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

INTRODUCTION

0.7µm, 2 metal layers Up to 100,000 devices on a chip Typical CPU frequency 50MHz

0.25µm, 6 metal Up to 10,000,000 devices on a chip Typical CPU frequency 400 MHz

1989 1999

IC

10 years of 10 years of evolutionevolution

10 years of 10 years of evolutionevolution

Page 4: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

INTRODUCTION

With the continued scaling down of technology,increased die aera :

* cross-section decreases* interconnect length increases

interconnections : blocking point of performances improvement

Introduction of new materials such as Cu

inclusion of inductance ?

Page 5: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

INTRODUCTION

Interconnect delay dominates gate delay

in current deep submicronic VLSI circuits.

More accurate interconnect models

and signal propagation characterization are required.

With faster on-chip rise times inductance

is becoming more important.

Electromagnetic analysis is needed.

Page 6: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

THEORETICAL LIMITS

Long lines :

Static hypothesis

x

AeA l

30

12

30

gl

x

lln

Short lines :

Traveling wave leA

Page 7: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

Range of lengths for inductance inclusion :

We have to determine

attenuation factor

phase factor

x : attenuation

coefficient

THEORETICAL LIMITS

x

lln

15

Page 8: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

Propagation parameters of the waveguide

INTERCONNECTION = WAVEGUIDE

Phase factorrad/cm

Attenuation factordB/cm ou Np/cm

Zc Characteristic impedance

ELECTROMAGNETIC ANALYSIS Methodology

Full wave analysis

Finite Element Method

Page 9: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

Zc

Wire length L

v1 v2

i1 i2

v1 v2

i1 i2

Z

v1 v2

i1 i2

Y

v

i

L Z LL

ZL

v

i

c

c

1

1

2

2

cosh( ) sinh( )sinh( )

cosh( )

v

i

Z v

i1

1

2

2

1

0 1

v

i Y

v

i1

1

2

2

1 0

1

j

a

b

c

ELECTROMAGNETIC ANALYSIS Methodology

Definitons of the voltage-current matrices used in this analysis

Page 10: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

ELECTROMAGNETIC ANALYSISMethodology

Vin(t) Vout(t)

Vin(freq)

(freq) (freq) Zc(freq)

Matched Load Impedances

Chain Matrix Vout(freq)

F.F.T.-1

+

* F.F.T = Fast Fourier Transform

F.F.T.

Page 11: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

ELECTROMAGNETIC ANALYSISApplication

Interconnection geometry and environment

0.8 m

M5

0.8 m

2.4 m

M5

7.3 m

passivation

SiO2

Si bulk 7cm 500 m

2.4 m

M5

7.3 m

passivation

SiO2

2nd configuration1st configuration 3rd configuration

Metal 5 : W=1 m

T= 1 mAluminium or Copper

Page 12: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

ELECTROMAGNETIC ANALYSISApplication

Frequency behavior of the attenuation factors

0

0.5

1

1.5

2

2.5

3

0 5 10 15 20 25 30Frequency (GHZ)

(

Np

/cm

)

1st configuration

2nd configuration

3rd configuration

Al

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0 5 10 15 20 25 30Frequency (GHZ)

(

Np

/cm

)

1st configuration

2nd configuration

3rd configuration

Cu

Page 13: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

ELECTROMAGNETIC ANALYSISApplication

Frequency behavior of the phase factors

0

2

4

6

8

10

12

14

16

18

20

0 5 10 15 20 25 30Frequency (GHZ)

(

rad

/cm

)

1st configuration

2nd configuration

3rd configuration

Al

0

2

4

6

8

10

12

14

16

18

20

0 5 10 15 20 25 30Frequency (GHZ)

(

rad

/cm

)

1st configuration

2nd configuration

3rd configuration

Cu

Page 14: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

ELECTROMAGNETIC ANALYSISApplication

Attenuation determination

Traveling wavex

AeA l

0

5

10

15

20

25

30

35

40

0 5 10 15 20Length (mm)

Atte

nuat

ion

valu

e

1st configuration

2nd configuration

3rd configuration

Al

0

5

10

15

20

25

0 5 10 15 20Length (mm)

Atte

nuat

ion

valu

e

1st configuration

2nd configuration

3rd configuration

Cu

Attenuation value of the wave, for 10 GHz, versus interconnection length

Page 15: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

Theoretical limits :

We have determined To determine x :

comparison output signal

between RC and RLCG models

x

lln

15

ELECTROMAGNETIC ANALYSISApplication

Page 16: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

OUTLINE OF THE TALK

Introduction

Theoretical limits

Electromagnetic analysis :- Methodology- Application

Limits between RLC and RC models

Illustration of the theoretical limits :- in frequency-domain- in time domain

Conclusion

Page 17: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

LIMIT BETWEEN RLC AND RC MODELS

The RLCG line model deduced from the electromagnetic analysis :

)..).(..(. CjGLjRj

..

..

CjG

LjRZc

240

260

280

300

320

340

360

380

400

0 5 10 15 20 25 30 35 40 45Frequency (GHZ)

R (

cm)

1st configuration

3rd configuration

2nd configuration

0

200

400

600

800

1000

1200

1400

1600

1800

0 5 10 15 20 25 30 35 40 45Frequency (GHZ)

C (f

F/cm

)

1st configuration

2nd configuration

3rd configuration

Page 18: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

These calculated values are used to build the distributed RC model

LIMIT BETWEEN RLC AND RC MODELS

n

Rline

n

Cline

.2 n

Cline

n cells

COMPARISON BETWEEN :

HSPICE simulations : RC modelElectromagnetic analysis : RLC model

Page 19: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

LIMIT BETWEEN RLC AND RC MODELS

Waveform of input and output signals in the range of lengths with inductance effect

2nd configuration - L=6 mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

0 50 100 150 200 250 300Time (ps)

Vo

lta

ge

(V

)

Vin

Vout1st reflection on the output

1st reflection on the input

2nd reflection on the output

Page 20: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

LIMIT BETWEEN RLC AND RC MODELS

Waveform of input and output signals in the range of lengths with inductance effect

2nd configuration - L=10 mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

0 50 100 150 200 250 300 350 400Time (ps)

Vo

lta

ge

(V

)

Vin

Vout1st reflection on the output

1st reflection on the input

2nd reflection on the output

Page 21: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

1st structure - L=10mm - Al

0

0.5

1

1.5

2

2.5

3

3.5

0 100 200 300 400 500 600

Time (ps)

Vol

tage

(V)

Input signal

Ouput RC model

Output RLC Model

1st structure - L=16 mm - Cu

0

0.5

1

1.5

2

2.5

3

3.5

0 100 200 300 400 500 600 700 800Time (ps)

Vo

ltag

e (V

)

Input Signal

Ouput RC model

Output RLC Model

LIMIT BETWEEN RLC AND RC MODELS

Attenuation determination :

Limit : the amplitude of the reflected wave is sufficiently low to give the reflection effect negligible

Page 22: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

OUTLINE OF THE TALK

Illustration of the theoretical limits :- in frequency-domain- in time domain

Theoretical limits :

We have determined x

x

lln

15

Page 23: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

Aluminium

0

0,5

1

1,5

2

2,5

3

0 5 10 15 20 25 30Frequency (GHz)

Lo

we

r li

mit

(m

m)

1st configuration

2nd configuration

3rd configuration

Copper

0

0,5

1

1,5

2

2,5

3

0 5 10 15 20 25 30Frequency (GHz)

Lo

we

r li

mit

(m

m)

1st configuration

2nd configuration

3rd configuration

Aluminium

0

10

20

30

40

50

60

0 5 10 15 20 25 30Frequency (GHz)

Up

pe

r li

mit

(m

m)

1st configuration

2nd configuration

3rd configuration

Copper

0

10

20

30

40

50

60

0 5 10 15 20 25 30Frequency (GHz)

Up

pe

r li

mit

(m

m)

1st configuration

2nd configuration

3rd configuration

ILLUSTRATION OF THEORETICAL LIMITSin the frequency-domain

Page 24: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

0 5 10 15 20 25 30 35 40 45 50Frequency (GHz)

Re

lati

ve

mo

du

le

0

0,5

1

1,5

2

2,5

3

0 100 200 300 400 500Time (ps)

Vo

lta

ge

(V

)

1

2

3

4

rtf

1Frequency Time domain

ILLUSTRATION OF THEORETICAL LIMITSin the frequency-domain

Page 25: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

Aluminium

0

5

10

15

20

25

30

0 20 40 60 80 100 120 140 160 180 200tr (ps)

Up

pe

r lim

it (

mm

)

1st configuration

2nd configuration

3rd configuration

Copper

0

5

10

15

20

25

30

35

40

0 20 40 60 80 100 120 140 160 180 200tr (ps)

Up

pe

r lim

it (

mm

)1st configuration

2nd configuration

3rd configuration

Aluminium

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 50 100 150 200 250 300 350tr (ps)

Lo

we

r lim

it (

mm

)

1st configuration

2nd configuration

3rd configuration

Copper

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 50 100 150 200 250 300 350tr (ps)

Lo

we

r lim

it (

mm

)

1st configuration

2nd configuration

3rd configuration

ILLUSTRATION OF THEORETICAL LIMITSin the time-domain

Page 26: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

OUTLINE OF THE TALK

Introduction

Theoretical limits

Electromagnetic analysis :- Methodology- Application

Limits between RLC and RC models

Illustration of the theoretical limits :- in frequency-domain- in time domain

Comparison with previous work

Conclusion

Page 27: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

COMPARISON WITH PREVIOUS WORK

The two figures of merit can be combined into a two sided inequality that determines the range of the length of interconnect in which inductance effects are significant :

C

L

Rl

CL

tr

2

.2

« Figures of Merit to characterize the Importance of On-chip Inductance »DAC 98, June 1998 

1st configuration :

R = 17300 /mC = 170 pF/mL = 490 nH/mG # 0

2nd configuration :

R = 17300 /mC = 63.6 pF/mL = 655 nH/mG # 0

Page 28: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

1st configuration - L=2mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

4

0 50 100 150 200 250Time (ps)

Vo

ltag

e (

V)

Vin

Vout

1st configuration - L=1mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

4

0 50 100 150 200 250 300Time (ps)

Vo

ltag

e (

V)

Vin

Vout

1st configuration - L=10mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

4

0 100 200 300 400 500Time (ps)

Vo

ltag

e (

V)

Vin

Vout

COMPARISON

WITH PREVIOUS WORK

1st configuration - Copper

0

5

10

15

20

25

0 20 40 60 80 100 120 140 160 180 200tr (ps)

Lim

it (

mm

)

Upper limit

Lower limit

DAC Limit

Page 29: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

2nd configuration - L=15mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

4

0 50 100 150 200 250 300 350 400Time (ps)

Vo

ltag

e (

V)

Vin

Vout

2nd configuration - L=25mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

4

0 100 200 300 400 500 600 700 800Time (ps)

Vo

ltag

e (

V)

Vin

Vout

2nd configuration - L=2mm - Cu

0

0,5

1

1,5

2

2,5

3

3,5

4

0 50 100 150 200 250Time (ps)

Vo

lta

ge

(V

)

Vin

Vout

COMPARISON

WITH PREVIOUS WORK

2nd configuration - Copper

0

5

10

15

20

25

30

35

40

0 20 40 60 80 100 120 140 160 180 200tr (ps)

Lim

it (

mm

)

Upper limit

Lower limit

DAC Limit

Page 30: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

CONCLUSION

A full-wave electromagnetic analysis have been presented

to build accurate interconnect models,

including inductance effects.

New limits for signal reflections due to inductance

for on-chip interconnections have been proposed.

Page 31: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

CONCLUSION

These limits have been illustrated

with typical interconnection geometries,

for Al and Cu wires.

This study shows evidence demonstrating that a range

exists for which inductance effects cannot be neglected

and requires a transmission line model.

Page 32: THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis

CONCLUSION

FUTURE WORK :

Interconnect coupling : taking into account

not only the coupling capacitance, but also

the impact of inductance and mutual inductance.