THz III-V HEMT Technology

J. A. del AlamoMicrosystems Technology Laboratories, MIT

International Wireless Symposium 2013Workshop on THz Material Growth, Device Fabrication and Modeling

Beijing, April 14, 2013

Acknowledgements: Dae-Hyun Kim, Jianqiang Lin, Tae-Woo Kim, Niamh WaldronSponsors: FCRP-MSD, Intel, SRC, ARLLabs at MIT: MTL, SEBL, NSL

2

Outline

1. High‐frequency III‐V HEMTs: megatrends

2. State‐of‐the‐art InGaAs HEMTs and fT analysis

3. The path to THz operation

Chen

1. III-V HEMT: record fT vs. time

3

• For >20 years, record fT obtained on InGaAs‐channel HEMTs• InGaAs‐channel HEMTs offer record balanced fT and fmax

Current record:fT=688 GHzfmax=800 GHzKim IEDM 2011 (Teledyne/MIT)

(and MHEMT)

fT=710 GHz, fmax=478 GHz Chen APEX 2013

Record fT III-V HEMTs: megatrends

4

• Over time: Lg↓, InxGa1‐xAs channel xInAs↑• Lg, xInAs saturated  no more progress possible?

Record fT III-V HEMTs: megatrends

5

• Over time: tch↓, tins↓• tch, tins saturated  no more progress possible?

6

2. State-of-the-art InGaAs HEMT

• In0.7Ga0.3As QW channelo tch = 10 nm o µn,Hall > 10,000 cm2/V‐sec

• In0.52Al0.48As barrier + In0.7Al0.3As spacer (Kim, EL 2011)

• Dual Si ‐doping (Kim, IEDM 2010)• Pt (3 nm)/Ti/Pt/Au Schottky

o tins=4 nm• InP etch stop (tInP=6 nm)• Lside=100 nm• Gate stem > 250 nm• Mo‐based S/D with 2 µm S‐D spacing

Kim, IEDM 2011

Lg=40 nm InGaAs Metamorphic HEMT

GaAs substrate

7

TEM cross section

GaAs Substrate

Graded Buffer

HEMT Epi

Buried Pt

Ti

Pt

Au

SG

D

8

Output and transfer characteristics

• Large current drive: ID>1 mA/µm at VDS=0.8 V• High transconductance: gmpk= 2.75 mS/μm at VDS=0.8 V • VT ≈ 0 V, RON=280 Ω.μm

Kim, IEDM 2011

0.0 0.2 0.4 0.6 0.8 1.00.0

0.4

0.8

1.2

0.5 V

I D [m

A/

m]

VDS [V]

VGS = 0.6 V

0.0 0.2 0.4 0.60

1

2

30.8 V

0.2 V

g m [m

S/m

]VGS [V]

VDS = 0.1 V

Lg=40 nmLg=40 nm

109 1010 1011 10120

20

40

Frequency [Hz]

Gai

ns [d

B]

0

1

2

3

4

Stability Factor (k)

High-frequency characteristics

9

• Only transistor of any kind with both fT and fmax > 680 GHz• Obtained at same bias point, VDS=0.6 V

Kim, IEDM 2011

fT = 688 GHzfmax = 800 GHz

VDS=0.6 V, VGS=0.4 V

h21

MSG

Ug

k

VDS=0.6 V, VGS=0.4 V

10

fT vs. fmax

0 200 400 600 800 10000

500

1000

1500

MIT/TSC HEMT Fujitsu HEMT NGAS HEMT SNU HEMT UCSB HBT UIUC HBT TSC HBT HRL HBT ETH HBT

max ff

f max

[GH

z]

fT [GHz]

300 600 700 = favg =

TSC/MIT(This work)

• Record fT FET• Best‐balanced fT and fmax transistor

Kim, IEDM 2010 (fmax=1.25 GHz)

Kim, IEDM 2011

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ft analysis

• First‐order fT expression for HEMT:

gmivgs

goi

RDRS

Cgs Cgd

S D

G

12

Break out extrinsic capacitances

• Capacitance components:

S

G

D

13

Delay time analysis

• Delay time:

• Components of delay time:

Intrinsic delay (transit time)

Extrinsic delay  Parasitic 

delay 

Extraction of parasitic capacitances

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• Need devices with different Lg• Bias them at same VGS overdrive around peak fT point• Extract small‐signal equivalent circuit models• Study Lg scaling behavior of Cgs and Cgd

0 100 2000

1000

2000

Cgs_ext

Cgs

, Cgd

[fF/

mm

]

Lg [nm]

VDS = 0.6 VVGS - VT = 0.3V

Cgs

Cgd

Cgd_ext

Kim, IEDM 2011

15

Delay components of Lg=40 nm InGaAs HEMT

Delay time from fT:    ~231 fs• Intrinsic delay:          ~81 fs• Extrinsic delay:        ~99 fs• Parasitic delay:         ~50 fs• Unaccounted:             ~9 fs

yields  <ve>=5x107 cm/s

most significant

Kim, IEDM 2011

16

Scaling of delay components

ext and par do not scale, become dominant for Lg< 50 nm 

0 100 2000

200

400

600VDS = 0.6 VVGS - VT = 0.3V

Del

ays

[fs]

Lg [nm]

Transit

ext

par

17

Scaling of small-signal components

0 100 2000

1000

2000

Cgs_ext

Cgs

, Cgd

[fF/

mm

]

Lg [nm]

VDS = 0.6 VVGS - VT = 0.3V

Cgs

Cgd

Cgd_ext

do not scaledo not scale

↑

As Lg↓:

↓

• Intrinsic delay↓  Lg ↓ 

• Extrinsic delay↓:

Cgsext, Cgdext ↓  gate engineering gmi ↑ harmonious scaling

• Parasitic delay↓:

RS+RD ↓  S/D engineering goi/gmi↓  harmonious scaling

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3. The path to THz operation

19

How to reach ft = 1 THz?

fT = 1 THz feasible by: scaling to Lg ≈ 25 nm ~30% parasitic reduction

100200

400

600

800

1000

1200

VDS = 0.6 V

30% reductionin all the parasitics

Measured fT

Modeled fT

Model Projection

f T [GH

z]

Lg [nm]

1 THz

30

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.2

0.4

0.6

0.8

1.0

0 V

0.1 V

0.2 V

0.3 V

0.4 V

I D [m

A/

m]

VDS [V]

VGS = 0.5 V

Approach to RS+RD↓: self-aligned process

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• Dry‐etched Mo contacts: Rc = 7 Ω.μm• Lg=50 nm, RON=290 Ω.μm, gmpk=2.2 mS/μm @ VDS=0.5 V

Lside=100 nm

Kim, IEDM 2010Waldron, TED 2010

Lg=50 nm

1 10 100 10000

20

40

K

MAG/MSG

Ug

Measured data Modeled data

H21

, MA

G/M

SG a

nd U

g [dB

]

Frequency [GHz]K

VGS = 0.2 V, VDS = 0.6 VH21

0

1

2

3

4

Lg=60 nm self-aligned In0.7Ga0.3As HEMT

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Highest fT and fmax of any FET at Lg 60 nm 

Kim, IEDM 2010

Lg=60 nm

fT=595 GHzfmax=680 GHz

Lg=30 nm self-aligned InGaAs MOSFET with Lside~30 nm

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gmpk=1.4 mS/μmRON=475 Ω.µm  access region design critical!

Lin, IEDM 2012

0.0 0.1 0.2 0.3 0.4 0.50

200

400

600

I d (A

/m

)Vds (V)

Vgs = -0.2 to 0.5 V in 0.1 V stepRon=475 m (at Vgs =0.7 V)Lg = 30 nm

Lside~30 nm

Regrown source and drain regions

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Lch=30 nm InGaAs MOSFET: RON=133 Ω.µmZhou, EDL 2012

Lch=55 nm InGaAs MOSFET: RON=199 Ω.µm

Egard, IEDM 2011

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Harmonious scaling:aspect ratio of record ft devices

Dimensions verified by XTEM

• Channel AR: 3 ~ 4• Insulator AR: 7 ~ 10

Channel Aspect Ratio: Lg/tch Insulator Aspect Ratio: Lg/tins

For Lg=25 nm:  tch~ 7 nm, tins~ 3 nm

25

Issues in channel scaling

Deep channel thickness scaling degrades performance: RS ↑  fT ↓

Kim, IPRM 2010

InAs HEMT, Lside = 80 nm, tins = 5 nm

Noticeable mobility degradation:  tch=10 nm  µe=13,500 cm2/V.stch=5 nm    µe=9,950 cm2/V.s

vinj - impact of channel thickness

In thin‐channel devices:• Long Lg: vinj decreases right along with e (~23%)• Short Lg: vinj relatively unaffected  

consistent with near ballistic transport

10 1000

1

2

3

4

tins = 3 nm & tch = 5 nm

tins = 4 nm & tch = 10 nm

Strain-Si

(VDS = 1.1 ~ 1.3 V)Si nFETs

n ~ 13,000 cm2/V-s

n ~ 9,950 cm2/V-s

v inj [1

07 cm

/s]

Lg [nm]

VDS = 0.5 V

Kim, IEDM 2009

26

27

Channel transport enhancement through strain engineering

InAs 300 K quantum‐well mobility vs. lattice constant: 

InP AlSbInAs InSb

Independent control of channel strain and composition: new possibilities for channel design

28

Issues in barrier scaling

Kim, TED 2008

In0.7Ga0.3As HEMTstch=13 nm, Lside=150 nm 

For harmonious scaling: as Lg↓  tins ↓

Want to scale Lg without degrading gm or go

29

Limit to HEMT barrier scaling: gate leakage current

InAlAs/InGaAsHEMTs

At Lg=40 nm, modern HEMTs are at the limit of scaling!

Lg=40 nmVDS=0.5 V

30

Limit to HEMT barrier scaling: gate leakage current

Need high‐K gate dielectric: HEMT MOSFET!

InAlAs/InGaAsHEMTs

Al2O3 (3 nm)/InP (2 nm)/InGaAsMOSFET

10‐5x!

VDS=0.5 VLg=40 nmVDS=0.5 V

III-V MOSFET: deep scaling possible

-0.2 0.0 0.2 0.4 0.610-11

10-10

10-9

10-8

10-7

10-6

S=69 mV/dec

Vds=0.5 and 0.05 VLg= 300m

I d (A

/m

)

Vgs (V)

31

S=69 mV/dec Low Dit at MOS interface demonstrated

Lin, IEDM 2012

InP (1 nm) + Al2O3 (0.4 nm) + HfO2 (2 nm)  EOT ~ 0.9 nm[vs. 4 nm InAlAs EOT = 1.3 nm] should bring us to Lg=20 nm

Long‐channel In0.53Ga0.47As MOSFETμe ≈ 2700 cm2/V.s

Equivalent oxide thickness

High-frequency InGaAs MOSFETs

32

ft=370 GHz, RON=220 Ω.µm, gm=2.0 mS/µm, S=110 mV/dec

Kim, APL 2012Lg=60 nm InGaAs MOSFET with Lside~5 nm, EOT=1.2 nm

Lg=60 nmVDS=0.5 V

THz MOSFETs: possible designs

33

n+n+

Regrown S/D QW‐MOSFET

FinFET Gate‐all‐around nanowire FET

Etched S/D QW‐MOSFET

34

Conclusions

• THz III-V FETs just around the corner need to reduce parasitics need to scale harmoniously

• Exploding interest on III-V CMOS: huge opportunity for THz III-V electronics! fast technology progress new processes and tools fundamental research on transport, interface, etc. Si as substrate for THz electronics