1. Phn loi tp lnh ASM-PIC Pic dng mid-range c tp lnh 14 bt gm c tng cng 35 lnh, c th phn chia thnh 4 nhm lnh ty thuc vo loi / s ton hn m lnh thc hin: Lnh thao tc trn con tr 7 bit ch n vng nh RAM. f: con tr 7 bit d: ch nh thanh ghi dng cha kt qu thc hin lnh. 0 cha trong thanh ghi W, 1-cha trong thanh ghi c tr ti bi con tr f Lnh x l s 8 bit k: d liu c di 8 bit Lnh thao tc trn thanh ghi chng trnh 11 bit. a: con tr ch n vng cha chng trnh Lnh x l bt cha trong thanh ghi c tr bi con tr 7 bit ch n vng nh RAM. b: s th t bit cha trong thanh ghi m lnh tc ng.2. Ch nh a ch-khi truyn ton hn cho cc lnh

- Ch tc thi (intermediate addressing): gi tr ca d liu ng vai tr ton hn cho cc lnh.- Ch trc tip: a ch ca thanh ghi ng vai tr ton hn ca lnh c truyn trc

tip.- Ch gin tip: a ch ca thanh ghi ng vai tr ton hn c truyn cho lnh gin

tip qua thanh ghi a ch d liu (data address registers)- i vi dng PIC mid-range th FSR v INDP (special select registers) chnh l cc thanh ghi a ch d liu. Cn ch : do vng nh RAM ca PIC c chia theo bank, nn trc ht phi chn bank cha thanh ghi mun truy xut n. Cch thc chn bank li ph thuc vo ch nh a ch thanh ghi truyn cho lnh cn s dng.

1

+ Nu nh a ch trc tip th chn bank bng cch thay i gi tr cc bit RP1,RP0 cha trong thanh ghi STATUS. Cch khc l dng lnh banksel thanh ghi cha trong bank cn lm vic. +Nu nh a ch gin tip th lm theo cc bc sau: Step1: chn bank bng cch thay i bit IRP (0 bank 0,1 1-bank 2,3) cha trong thanh ghi STATUS. Step2: Gn gi tr cho thanh ghi FSR vi gi tr c gn = gi tr a ch nh cn tr ti OR logic vi b10000000 (tc t bit cao nht ca a ch nh cn thao tc ln 1) bng lnh iorlw Step3: movlw gi tr cn gn vo nh s trc tr gin tip. Step4: movwf INDF (INDF: thanh ghi cha i ch con tr vng nh cn tr ti lnh tc ng ln. Khi mt lnh khng c cha a ch ca vng nh cn thao tc tc l trong ch nh a ch gin tip- th khi INDF ng vao tr l i s truyn chho lnh th lnh s t tr ti a ch cha trong thanh ghi FSR theo qui tc bit cao nht nng ln 1 nh Step2). VD: Given a PIC16F873 microcontroller, place the value 0x35 in the register 0x20 of bank 1. Do this task using direct and indirect addressing. Ch nh a ch trc tip: bcf bsf STATUS, RP1 STATUS, RP0 ; chn bank1

movlw 0x35 movwf 0x20 nh a ch gin tip:2

; nh a ch trc tip

bcf movlw

STATUS, IRP 0x20

; chn bank1 khi dng phng php nh a ch gin tip

movwf SFR movlw b10000000 iolwf SFR,1

; chuyn trc gi tr 0x20 = a ch nh cn tr ti vo SFR

; dng pp masking nng bit cao nht ca SFR ln 1 bng lnh OR logic vi kt qu c ch nh gn cho SFR

movlw

0x35 ; Gn gi tr 0x35 bng pp nh a ch trc tip thgn qua thanh ghi INDF tr ti thanh ghi SFR tr ti a ch 0x20 cn gn gi tr

movwf INDF

3. STACK c im STACK trong PIC mid-range:- Vng nh STACK tch bit khi vng nh data v program v c su ti a = 8. - Ch cha a ch thanh ghi chng trnh PC tr v sau khi kt thc mt chng trnh con

hoc ngt c di 13 bit - Cha ti a 8 a ch => ch cho php lng ti a 8 chng trnh con vi nhau. Nu lng nhiu hn 8 s gy li nghim trng do khng c c ch qun l trn STACK- T ng tng khi PUSH data vo STACK, t ng gim khi POP data ra khi STACK

4. NHM LNH TON HC V LNH LOGIC - Cc lnh ton hc bao gm: tng, gim, cng tr tc ng ln cc c C, DC, Z trong thanh ghi STATUS.- Cc lnh LOGIC gm AND, OR, XOR, ly b, xoay tri phi, o nibble s tc ng ln

c Z trong thanh ghi STATUS, lnh xoay tc ng ln c C v lnh o nibble khng tc dng ln bt k c no.- Cc lnh ton hc v logic s dng 2 ton hn th phi c mt ton hn cha trong thanh

ghi W, ton hn cn li cha trong thanh ghi bt k c th nh a ch trc tip hoc gin tip (INDF, FSR) , kt qu tnh ton c c th gn cho thanh ghi W hoc thanh ghi cn li bng cch ch nh bit d trong opcode.3

-

Khng c lnh s hc cng hoc tr vi s tham gia ca c nh C mt cch trc tip, nu mun thc hin th phi vit thm code xt c C.

5. NHM LNH R NHNH CHNG TRNH a. Nhm r nhnh khng iu kin

Khi ni n nhm lnh nhy cn ch :- Thanh ghi chng trnh PC 13 bit => c kh nng tr n 8K a ch, mi lnh ca dng

PIC Mid-range 14 bit => Vng nh chng trnh c kch thc ti a 8K x 14 => chia lm cc trang 2Kx14 do trong ton hn ca cc lnh nhy ch l thanh ghi chng trnh truyn ng vai tr ton hn ch c 11 bit=> nu ch n thun dng 11 bit a ch ny ch nhy trong phm vi 2K b nh chng trnh (tc trong 1 trang). Do nu trong chng trnh c lnh nhy gia cc on chng trnh lu trn nhiu page th cn phi c thm 2 bit qui nh page cn nhy ti, 2 bt ny ly trong thanh ghi PCLATH (4,3) ( program counter latch high). - Nu chng trnh thc hin theo tun t cc cu lnh m khng c lnh nhy th khng cn quan tm n vic phn chia trang trong Program memory.

4

Thc hin:

movlw HIGH Prog10 ; ly a ch 8 bit cao ca thanh ghi PC cha chng trnh con Pro10 movwf PCLATH ; gn 8 bit cao ny cho PCLATH => PCLATH(4,3) s cha page tng ng vi chng trnh con Prog10, sau gi CALL Prog10 th trnh bin dch s t ng cp nht page tng ng ly t PCLATH(4,3). movlw LOW Prog10 : ly gi tr 8 bit thp ca vng nh ch n chng trnh con Prog10 movwf PCL ; gn gi tr 8 bit thp va ly c gn cho thanh ghi PCL cha 8 bit thp ca thanh ghi PC, sau khi thc hin lnh gn ny, chng trnh s lp tc nhy n on m bt u bng a ch PC = PCLATH_PCL5

Khi kt hp vic thay i gi tr thanh ghi PC hp l, c th thc hin nhy m khng s dng lnh nhy trong tp lnh c sn. Tuy nhin ng dng thng dng nht ca k thut ny l to cc bng tra. V d: Chng trnh tnh bnh phng 1 s t 0 -> 9 c cha ti a ch RAM a dng t tn l SO (s), cha kt qu ti a ch c t tn KETQUA ; CHNG TRNH TM BNH PHNG S T 0-9 DNG BNG TRA Main: bcf bcf STATUS,RP0 STATUS,RP1 ; chn vng lm vic trong bank0 ca RAM

movlw 7 movwf SO ; gn tr cho s cn ly bnh phng movlw 0 movwf KETQUA movlw HIGH BANGTRA ; chn page ca vng nh chng trnh cha chng trnh con BANGTRA movwf PCLATH movf SO,0 call BANGTRA movwf KETQUA GOTO KETTHUC BANGTRA: addwf PCL retlw 0 retlw 1 retlw 4 .... retlw 81 KETTHUC: END b. Nhm r nhnh c iu kin Trong PIC mid-range ch cung cp cc lnh r nhnh c iu kin sau: tbfsc , tbfss : xt bit b qua nu set hoc clear decfsz, incfsz : tng/ gim thanh ghi b qua cu lnh tip theo nu bng zero6

; gn gi tr trong nh SO cho thanh ghi W

Vi iu kin r nhnh da vo gi tr ca 1 bit trong 1 thanh ghi do ngi s dng ch nh.

6. Nhm lnh qun l bit Ch c 2 lnh: bfs : set bit ln 1 bfc: clear bit v 0 7. Nhm lnh khc 8. Fdfd

II. LP TRNH BNG MPLAB ASM

1. Cc thnh phn trong mt chng trnh vit bng MPLAB ASM- Lnh, tun theo cc qui nh trong tp lnh ASM ca PIC - Ch th cho chng trnh dch ASM : cc lnh ny s tc ng n trnh dch ASM ch

khng tc ng lnh PIC, trnh MPLAB ASM s c tp ch th ring ca n. Cc ch th thng dng l nh ngha bin (EQU) , nh v tr thanh ghi PC cha mt on chng trnh trong b nh chng trnh (ORG)...7

- Nhn: l tn t cho mt nhm lnh thc hin mt chc nng c th, mi khi mun thc

hin chc nng th ch cn nhy (GOTO) hoc gi (CALL) nhn tng ng.

Hng v qui c vit hng s trong MPLAB ASM, hng s c th m (-) hoc dng (+)

Symbol: tn t cho mt hng s, s dng ch th EQU nh ngha hng s. C th t du - trc symbol ly gi tr m ca n.

- MPLAB cung cp sn cc nh ngha tn cc thanh ghi SFRs v cc bit c chc nng c

bit trong file P16F887.inc . Trong chng trnh cn dng ch th #include P16F887.inc trc khi s dng.8

- Biu thc (expression) : c to thnh t cc symbol, hng s, kt hp vi cc lnh

tinh1 ton s hc hoc logic, phn cch bng cp du ngoc (). Biu thc c th ng vai tr tham s cho cc lnh, khi gi tr ca biu thc s l tham s gn cho lnh. nh ngha symbol REG1 c gi tr l 20h Biu thc REG1+1 c gi tr l 21h s ng vai tr tham s cho lnh movwf => gi tr ca thanh ghi w s gn cho thanh ghi c a ch 21h

- Cc ton t c nh ngha trong MPLAB ASM thc hin tnh ton trn cc thanh ghi 32 bit, kt qu cui cng s c xn cho ph hp kch thc ca nh cha kt qu tnh ton.

V d: DATA1 EQU .18 DATA2 EQU .7 movlw DATA1%DATA2 ; gi tr ca thanh ghi w s l 4

DATA EQU .3 movlw -DATA ; khi thanh ghi w s c gi tr b 2 ca s 3 w=0xFD

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- Php ton trn cc bit

- Lnh gn:

10

V d:DATA EQU .10 REGISTER EQU 0x20 movlw DATA movwf REGISTER DATA+=5 REGISTER++ movlw DATA movwf REGISTER gn gi tr thp phn 10 cho symbol DATA gn gi tr 20h cho symbol REGISTER Chuyn gi tr ca DATA cho thanh ghi c a ch REGISTER DATA= DATA+5 REGISTER=REGISTER+1

- Ton t thao tc vi a chi: ton hn ca cc ton t loi ny l a ch ca vng nh chng trnh.

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$ : nhy ti ch low label : tr v 8 bit thp [0-7] ca vng nh chng trnh bt u t nhn label high label : tr v 8 bit cao [8-15] ca vng nh chng trnh bt u t nhn label upper label : tr v 6 bit cao nht [16-21] ca vng nh chng trnh bt u t nhn label

2. CH TH ( DIRECTIVE ) TRONG MBLAP ASM Directive qui nh cch thc thc hin ca trnh bin dch, directive c cc ton hng ring ca n,cc ton hn ca mt directive s cch nhau bi du phy (,) . Dng tng qut ca mt directive:

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SET : nh ngha mt bin, gi tr ban u gn cho bin khi khai bo c th thay i trong qu trnh thc hin chng trnh.

EQU : nh ngha mt hng, gi tr ca hng khng c thay i trong sut qu trnh thc hin chng trnh.

CH : - Theo khuyn co ca Microchip , khi chng trnh dc bin dch dng Absolute (tc khng c s dng trnh lin kt linker) th EQU c dng nh ngha tn ca cc thanh ghi d liu trong vng GENERAL PURPOSE.

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- Khi dng chng trnh bin dch ra dng m Relocatable object code th khng nn dng EQU nh ngha cc thanh ghi trong vng GENERAL PURPOSE m phi dng directive RES c bao trong khi UDATA hoc UDATA_SHR ???

V d: DATA SET .15 REGITER1 EQU 0x20 REGISTER2 EQU 0x21

movlw DATA movwf REGISTER1 DATA++ ; do DATA c khai bo vi SET nn gi tr c th thay i c movlw DATA movwf REGISTER2

Directives for relocatable code: Relocatable code l nhng chng trnh khi bin dch cn thm chng trnh linker, trong on m relocatable khng s dng bt k a ch RAM/ROM no. Cc directive bao gm: nh v tr khi u ca ca d liu hoc khi lnh (instruction block) [label] code [program memory (ROM) address] t tn cho mt on m chng trnh, nu khng ch nh program memory address th trnh lin kt linker s t cp pht khi tin hnh hp dch [label] udata [RAM address] udata=uninitialized data : nh v vng nh ca cc bin c khai bo tip sau s nm trong cng 1 bank, v khi gn vng nh s khng gn gi tr khi u. Nu khng ch nh RAM address th linker s t gn. [label] udata_shr [RAM address] udata=shared uninitialized data : nh v vng nh 14

ca cc bin c khai bo tip sau s nm trn nhiu bank, v khi gn vng nh s khng gn gi tr khi u. Nu khng ch nh RAM address th linker s t gn. [label] res [memory size] nh ngha mt bin c tn l label c kch thc memory_size v khng c gi tr khi to bin.

Cc bin REG1 v REG2 c nh ngha c kch thc 1 byte, khng c tr khi to v c t trn cc bank khc nhau do trnh linker chn. nh phm vi vng nh cha cc bin d liu phc v cho chng trnh. nh phm vi hot ng ca cc symbol trong cc on m khi chng trnh gm nhiu on m khc nhau (external hay global) global symbol1, symbol2.... global khai bo mt symbol (tn subroutine, bin, hng s) l ton cc c th c s dng trong cc on chng trnh khc. extern symbol1,symbol2..... extern khai bo vic s dng mt symbol ton cc c khai bo u trong cc file cng mt project s c linker. Chn program memory page hoc data memory bank pagesel label ch n ROM page cha an chng trnh c gn nhn label (lm thay i ni dung PCLATH) banksel label ch n RAM bank cha bin c gn nhn label (lm thay i ni dung thanh ghi STATUS) bankisel label

V d 1: list p = 16f873 #include p16f873.inc ; Khai bo cc hng s DATA1 equ 0x55 DATA2 equ .10 ; Khai bo cc bin c kch thc 1 byte , khng c gi tr khi to, cha trn nhiu bank udata_shr REG1 res 1 ; REG1 is register 20h in the data memory. 15

REG2 res

1

; REG2 is register 21h in the data

; Programs _ Khai bo on chng trnh bt u ti nh 0H trong ROM Rst_vector code 0 pagesel PP ; Select page where PP is located. goto PP ; This guarantees branching to ; correct address. Prog_Principal code ; on chng trnh c tn l Pro_principal c v tr trn ROM do linker cp PP: pagesel SRoutine ; Select page where subroutines are located call SRoutine ; guaranteeing branching to correct location. ; Operate with registers TRISB and PORTB using direct address: banksel TRISB ; Select bank 1 because TRISB is in this bank. This assures the correct addressing for TRISB. clrf TRISB ; Work with TRISB. banksel PORTB ; Return to Bank 0, because PORTB is located in this bank. movf PORTB, DATA1 ; Work with PORTB. ; Operate with REG1 using indirect address: movlw REG1 movwf FSR ; Stored address of REG1 in FSR. bankisel REG1 ; Select bank where REG1 is located. movlw DATA2 ; Write 10 in movwf INDF ; REG1 using indirect addressing. SRoutine: ; ; Write here subroutine instructions. ; return end

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V d 2: on chng trnh c vit theo kiu module nh sau: - Chng trnh chnh cha trong 1 file ring s gi hm DELAY c nh ngha trong chng trnh con c vit trong 1 file ring. - Chng trnh chnh s truyn cho chng trnh con 1 bin c tn l REG chng trnh con DELAY c gi s nhn bin ny lm s ln lp. ; Main program module. ; Examples of using directives global and extern. list p = 16f873 #include p16f873.inc udata_shr REG res 1 ; Define symbol REG. global REG ; Symbol REG declared asglobal in this ; module ; and external in the subroutine module. ; Subroutine module (file sr.asm): ; Subroutine program module. ; Examples of using directives global and extern.

list p = 16f873 #include p16f873.inc global Delay ; Symbol Delay defined global in; and external in the main program

this module module.

externthis module

REG ; Symbol REG declared external in

extern Delay ; Symbol Delay defined external in this module ; defined and declared global in subroutine module.; The call to subroutine Delay is in one of the sections in the main

; and global in the main program. ; The call to subroutine Delay is in one of the sections in the main program.

; program (for example, in the Program

Section).

Program

code

Program code Delay: decfsz REG,1 goto Delay return ; end

movlw 35h movwf REG call Delay end

Macrointruction: l tp hp cc lnh v ch th ca trnh bin dch, lm mt chc nng c th, khi c nh ngha macro c th c gi v thi hnh nh mt instruction. nh ngha mt macro dng cu trc sau: macro_name macro [arg_def1, arg_def2,] [ local label [, label, label,]] ; ; Body of macroinstruction ; endm Gi macro: Macro_name [arg1, arg2,] 17

- arg1, arg2 ..: i s truyn cho macro. i s c th l symbol hoc mt biu thc - Bn trong macro c th khai bo cc bin local phc v cho vic thc hin tnh ton. V d 3: Vit mt macro thc hin cng vic sau: nhn mt s HEX c gi tr t (0..F) cha trong bin HEXA, chuyn thnh m ASCII tng ng ri gn kt qu chuyn i vo bin ASCII ( nu HEXA < 9 th cng 30h, nu HEXA > 9 th cng 37h !!!) list p = 16f873 #include p16f873.inc ; Macro definition: ; ; This macro converts an hexadecimal digit (0 to F) located in register called HEXA into its equivalent ; ASCII character. The ASCII digit is then stored in the register called ASCII. ; Convert macro HEXA, ASCII ; macro c tn Convert nhn 2 i s l HEXA v ASCII local add30, add37, end_mac ; nh ngha cc nhn cc b movf HEXA, W ; Store hex digit in HEXA sublw 9 ; W > 9 ? (affects STATUS). movf HEXA, W ; Store hex digit in W (does not affect STATUS). btfsc STATUS, C ; Yes (C = 0), add 37h to HEXA. goto add30 ; No (C = 1), add 30h to HEXA. add37: addlw 37h goto end_mac add30: addlw 30h end_mac: movwf ASCII endm ; Data memory registers: udata_shr HEXA1 res 1 HEXA2 res 1 ASCII1 res 1 ASCII2 res 1 ; Programs Rst_vector code 0 pagesel MP goto MP ; on m chng trnh c label l Rst_vector t ti a ch 0h trong ROM ; Select page where MP is located ; to guarantee correct branching. ; on m chng trnh chnh t ti a ch 0x800 ROM ; cc bin c nh ngha c th cha trn nhiu bank , khng c khi to gi tr

; Store result in register ASCII. ; End of macro.

Main_Program code 0x800 MP: movlw 9

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movwf HEXA1 movlw 0Ah movwf HEXA2 Convert HEXA1, ASCII1 ; nop ; Convert HEXA2, ASCII2 nop goto $ end ; Call macro Convert again. ; Call macro Convert. Assembler program will introduce here ; the instructions for the macro.

; Infinite loop. ; End of program.

CU TRC MT CHNG TRNH ASM im ch nh v a ch ROM cha m chng trnh Absolute Code Buc phi ch nh c th a ch ROM bt u bng directive org Relocatable Code nh a ch ROM bng directive code. - Bt buc nh a ch cho chng trnh con RESET ti a ch ROM 0h - Bt buc nh a ch chng trnh con cho ngt ti a ch ROM 04H - Cc on chng trnh cn li khng bt buc nh a ch ROM

nh a ch cho symbol

equ set

udata, udata_shr res

Cu trc chng trnh theo th t sau: 1. Ch nh loi VXL dng cho project bng directive list v #include 2. nh ngha cc macro s dng trong chng trnh. 3. nh ngha cc symbol biu din cc hng s dng trong chng trnh bng directive equ v set 4. nh ngha cc bin symbol dng trong chng trnh _ cc bin ny cha trong Gerneral purpose RAM 5. Chng trnh chnh 6. Chng trnh con _ subroutines. 7. Kt thc chng trnh bng directive end

PHN BIT MACROINSTRUCTION V SUBROUTINEMacroinstruction v Subroutine ch khc nhau trong qu trnh bin dch.

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- Macroinstruction : ti nhng ni gi macro, trc khi bin dch th on m tng ng s c thay th vo v tr macro c gi. - Subroutine: on m chng trnh subroutine c bin dich cng vi chng trnh chnh, khi c lnh gi Subroutine th chng trnh s nhy ti v tr Subroutine thc hin , xong ri quay tr li chng trnh chnh. - Trong chng trnh gi cng nhiu ln macro th m chng trnh cng ln, trong khi gi bao nhiu ln subroutine i na th m chng trnh khng b phnh ra nhiu nh macro. - Khi s dng subroutine th cn 3 yu t: lnh gi subroutine, stack cha trng thi chng trnh trc khi nhy vo subroutine, lnh tr li chng trnh chnh (hoc chng trnh subroutine m cha subroutine ang lm vic - nu s dng subroutine lng nhau). C th lp mt tp th vin cha nhng subroutine dng thng xuyn v lin kt vi chng trnh cn s dng bng trnh linker. - Do s hn ch ca b nh chng trnh trong VXL, thng u tin dng subroutine hn l macro.

V d 4: Chng trnh dng absolute code ; Vng khai bo vxl, cc ch khi to ;khi star uplist p = 16f873 #include

Chng trnh dng relocatable code ; Vng khai bo vxl, cc ch khi to ;khi star uplist p = 16f873 #include

; Vng khai bo cc hngDATA1 DATA2 EQU 0x1 ; EQU 0x2 ;

; Vng khai bo cc hngDATA1 DATA2 equ 0x1 equ 0x2

; Vng khai bo cc bin (genera ;purposed RAM)w_temp equ 0x20 ; Variable used to store W. status_temp equ 0x21 ; Variable used to storeSTATUS

; Vng khai bo cc bin (genera ;purposed RAM)udata_shr w_temp res 1 ; Variable used to store W. status_temp res 1 ; Variable used to store STATUS. X res 1 ; Example. Y res 1 ; Example.

X Y

equ 0x22 equ 0x23

; Example. ; Example.

; Thn chng trnhorg 0x000 ;Reset vector address. movlw high PP ; Prepare branch to main program, movwf PCLATH ; guaranteeing correct address. goto PP ; Go to address where main program starts. 20

; Thn chng trnhRst_vector code 0 ; Reset vector in address 0 pagesel PP ; Prepare branch to main program goto PP ; branch to address where it starts.

org 0x004 ; Interrupt vector address. movwf w_temp ; Save current content of W. movf STATUS, W ; Copy current STATUS in W, bcf STATUS, RP0 ; Assure selection of bank 0 movwf status_temp ; and save content in STATUS ; Write here subroutines for interrupt requests. bcf STATUS, RP0 ; Assure selection of bank 0 movf status_temp, W ; Recall copy of STATUS movwf STATUS ; and write it back. swapf w_temp, f ; Recall copy of W swapf w_temp, W ; and write it back without altering STATUS. retfie ; Return from interrupt. PP: clrf X clrf Y ; Initialize variables. ; Initialize variables.

Intr_vector code 4 ; Interrupt vector in address 4 goto SR_Int ; Branch to interrupt subroutine. Intr_Prog code 5 ; Section with interrupt subroutine. SR_Int: movwf w_temp ; Save current content of W. movf STATUS, W ;Copy current content of STATUS in W. bcf STATUS, RP0 ; Assure selection of bank 0 and;save content of STATUS.

movwf status_temp ; Write here instructions for interrupt subroutine. bcf STATUS, RP0 ; Assure selection of bank 0. movf status_temp, W ; Recall copy of STATUS movwf STATUS ; and write it back. swapf w_temp, f ; Recall copy of W. swapf w_temp, W ; Write it back without altering STATUS. retfie ; Return from interrupt. Prog_Principal code ; Write main program here PP: clrf X ; Initialize variables. clrf Y ; Initialize variables. ; Write here instructions for main program. pagesel SR1 ; Select page where SR1is located. call SR1 ; Call subroutine SR1. ; Write here instructions for main programl. goto $ ; Example: infinite loop

; Write here instructions of the main program. movlw high SR1 ;If SR1 is in a different page movwf PCLATH ; guarantee selection of correct page call SR1 ; and call subroutine. ; Write here instructions of the main program goto $ ; Example: infinite loop to finish main program.

; on m cha chng trnh conSR1: ; Beginning of subroutine SR1.

; on m cha chng trnh conSubroutines code ; Section for subroutines. SR1: ; Beginning of subroutine SR1. ; Write here instructions for subroutine SR1. pagesel SR2 ; Example: From subroutine SR1 call SR2 ; call subroutine SR2. ; Write here instructions for subroutine SR1. return SR2: ; Return to main program. ; beginning of subroutine SR2.

; Write here instructions for subroutine SR1.

movlw high SR2

; Example: Call subroutine 2 ; that is in another page

movwf PCLATH ;guarantee selection of correct page call SR2 ; and call subroutine SR2. return ; Return to main program from SR1.

; Write here instructions for subroutine SR2. SR2: ; Beginning of subroutine R2.

; Write here instructions for subroutine SR2. return end ; Return to SR1 from SR2. ; End of source program. 21

; Write here instructions for subroutine SR2.

return end

; Return to subroutine SR1. ; End of source code.

Nhn xt: Nhn xt: Ch absolute code: Ch relocatable code: +Khai bo 1 subroutine ch bng cch t + Khai bo subroutine bng nhm lnh sau: nhnSubroutines code ;Linker t pht ROM cha Subroutines. ; Tn ca subroutine. +Gi mt subroutine hoc macro lun phi SR1: SR1:

t xc nh ROM page cha m chng + Gi Subroutine,macro th ROM page xc trnh bng nhm lnh sau: nh nh sau:movlw high SR1 ;If SR1 is in a different page movwf PCLATH ; guarantee selection of correct page call SR1 pagesel SR1 ; Select page where SR1is located. call SR1 ; Call subroutine SR1.

3. DSDS

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VO / RA SONG SONG

1. K thut truyn d liu xut/ nhp

Thnh phn c bn ca mt cng vo/ ra l D-latch (phn t cho php nh trng thi ca bit) Cu to ca 1 D-latch + cng 3 trng thi nh sau: DI : d liu vo DO: d liu ra STB: xung iu khin xut nhp- xung strobe OE#: ng iu khin cng ra 3 trng thi tch cc mc thp

Hot ng xut nhp d liu c chia lm 2 loi: - Nhp xut n gin- Nhp xut c iu khin (controlled input/output) cn gi l handshake

Trong xut nhp n gin, d liu c truyn gia cng v ngoi vi s dng nhiu nht l mt tn hiu xung strobe (STB) bo hiu l d liu sn sng cho vic xut nhp.

Trong xut nhp c iu khin (handshake) th phi bao gm t 2 tn hiu iu khin cho vic xut nhp (STB do bn pht d liu to ra v ACK do bn thu to ra) + giao thc truyn - nhn d liu.

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Xut nhp c iu khin theo giao thc n gin gm 3 bc: - Bn pht khi pht hin ACK=0 (bn thu ang ri) s pht d liu v t tn hiu STB ln mc 1 bo cho bn thu c d liu. - Bn thu khi bit c tn hiu gi ln bng cch kim tra STB s nhn d liu v bo cho bn pht l ang nhn d liu bng cch t ACK ln 1. - Bn pht s khng pht d liu cho n khi bn thu bo rng nhn xong d liu trc bng cch t ACK =0.

Xut nhp c iu khin theo giao thc phc tp hn. - Bn pht s bo hiu cho bn thu rng sn sng pht (nhng cha pht) bng cch t STB ln 1 - Bn thu khi nhn c tn hiu STB=1 nu sn sng nhn th s bo cho bn pht bit bng cch t ACK=1 - Bn pht s pht d liu cho bn thu v s t STB xung 0 khi pht xong. - Bn thu sau khi nhn xong d liu s bo cho bn pht bit bng cch t ACK=0

Vic qun l xut nhp d liu ra cc port trong PIC mid-range theo giao thc no th s c thc hin bng phn mm, do PIC mid-range khng h tr phn cng qun l giao thc truyn nhn d liu ra cc port. ??? I2C / RS232 ???

2. K thut xut nhp d liu gia VXL vi ngoi vi Phn chia lm 2 loi : loi c lp trnh qun l bng chng trnh phn mm v loi thng qua ngt qun l bng phn cng ca vi iu khin.

a. Xut nhp d liu vi ngoi vi bng phng php lp trnh Gm 2 loi : polling I/O v waiting I/O

Polling I/O VXL s gi tn hiu yu cu xut/nhp d liu cho ngoi vi.

Waitng I/O VXL s gi tn hiu yu cu xut/nhp d liu n ngoi vi lin tc cho n khi thc hin xong24

- Nu YES th s thc hin cc thao tc truyn nhn d liu vi ngoi vi, ri mi quay li chng trnh chnh. - Nu NO th s thc hin tip chng trnh chnh.

vic truyn nhn d liu vi ngoi vi th mi tip tc chng trnh chnh.

b. Xut nhp d liu vi ngoi vi thng qua ngt

Khi ngoi vi c yu cu truy xut d liu vi VXL, n s to ra mt tn hiu ngt bo cho VXL. Khi nhn c tn hiu ngt ny, VXL s dng cng vic ang thc hin, nhy ti chng trnh con tng ng vi ngt v thc hin cc thao tc xut nhp d liu vi ngoi vi. Khi thc hin xong th quay thc hin tip cng vic trc khi dng ngt.

Nhn xt: d truy xut d liu vi ngoi vi thc hin bng phn mm hay ngt th d liu u phi thng qua CPU ca VXL nn tc b hn ch. C ch truy xut d liu gia vi ngoi vi khng thng qua CPU gi l DMA (direct memorry access) s tng tc ng k, c mt phn cng chuyn thc hin cng vic ny . Tuy nhin PIC khng dng c ch DMA.

3. Cu trc ca mt port I/O ca PIC mid-range

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P_MOSFET : ON khi chn G=0 (positive) N_MOSFET : ON khi chn G=1 (negative) M t hot ng: Mt chn s gm 2 b latch: mt qun l d liu (Data Latch) v mt dng nh ch hot ng ca chn l xut hay nhp (TRIS Latch). + Khi chn ch nhp: Q_TRIS Latch = I. D liu nhp s l mc tnh hiu I/O pin. Khi c tn hiu c d liu t ngoi vo RD PORT. D liu s c cht vo mt b D_Latch dng cho nhp d liu ri truyn vo DATA BUS. + Khi ch xut d liu: tn hiu cht ng ra TRIS Latch l 0. - Khi xut mc tn hiu 1 t data bus: th Mosfet P dn, Mosfet N tt => I/O pin =1 - Khi xut mc tn hiu 0 t data bus: Mosfet P tt, N dn => I/O pin =0

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PORT A 16F887:

Ch khi thao tc c/ghi d liu trn PORTA: Reading the PORTA register (Register 3-1) reads the status of the pins, whereas writing to it will write to thePORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. read-modify-write : Khi thc hin thay i gi tr ca 1 bit hay thanh ghi gn vi 1 port: c gi tr status t cc chn, hiu chnh data c c t cc chn theo chc nng ca lnh, ghi gi tr sau hiu chnh vo port data latch.

Mt s chn trn PORTA c chc nng analog, khi cc chn ny hot ng ch analog th tn hiu c t chn ny s lun l 0

Chn RA0:- Digital I/O - Analog input - Negative analog input cho chc nng comparator C1 / C2

Khi thc hin chc nng Output:

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- TRISA=0, d liu c ly t D-Latch DATA

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