TOPIC : Backtracking TOPIC : Backtracking MethodologyMethodology

UNIT 3 : VLSI Testing

Module 3.2: Arriving at Input Test Vector

IntroductionIntroductionLine justification problem is of getting a proper

assignment of the inputs which can activate the fault.

Error propagation problem is of choosing the inputs such that the fault is propagated to the primary output.

So, to arrive at an input vector, one has to satisfy the problems:◦ Line justification◦ Error propagation

Representation:◦ Justify(node, value) – at that node, the value should occur◦ Propagate(node,value) – from that node, the value should

be propagated to the output

Different MethodsDifferent Methods

There are various methods of arriving at the vector that can detect the faulty circuit. Some of them which are fairly used are:

1. Backtracking method2. D-frontier3. PODEM

Backtracking MethodBacktracking Method

Initially a vector/ partial vector is applied at the input assuming it activates and propagates the fault.

For some reason, if the fault propagation is stopped, come back to a junction point and take another path.

We assume that the fault propagates to the output in the newly chosen path. If not again come back and take another path.

This process of going forward and backward is called backtracking.

ProcedureProcedure It can be illustrated using an example below:

Assume the node ‘h’ as stuck-at-1.

Contd …Contd …Since node ‘h’ is stuck-at-1, 0 should be

applied to activate the fault. Therefore “h=0”.

The propagation of the effect of the fault can be done only through the line ‘p-s’.

Now the value at node ‘h’ is D_bar according to 5-valued logic.

For this fault to propagate to the node ‘p’ through the Gate5, the inputs e & f should be equal to 1. Hence p=D_bar

Hence the vector “efh”=“110”

Contd …Contd …

Now, D_bar at the node ‘p’ is the input to Gate6.

For the value D_bar to propagate to the output node ‘s’, ‘r’ and ‘q’ should be 1, since Gate6 is an AND gate.

In other words, the other inputs should be the C_bar, where ‘C’ is the controlling value of the gate.

Thus q=1, r=1, e=1, f=1, h=0 propagates the faulty value D_bar from ‘h’ stuck-at-1 to output ‘s’.

This calls for justifying q=1 & r=1.

Contd …Contd … Justifying q=1: Since Gate3 is OR, either ‘L’

or ‘k’ or both should be 1.Assume L=1, then both c & d should be 1

since Gate2 is AND. This makes m=0 & n=0 which results in r to be 0.

Therefore a clash has been occurred since r must be equal to 1 for the fault to propagate.

Now, one should track backwards and then make k=1 instead of L=1.

K=1 can be justified by making a=1 & b=1.

Contd …Contd … Justifying r=1: Atleast one of the values m, n, o

should be 1 since Gate4 is a OR gate. Since e=1 is already assigned, o is 0 and hence atleast one of the values m, n should be 1.

This implies atleast one of the inputs c or d should be 0.

Thus, the vector “cd” can be “00 / 01 / 10”

Combining all the obtained assignments, the inputs that can detect ‘h’ stuck-at-1 are

h=0, e=1, f=1, ab=11, cd=00,01,10

so the vectors are 1101110, 1110110, 1100110

Tabular form of Tabular form of BacktrackingBacktrackingDecisions Implications Remarks

h=D_bare=1f=1p=Dr=1q=1o=0s=D

Initial Implications

L=1 c=1D=1m=0n=0r=0

To justify q=1

CONTRADICTION

FAILURE

K=1 a=1b=1

To justify q=1SUCCESS

M=1 c=0L=0

To justify r=1SUCCESS