TOPIC - BIST architectures I

MODULE : BIST architectures

UNIT 5: Built-in-Self-Test

Centralized and Separate Board-Level BIST Architecture

In offline mode, inputs are driven by a PRPG.

Outputs are monitored using a single-input signature analyzer. (To reduce hardware costs, the test is repeated m times, once for each output)

This method is best suited for pipeline circuits with limited feedback.

• centralized and separate BIST architecture;

• no boundary scan;

• combinational or sequential CUT.

Built-1n Evaluation and Self-Test (BEST)

It is an application of the CSBL design to chips.

The inputs to the CUT are driven by a PRPG and the outputs are compressed using MISR.

The hardware overhead for the BEST architecture is low.

But, for some circuits this technique can be ineffective in achieving an acceptable level of fault coverage.

Both an embedded version and a separate version of this architecture exist.

The details of switching between the primary inputs and the output of the PRPG when applying the normal or the test inputs to the CUT are not shown. Either a MUX can be used, or the primary inputs can first be loaded into the PRPG and then applied to the CUT. The same concepts apply to the outputs.

BIST for high fault coverage

The previous BIST architectures often result in low fault coverage because they rely on the use of pseudorandom patterns for testing a sequential circuit.

To circumvent this problem, an internal scan path can be used within the CUT so that the testing of the CUT can be reduced to the problem of testing combinational logic. The next few BIST architectures will illustrate this concept.

Random-Test Socket (RTS)

The random-test socket (RTS) is not a true BIST architecture because the test circuitry is external to the CUT. distributed and

separate test hardware;

no boundary scan; scan path (LSSD) CUT

architecture.

Testing procedure in RTS

Initialize the LFSRs. Load a pseudorandom test pattern

into the scan path using R2. Generate a new pseudorandom

test pattern using R1

Capture the response on the primary outputs of the CUT by applying one clock pulse to R3

Execute a parallel-load operation on the system storage cells to capture the response to the random test pattern.

Scan out the data in the internal scan path of the CUT and compress these data in R4.

Steps 2-6 are repeated until either an adequate fault coverage is achieved

Testing is inherently slow, since for each test pattern the entire scan path must be loaded.

LSSD On-Chip Self-Test (LOCST)

The test process is as follows: Initialize: The scan path

is loaded with seed data via the Sin line.

enable LFSR. Load the scan path with

a pseudorandom test pattern.

Compare the final value in the SISR with the known good signature.

•centralized and separate BIST architecture;•scan path (LSSD) CUT architecture.•on-chip test controller.

Self-Testing Using MISR and Parallel SRSG* (STUMPS)

Applied to boards : Centralized and separate

BIST architectures. Multiple scan paths. No boundary scan.

The scan paths are driven in parallel by a PRPG, and the signature is generated in parallel from each scan path using a MISR.

The scan paths may be of different lengths, the PRPG is run for K clock cycles to load up the scan paths.