8/12/2019 Trans Gate

1/4

Transmission gates,

latchesand ipops

Transmission gates

A transmission gate (Fig.1) is an analog switch controlled by logic signals. It consists of a nand a p type MOS transistor. When the EN = 1 the gate conducts and shorts the input andthe output, otherwise it cuts off and the output oats.

The characteristic equations of the n and p type MOS transistors are:

I Dn = W nL n

n oxtox

(V GSn V T n ) V DSn V 2DSn

2

andI Dp =

W pL p

poxt ox

(V GSp V T p ) V DSp V 2DSp

2

respectively, where the threshold voltage of the n type transistors ( V T n ) is positive while thatof the p types (V T p ) is negative.

In order to understand the operation of transmission gates, the entire input range of V inneeds to be investigated at both true and false values of the enable signal (EN).

Figure 1: A transmission gate

Lets examine the EN = 1 case rst andlets assume that

V DD > V T n + |V T p |

as in Fig. 2.In this case the gate potential of the n type

transistor is at V DD and that of the p type isat ground potential. When the input ( V in ) isbelow |V T p | , the p type transistor is closed asit needs to have a V GSp = V Gp V Sp V T p toconduct. The n type transistor on the otherhand conducts as its gate-source voltage is

large enough: V GSn = V Gn V Sn .If the input voltage goes above |V T p | the ptype transistor starts to conduct. When theinput voltage rises above V DD V T n the gate-source voltage of the n type transistor becomes

1 November 7, 2012

8/12/2019 Trans Gate

2/4

less than V T n so it cuts off. But by this time the p type transistors channel is created andit connects the input and the output. In summary we can conclude that at least one of thetransistors conducts during the entire input range when the enable input is true .

Figure 2: The threshold voltages when V DD > V T n + |V T p |

When the enable input is false (EN = 0 ) the gateof the n type transistor is at ground potential, that of the p types is at V DD . This means that in the entire[0, V DD ] voltage range of the input voltage the gate-source voltage of the n type transistor is less or equalto zero, so the transistor cuts off. The same is true forthe p type as its source potential is less or equal than itsgate potential in the entire range, thus its gate-sourcevoltage is always non-negative.

We have found that when E N = 0 the transis-sion gate is equivalent to an open circuit between itsinput and output.

When

V DD V T n + |V T p |the conducting regions of the transistors overlap whenEN = 1 , which means that there is a voltage range

where both transistors conduct. This makes the series resistance of the gate even less, which isadvantageous.

The RS latch

The RS latch (Fig. 3.) is the simplest sequential logic element that can be used to store one

bit. It consists of two NOR gates and contains feedbacks from both of gates outputs. It is abistable circuit, which means that it has two stable states.

Figure 3: An RS latch

The truth table of a NOR gate can be seenin Table1. The operation of the latch can beanalysed using the table.

Lets assume that the output of theRS latch is false (Q = 0 and Q = 1). Thismeans that 1 is fed back to the upper NORgate and 0 to the lower gate. When R = 0and S = 0 then the upper NOR gate provides0 at its output and the lower one gives 1, sothe circuit is in a stable state.

When S is set to 1, the lower NOR gatehas 0 and 1 at its inputs so its output turnsto 0. As a consequence, the input of the upperNOR gate becomes 0 0, so its output changesfrom 0 to 1. When S becomes 0 again, the lower NOR gate has 1 0 at its inputs, so it stillprovides a 0 at its output. This means that the latch is in a stable state again but its outputhas changed from 0 to 1. S stands for set for this reason.

If R becomes 1, the output of the upper gate changes to 0. The lower gate now has 0 0 atits inputs so its output goes high. The input of the upper NOR gate thus becomes 1 1 but thiscombination doesnt result in a change at its output, it remains 0. When R goes back to 0,the upper gates input combination becomes 0 1, which still results in a 0 at its output, so thelatch falls back to a stable state with an output value of 0. So the R input resets the output.

2 November 7, 2012

8/12/2019 Trans Gate

3/4

If both inputs go high, then both outputs will go low independently of the circuits stateas the NOR gate has a 0 at its output if any of its intputs is 1. When they fall back to 0,the output will become either 0 or 1 depending on which signal falls back faster. This is anunpredictable operation, so an RS latch should never have logic 1 at both inputs at the same time .

Table 1: The truth table of a NORgate

A B A|B0 0 10 1 01 0 0

1 1 0

D latch with transmission gates

A D latch has two inputs: a data input ( D ) and anenable or clock input ( EN ). When then enable inputis true it copies its input to its output. When the enablebecomes false the output freezes and stays at the logiclevel the input had at the time of enable inputs fallingedge.

A D latch can be realized using an RS latch simplyby connecting S to the R input. However, several otherways D latches can be realized exist due to the fact thatit is probably the most important latch.

Figure 4: A D latch with transmission gates

A very simple circuit can be seen in Fig. 4.It consists of only two transmission gates andtwo inverters (8 transistors altogether). Thetwo inverters will copy the input ( D ) to theoutput ( Q) when the upper transmission gateis on. Q is also available from between thetwo inverters.

The basis of the operation is that the twotransmission gates operate alternatively. Thisis obvious if one looks at the way the enableinput is connected to them: EN is connectedto the n type transistor of the upper gate,while it is connected to the p type transistorin the lower one.

Thus when EN falls to 0, the transmissiongate at the input of the latch cuts off andseparates the input from the output. At thesame moment, the other gate in the feedback

branch starts to conduct and will connect the output to the input of the rst inverter. This isa stable circuit where the input capacitance of the inverters hold the information.

Dynamic D ipop

With the same number of transistors (8) a D ipop can be realized (Fig. 5). A ipop is a1-bit memory that changes its output only at the rising or falling edge of the enable or clocksignal.

A latch is transparent during one of the logic levels of the clock. This is unwanted as theoutput value cannot be read with certainty during this half period.

Flipops consist of two latches in series controlled by inverted clock signals. The rst latchmonitors the input during the true level of the control signal and freezes at the falling edge,while the second copies the output of the rst to the output during the false level of the control

3 November 7, 2012

8/12/2019 Trans Gate

4/4

and freezes at the rising edge. It never experiences changes during these half periods as itsinput, the output of the rst latch is frozen. This way changes only occur at the falling edgeof the control signal, when the rst latch freezes and the second one copies its output to theipops output.

Figure 5: A dynamic D ipop

This is exactly what is done in the cir-cuit in Fig. 5. The somewhat surprising fea-ture of this circuit is that there is no feedback,so it might seem unclear where the informa-tion is stored. The answer is that the inputcapacitance of the inverters is charged anddischarged during the half-periods when thetransmission gates at their inputs are on andwhen the inverters inputs oat in the otherhalf, the accumulated charges will ensure thatthe inverters remain in the same state thatthey were last driven to.

When EN = 1 the transmission gate atthe input conducts and charges the input capacitance of the rst inverter to the value of theinput. When EN falls to 0, this gate cuts off and the other one conducts. The rst inverterremains at the value it was charged to and drives the second inverter. This way the input atthe time of the falling edge gets to the output after two inversions, i.e. unchanged. When EN rises again, the second inverter is separated from the rst one and during this half-period itsinput capacitance stores the output.

Every capacitor gets discharged in time. Parasitic parallel resistors can always be foundaround capacitors and charges ow away from the plates gradually. This means that if such aD iop is left on its own, i.e. the enable signal doesnt change often enough, then the input

capacitances get discharged and the output is set to 1 independently of the original value storedin the circuit.Actually the situation is even worse: a oating node (e.g. the input of the second inverter

when EN = 1) is very susceptible to noises. If a high impedance node is not driven, very weaksignals are able to change its potential. This means that in a noisy environment, the output of such a ipop is set to a random value if the enable signal is left unchanged for a long time.

For these reasons, dynamic logic circuits are only used in parts of a system where the clocksignal is very fast and thus the input capacitances are frequently recharged to a correct value.

4 November 7, 2012