TSMC Design Services - km2000.uskm2000.us/franklinduan/articles/tsmcloddfm.pdf · BIMS Fall 2003 Empowering Innovation SM © 2003 TSMC, Ltd Fall 2003 1 TSMC Design Services: Bringing

BIMSFall 2003 Empowering InnovationSM

Fall 2003 1© 2003 TSMC, Ltd

TSMC Design Services:Bringing Your Products to Market Faster

BIMSFall 2003

Empowering InnovationSM


Intense Design Challenges

0.25-micron0.18-micron

0.15-micron0.13-micron

90 nanometer

Gap atSynthesiswireload &P&R

ComplexityIterationat P&R

Noise &EM

65 nanometer

IR & leakage

Efficiencyof point tools

Design Complexity

DesignRequirements

TechnologyConstrains

BIMSFall 2003



What We Provide Besides Wafers

Design Foundation Data

Design Methodology

Design Assistance

Designer’sCreativity

BIMSFall 2003



Enabling Time to Volume

0.18-micron 0.13-micron 90 nanometer 65 nanometer

IP & Lib.

FoundationData (TSMC)FoundationData (TSMC)

Methodology& Assistance

(TSMC & 3rd Party)

Methodology& Assistance

(TSMC & 3rd Party)

DesignerDesigner

0.15-micron

BIMSFall 2003



Extensive Portfolio of Alliances

Foundation:Design Rule related: DRC, LVSSpice Model related: Spice, RCX

Methodology:Digital Reference Flow

Four generations of quality deliveryRF/MS Design Kit

Foundry industry’s first and broadest node coverage

Design Assistance:TSMC Implementation Service3rd-Party Implementation ServiceSilicon Debug and Repair Service

EDA AllianceEDA Alliance

EDA AllianceEDA Alliance

Validation AllianceValidation Alliance

DCA AllianceDCA Alliance

BIMSFall 2003




Design Methodology

Design Assistance


BIMSFall 2003



Foundation Data Quality

Device ModelingVersion strategy

V0.0x, V0.x – guess model, R&D modelV1.x, V2.x – silicon model and production

AccuracySilicon correlationCorner models (-40o ~ 125o)

Improved MOSFET ModelingVt ModelingGate current modelingSTI stress effect modelingGate capacitance modelingDiode leakage current modeling

SPICE Model

W

L

SA

SB

LOD

0

200

400

600

800

1000

1200

1400

-18-17-16-15-14-13-12-11-10-9 -8-7-6 -5-4 -3-2 -1 0 1 2 3 4 5 6 7 8 9 10

Error Percentage (%)

Number of Nets

BIMSFall 2003




DRC, LVSEarly AvailabilityIn-house developmentsynchronizes release withDRMHigh QualityDouble-blind QA ensuresindustry-leading qualityExtensive PortfolioBroad support of widelyused tools

DRMDesign Rule

Manual

DRCDevelopment

Test SuiteDevelopment

QA

CustomersTape-Out

Real DesignValidation

DRC

BIMSFall 2003




Extraction Model

Interconnect ModelRealistic Corner Model

Reflects combination ofmulti-layer statisticalcorners

Performs silicon correlationwith commercial toolsRC Accuracy enhancement

Model with metal-thickness90 nanometer enabled

PMOS Core W/L=10 /1 .2 Vgs= 0 .41V, Vds=1V

1.E-251.E-241.E-231.E-221.E-211.E-201.E-191.E-18

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6Frequency (Hz)

Sid

(A2 /H

z)


1.E-251.E-241.E-231.E-221.E-211.E-201.E-191.E-18

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Sid

(A2/H

z)


1.E-251.E-241.E-231.E-221.E-211.E-201.E-191.E-18

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6Frequency (Hz)

Sid

(A2 /H

z)

BIMSFall 2003


Fall 2003 10© 2003 TSMC, Ltd


Design Methodology

Design Assistance


BIMSFall 2003


Fall 2003 11© 2003 TSMC, Ltd

Industry’s Most Comprehensive FlowFour consecutive quality deliveries

Each release addresses new design challenges

All releases are backward compatible

SI ClosureFlow

HierarchicalFlow

HierarchicalFlow

TimingClosure Flow

Timing DrivenFlow

TimingClosure Flow

TimingClosure Flow

Efficiencyof point tools

Gap atSynthesiswireload &P&R

Iterationsat P&R

Complexity

Xtalk, IR &EM

Release 3.0Release 2.0Release 1.0

BIMSFall 2003


Fall 2003 12© 2003 TSMC, Ltd

Expands customer support through multiple majorvendors coverage

Responds to customers’ feedback

Dual-Track Reference Flow

Release 1.0 Release 2.0 Release 3.0

Single-trackCoverage

Single-trackCoverage

Note: TSMC Customer Base Coverage (physical implementation) Note: TSMC Customer Base Coverage (physical implementation)

Dual-trackCoverage

Dual-trackCoverage

BIMSFall 2003


Fall 2003 13© 2003 TSMC, Ltd

Multi-Vt Solution for Power Optimization

RTL

DRC/LVS

Physical SynthesisPhysical Optimization

RoutingRC Extraction

SI AnalysisSTA

Gate-level NetlistCell Swapping

Higher Speed

Lower Leakage

LowVt

Library

NominalVt

Library

HighVt

Library

DRC/LVS

Physical SynthesisPhysical Optimization

RoutingRC Extraction

SI AnalysisSTA

RTL

Commercial Flow

Layout ReplacementGDSDRC/LVS

GDS

BIMSFall 2003


Fall 2003 14© 2003 TSMC, Ltd

Power/Speed Optimization Example

Design Case: RISC Processor

Technology: TSMC 90 nanometer

100%HVT

100%

HVTHVTDynamicLeakage

100%20090.71.3HVT28092.93.6NVT

Cell Distribution

360

Frequency(MHz)

123.821.6

Power (mA)

LVT

Case

28%

28%

27%27%

72%

73%28091.52.2H/N VT43%360105.59.7H/N/L VT

360106.210.5N/L VT

BIMSFall 2003


Fall 2003 15© 2003 TSMC, Ltd

SI Analysis

• Well correlated RC Extraction considering In-die Process Variation.• Accurate SI Analysis.

SI and Timing Closure(Prevention, Analysis and Repair)

SI-Driven Prevention SI-Driven RepairPlacement

Optimization

Routing

Violation?

Physical VerificationNo

OptimizedNetlist

RC ExtractionIR Drop Analysis

Crosstalk AnalysisSTA

Yes

Dramatically Reduce the SI Violations

Quickly Achieve SI and Timing Closure

BIMSFall 2003


Fall 2003 16© 2003 TSMC, Ltd

Demonstration of SI and Timing Closure

Achieve both SI and timing closure withReference Flow 4.0

TSMC 0.13-micron technology

Two million-gate design

00Final Clean-up

Number of timingviolations

40183rd Iteration1121162nd Iteration6221437

Number of glitchviolations

1st Iteration

BIMSFall 2003


Fall 2003 17© 2003 TSMC, Ltd

DFM (Design for More?)How can a chip fail? How to avoid failures?

During design implementation (DFA – Design for Accuracy)Design Spec

Functional error (Logic – function verification)Electrical error (Timing, power – timing closure, poweranalysis)

Silicon technology specPhysical error (rule -- DRC check)Circuit error (silicon model, SPICE simulation)

During manufacturing (DFM – Design for Manufacturability)Mask/OPC inducedProcess steps inducedMaterial induced

During usage (DFR – Design for Reliability)Time induced (electron-migration, wire-heating)Situational signal induced (cross-talk delay and glitch)Environment induced (temperature, shock)

BIMSFall 2003


Fall 2003 18© 2003 TSMC, Ltd

DFA (increase accuracy; bring out best performance)Length of Defusion (LOD)

STI stress effectFunction of lengthBSIM3 & BSIM4 supportADS, Eldo, Hspice, Spectre

Metal thickness/width modelingRC accuracyCorner model

IR DropCapacitance calculationDe-coupling cell insertion

Cross-talkDelay, noise or glitchesSI design closure

PreventionAnalysisRepair

Design for Accuracy

A1,P1

A2,P2

A4,P4

A3,P3

L1 L

2

L3

W1

W2

W3

node1

node2

node3n

ode4

node5

node6

node7

S2

S1 S

3’

S4

S5

S6

POLY

ODC

ontact

S3’’ W

2’

W2’’

150020002500300035004000

0.0 0.2 0.4 0.6 0.8 1.0

M1

0.04

0.06

0.08

0.10

0.12

0.14

0.0 0.2 0.4 0.6 0.8 1.0

Density

Rs

M1

0.04

0.06

0.08

0.10

0.12

0.14

0.0 0.2 0.4 0.6 0.8 1.0

Density

Rs

BIMSFall 2003


Fall 2003 19© 2003 TSMC, Ltd

DFM (Design for Manufacturability)Mask induced

Lithographical effectLayer density rule

Process steps inducedCMP effect

Metal thickness variation modelingMetal density rule

Charge zap effectAntenna rule

Material inducedSTI effect LOD

LOD device modelingDielectric material

Maximize redundant VIAStack VIA effect

Stack height limit

Path Delay

diff %

Analysis of Dummy Metal Impact on Delay

0.08um

0.08um

0.005um

0.005um

0.08um

0.005um0.08um

0.005um

WidthSpacing 0.20 0.40 0.60 1 2 30.21 2.653

0.24 2.698 2.380 2.334 2.330

0.42 2.339 2.365 2.308

0.63 2.304 2.346 2.286 2.273

S\W 0.20 0.40 0.60 1 2 30.21 0.389 0.389 0.389 0.389 0.389 0.389

0.24 0.389 0.389 0.389 0.389 0.389 0.389

0.42 0.389 0.389 0.389 0.389 0.389 0.389

0.63 0.389 0.389 0.389 0.389 0.389 0.389

0.84 0.389 0.389 0.389 0.389 0.389 0.389

S\W 0.20 0.40 0.60 1 2 30.21 0.2275 0.4275 0.6275 1.0275 2.0275 3.0275

0.24 0.2275 0.4275 0.6275 1.0275 2.0275 3.0275

0.42 0.2275 0.4275 0.6275 1.0275 2.0275 3.0275

0.63 0.2275 0.4275 0.6275 1.0275 2.0275 3.0275

0.84 0.2275 0.4275 0.6275 1.0275 2.0275 3.0275

widthThickness

Resistivity

A1,P1

A2,P2

A4,P4

A3,P3

L1

L2

L3

W1

W2

W3

node1

node2

node3

node4

node5

node6

node7

S2

S1

S3’

S4

S5

S6

POLY

ODC

ontact

S3’’

W2’

W2’’

BIMSFall 2003


Fall 2003 20© 2003 TSMC, Ltd

DFR (Design for Reliability)DFR (avoid failure in use; increase MTBF)Electro-migration

Power EMPower meshWire tapering

Signal EMMultiple via insertion

Cross-talkDelay, noise or glitchesSI design closure

PreventionAnalysisRepair

Hot electronSafe IR control design practice

Self-heating wireSafe power/clock mesh design practice

Wire Tapering

Multiple VIA

BIMSFall 2003


Fall 2003 21© 2003 TSMC, Ltd

Flip-Chip Capability

RDL Flow (available)Silicon proven flow on several customer chips.

Area Array Flow (under development)Cluster approach using TSMC developed flip chip I/OsSilicon validated on internal test chipFine tuned for new I/O cells (better structure)

RDL Area Array

BIMSFall 2003


Fall 2003 22© 2003 TSMC, Ltd

PDK for High Quality MS/RF Designs

CM025CM018CM013*SG035**SG018**

Mixed Signal/RFDesigners

* Currently posted with CL013** Temporary posted at Cadence web site

Download & Support

( TSMC-Online )

Joint Development

SKILLCode

SKILLCode

PhysicalVerification

Files

…..….

…..….

DesignRules

SPICEModels

…..….

…..….

…..….

…..….

P-cell LayoutGenerators

For Mentor ADK contact Mentor

BIMSFall 2003


Fall 2003 23© 2003 TSMC, Ltd

TSMC PDK Device ListElements

RF PadEDSResistor

SupportingPassiveActiveMOS

InductanceCapacitorVaractor

Features

ThermalResistorNoise model3-T model4-T model

MOS

InductanceCapacitor

MethodologyMonte-Carlo

FlickerCorner

Statistical model

Matching

BIMSFall 2003


Fall 2003 24© 2003 TSMC, Ltd


Design Methodology

Design Assistance


BIMSFall 2003


Fall 2003 25© 2003 TSMC, Ltd

Design & EDA ExpertiseBirth place of TSMC reference flowsIn-house library, I/O & IP developmentPioneering tape out of advanced technologies

Silicon ExpertiseDevice characterizationSilicon correlation

Full Service ExpertiseTurn-key serviceKey customer drivenProduct engineering

Spec

TSMC In-house Implementation Service

BIMSFall 2003


Fall 2003 26© 2003 TSMC, Ltd

Industry’s Largest Design Center Alliance

Over 400 Tapeouts in 2002 28 Worldwide Partners

The Applications You WantCommunicationComputer Consumer

The Business Models You PreferT&M-based

Consulting ServiceNRE-based

Outsourcing Service Turnkey/ASIC Service

The Services You Require

SRAM DesignNetlist-to-GDSII RF Design

Mixed Signal DesignRTL-to-GDSII DFT ServiceFull Custom LayoutMemory CharacterizationPlatform-based Design

GOYAGOYA

BIMSFall 2003


Fall 2003 27© 2003 TSMC, Ltd

DCA Success Story - Consumer

BIMSFall 2003


Fall 2003 28© 2003 TSMC, Ltd

Ideally suited to video and image encodingand decoding applications that are relianton a low power, low cost integratedprocessing solution. Applications include:

Wireless Video Phones Camera Accessory Modules Wireless PDAs Wireless PC/ Network Cameras

FIRST-PASS SILICON SUCCESS!

TECHNOLOGY: 0.13 µm CMOS process,100 MHz operating frequency

APPLICATION: Array Processor forparallel operations, ARM922TTM for hostand high-level instructions

PACKAGE: 180 pin CABGA

POWER: 1.2V Core and 2.5/3.3 V I/Os,Multiple Power Modes

"We chose QThink because our projectteam found that they offered a solidsolution with a flexible interface thatwould allow customization of someareas of the design. They were one ofthe few that had true 0.13u tape-outexperience along with strong skills in thegeneration and integration of custommacros, and that gave us goodconfidence that the project would besuccessful."

Richard BériaultDirector of EngineeringAtsana Semiconductor

"We chose QThink because our projectteam found that they offered a solidsolution with a flexible interface thatwould allow customization of someareas of the design. They were one ofthe few that had true 0.13u tape-outexperience along with strong skills in thegeneration and integration of custommacros, and that gave us goodconfidence that the project would besuccessful."

Richard BériaultDirector of EngineeringAtsana Semiconductor

Atsana J2210 Media Processor “Product Architecture”

“Chip Implementation”

“Fabrication”

QThink Customer Design Success

BIMSFall 2003


Fall 2003 29© 2003 TSMC, Ltd

DCA Facilitates Customer Success

“Philips Semiconductors selected CadenceDesign Foundry to join Philips existingdesign capability in a design partnership toimplement the pnx8526 product. The combined efforts of both teams resultedin an essentially first silicon successproduct that met the end customer’saggressive production IC availabilityrequirements”

Wout BijkerVice-President, Business Line BroadbandHome ServersPhilips Semiconductors

Chip Photomicrograph of Philips Semiconductors’ EDAC 2002 award winnerNexperia-based Home Entertainment Engine pnx8526

• 5 Million Gates• 778Kbits of Sram (232 instances)• 0.13 um TSMC (1P8M + RDL)• 158MHz core clock speed, 56 domains• 150MHz Processor, 200MHz DSP• Complex Analog functions.• 8.6mm x 8.2mm• 367 I/Os and Power• Wirebond, BGA• Power consumption 2.6W

First Silicon Success®

BIMSFall 2003


Fall 2003 30© 2003 TSMC, Ltd

IC Validation Alliance – Bridging TheGap Between Prototype & Volume

Customer

Volume Production

Prototype Manufacturing

First-passSilicon Success

YES

NO

Design & Implementation

TSMC

The New Debug Strategies

Silicon DebugDirect Transistor MeasurementWire Bond and Flip-ChipApplication Board SupportedPerformance Up to 10 GHz

Silicon RepairCircuit ModificationFront-side and Back-side FIB*Wire-bond, Flip-Chip and WaferCu & low-k Dielectric Supported

* FIB: Focused Ion Beam

Design rework

Beam

DIE

PACKAGEFlip-Chip/Wire Bond

E-Beam Probe

WaveformMeasurements

90nm CAD 90nm LSM** Image Through SiliconFIB Repair to M2

* FIB: Focused Ion Beam** LSM : Laser Scanning Microscope

Validation AllianceValidation Alliance

BIMSFall 2003


Fall 2003 31© 2003 TSMC, Ltd

IC Validation - Business Model &Program Snap Shot

The business model you need fromGuaranteed localization of failure; no service charge iffailure is not localizedProject based pricing; remove the time and materialsrisk

28 IC validation projects completed in theprogram’s first 14 months

8 more projects underwayCovering computer, consumer andcommunication applications

1

0.35 µm

1

0.25 µm

13

0.18 µm

13

0.13 µm

# of Projects

Technology

BIMSFall 2003


Fall 2003 32© 2003 TSMC, Ltd

SummaryTime-to-Design Start

• High quality, highly consistent foundation data • DRC, LVS, RCX, SPICE

Time-to-Tapeout

Time-to-Volume• Flexible service business models• Safety net provided through Validation Service

• Robust and state-of-the-art methodology support • Four generations of Reference Flow • Expanded PDK for RF/MS design needs• Most comprehensive 3rd-party and in-house design services portfolio


Fall 2003 33© 2003 TSMC, Ltd

TSMC Design Services:Bringing Your Products to Market Faster


Fall 2003 34© 2003 TSMC, Ltd

Reference

BIMSFall 2003


Fall 2003 35© 2003 TSMC, Ltd

A Complete Design Service Package

Fastest time

to tape out

& volume

* In progress ** Upon request

Synopsys Hercules

Cadence AssuraDivaDracula

Mentor Calibre

DRC

SpiceAgilent ADS

Synopsys H-Spice

Cadence SpectreMentor Eldo

AssuraFire&Ice(QX)

RCX

Raphael NESStar RC(XT)

Cadence

HyperExtractNautilus

Mentor xCalibre

Sequence Columbus

Synopsys Arcadia

LVS

Synopsys Hercules

Cadence AssuraDivaDracula

Mentor Calibre

Application Notes

Usage Guideline etc.

SubstrateCadence Substrate-

Storm**

Mixed-Sig /RF Design Kits

CadenceMentor*

PDKADK

ReferenceFlows

Cadence, SynopsysMentor, Syntest

BIMSFall 2003


Fall 2003 36© 2003 TSMC, Ltd

EDA Alliance

Reference FlowReference FlowDual implementation tracks Enablingdirect manufacturability into TSMC’s

advanced technologies

Analog Design KitAnalog Design KitOff-the-shelf productivity fromindustry-leading analog tools

DRCDRCDouble-blind

QualityAssurance

LVSLVSMatches device (spice),

layers (design rule)and application notes

SPICESPICEIndustryleadingmodels

RCXRCXAlways

calibrated tosilicon

SubstrateSubstrateAdvanced noiseanalysis for RF

design

Foundation

Methodology

World Leading Design Foundation and Design Methodology

BIMSFall 2003


Fall 2003 37© 2003 TSMC, Ltd

Physical / Multi-Vt Synthesis

Floor-plan/ Power-plan

Placement / Routing

RC Extraction

Static Timing Analysis

Cross-talk / IR-Drop

Design For Manufacturability

CadenceCadenceSynopsysSynopsysMentorMentor

BIMSFall 2003


Fall 2003 38© 2003 TSMC, Ltd

Current Design Center Alliance

Bring Multiple Choices to Customers !

The Most Extensive Design Center Portfolio in Foundry Industry

Geographically Diversified Availability : 27 Design Centers Worldwide

♦ Asia: 7 PGCInnochip SotaGoya SocleGUC

♦ Europe: 4 S3-GroupNewlogic Nordic VLSI

♦ Japan: 4 Toppan WiproDai Nippon Hoya

♦ US: 12 Cadence

Qualcore LogicSynopsys Syntest

MacroTechGreenforest LegendArcadia Crest Oridus

♦ Implementation♦ Netlist-to-GDSII

♦ RTL-to-GDSII

♦ Spec.-to-GDSII

♦ RF Design

♦ DFT

♦ Memory Characterization

♦ SRAM Design

♦ Mixed Signal Design

♦ Full Custom Layout

Broad Service Expertise♦ Specialty

♦ Turnkey

SMT*

SPIKE*QThink

Accent*

* New additions

.

Documents

TSMC Design Services - km2000.uskm2000.us/franklinduan/articles/tsmcloddfm.pdf · BIMS Fall 2003 Empowering Innovation SM © 2003 TSMC, Ltd Fall 2003 1 TSMC Design Services: Bringing