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Thin Solid Films 461 (2004) 336–339

Turn-off current variation in drain-offset polysilicon thin film transistors

In Chan Lee, Tae Young Ma*

Department of Electrical Engineering and Research Institute of Computer Information Communication, Gyeongsang National University,

Gazwadong 900, Jinju 660-701, South Korea

Received 31 August 2003; received in revised form 21 January 2004; accepted 14 February 2004

Available online 6 May 2004

Abstract

Bottom gate drain-offset polysilicon thin film transistors (poly-Si TFTs) were fabricated on SiO2 coated Si wafers. After completing gate

oxide deposition, we exposed the wafers to air in a clean room. Poly-Si films were deposited on the gate oxides for the active layer of the

drain offset poly-Si TFTs with changing the air-exposure time. Threshold voltage shift to positive value and turn-off current raise with

increasing the air-exposure time were observed. In this paper, we focused on evaluating the causes of the turn-off current raise with the air-

exposure time. The carbons piled up at the poly-Si/SiO2 interface were observed by a SIMS measurement, which is considered to be the

origin of negative charges. The concentration of the carbon was remarkably increased by expanding the air-exposure time. The existence of

the negative charges in the oxide was also found by a capacitance–voltage measurement. We conclude that the carbons originated from the

air in the clean room are the main cause of the threshold voltage and turn-off current variation in the drain-offset poly-Si TFTs.

D 2004 Elsevier B.V. All rights reserved.

Keywords: Drain-offset poly-Si TFT; Air-exposure; Poly-Si/SiO2 interface; Carbon

1. Introduction

Bottom gate polysilicon thin film transistors (Poly-Si

TFTs) have been widely used as active pull-up devices of

complementary metal oxide semiconductor static random

access memories (CMOS SRAMs) [1–3]. For such appli-

cations, the off-state leakage current (turn-off current) has to

be in the range of sub picoampere. However, poly-Si TFTs

suffers from the anomalous high turn-off current, which is

attributed to the emission of the traps presenting at grain

boundaries in the drain junction [4,5]. In order to reduce the

turn-off current, drain-offset structures, etc. have been

adopted for poly-Si TFTs [6–8].

In addition to traps, organic contaminants adsorbed on

silicon dioxide and/or poly-Si film are also considered as the

cause of turn-off current. It has been reported that organic

contaminants come from organic volatiles in a clean room,

solvents and wafer cassettes, etc. [9,10]. In the bottom gate

poly-Si TFTs, gate oxides are prepared on substrates in

advance of poly-Si deposition for active layers. During the

process, the naked gate oxides are exposed to the air in the

0040-6090/$ - see front matter D 2004 Elsevier B.V. All rights reserved.

doi:10.1016/j.tsf.2004.02.031

* Corresponding author. Tel.: +82-55-751-5343; fax: +82-55-759-2723.

E-mail address: tyma@nongae.gsnu.ac.kr (T.Y. Ma).

clean room by the time the substrates are loaded into a

furnace to be coated with poly-Si films. The organic con-

taminants can be adsorbed on the gate oxide, which is

waiting for being loaded into the furnace. Toshiyuki Iwa-

moto et al. [11] have reported that carbon contaminants

caused by the wafer exposure to the clean room air induce

degradation of the gate oxide reliability.

In this paper, we have fabricated p-channel bottom gate

poly-Si TFTs for which the air-exposure time between the

deposition of the gate oxide and that of the active poly-Si

film was varied from 20 to 390 min. We have investigated

the effect of the air-exposure time on the turn-off current of

poly-Si TFTs. Transmission electron microscopy (TEM),

atomic force microscopy (AFM), secondary ion mass spec-

trometry (SIMS) and gate capacitance–gate voltage (CG–

VG) measurements were conducted to evaluate the cause of

the deterioration of the properties in poly-Si TFTs.

2. Experimental procedure

Fig. 1 shows the cross-sectional view of the bottom gate

drain-offset poly-Si TFT. The drain-offset region of 0.4 Amwas implanted to reduce leakage current in the cut-off. The

gate dielectric was 30-nm-thick SiO2 grown by a low-

Fig. 1. Cross-sectional view of a bottom gate drain-offset poly-Si TFT.

Fig. 3. ID–VG characteristics of drain-offset poly-Si TFTs prepared with

different air-exposure times.

I.C. Lee, T.Y. Ma / Thin Solid Films 461 (2004) 336–339 337

pressure chemical vapor deposition (LPCVD) at 830 jC.Active poly-Si films prepared by the LPCVD at 480 jCwere annealed at 650 jC for 4 h. The thickness of the active

poly-Si film was 32 nm. Offset regions were doped by

implanting boron ions with a dose of 5�1012 cm�2 and an

energy of 20 keV. Boron phosphorus silica glass (BPSG)

was coated on the wafers by PECVD for the passivation and

planarization. Al/Ti/TiN multilayers were used for metal

pads. The final annealing was carried out at 410 jC for 30

min in N2 ambient. The channel width and length were 0.35

Am and 0.7 Am, respectively. The air-exposure time was

intentionally varied from 20 to 390 min. The Si wafers

completing gate oxide deposition were bared to the clean

room air during the air-exposure time. Drain current (ID) as

a function of gate voltage (VG) was measured using a

semiconductor parameter analyzer (HP4145). A capacitance

meter (HP 4284 LCR meter) was used to measure gate-

channel capacitance (Cgc) as a function of gate voltage (VG).

Cgc was measured by shorting together the source and drain

which are connected to ground. VG was varied from �5 to 5

V. A transmission electron microscope (Philips, model

CM200) operating at an acceleration voltage of 300 kV

was employed to study the grain size of the poly-Si films

used as the active layer. The surface roughness (RMS) of the

poly-Si films was evaluated by an atomic force microscope

Fig. 2. ID–VG characteristics of drain-offset poly-Si TFTs. The drain-offset

lengths are between 0.1 and 0.4 Am.

(SEIKO, model SPI3700). The AFM was operated in the

tapping mode and in the repulsive force regime with a force

constant of 1 nN. Carbon, oxygen and fluorine depth

profiles for the active layers were obtained using 2.0 keV

Cs+ beam. A secondary ion mass spectrometer (Perkin-

Elmer, model PHI 6300) was used for this purpose.

3. Results and discussion

Fig. 2 shows ID–VG characteristics of drain-offset poly-

Si TFTs with a parameter of offset length. The offset lengths

of the drain-offset poly-Si TFTs are between 0.1 and 0.4 Am.

The turn-off current reduces drastically when the offset

length increases to 0.4 Am. We adopted the drain-offset

length of 0.4 Am for this experiment.

Fig. 3 shows ID–VG characteristics of the drain-offset

poly-Si TFTs prepared with different air-exposure times.

Fig. 4. High frequency gate-channel capacitance as a function of gate

voltage.

Fig. 5. IOFF variation of drain-offset poly-Si TFTs with air-exposure time.Fig. 7. AFM images of the poly-Si films used as active layers of drain-offset

poly-Si TFTs. Air-exposure time was: (a) 1 h and (b) 4 h.

I.C. Lee, T.Y. Ma / Thin Solid Films 461 (2004) 336–339338

The air-exposure time varied from 20 to 390 min. Turn-on

current (ION) and turn-off current (IOFF) increase with

increasing the air-exposure time. ION is the drain current

at VG<0 V and IOFF means the minimum current in the cut-

off region. Threshold voltage apparently moves toward

positive values.

High frequency (1 MHz) Cgc as a function of VG is

shown in Fig. 4. The air-exposure time of two samples is 1

h and 4 h, respectively. The flatband voltage shifts toward a

positive value when the air-exposure time increases from 1

to 4 h, which means the existence of negative charges in the

gate oxide [12]. The threshold voltage shifts to positive

value resulted from the negative charges in the gate oxide.

The variation of ION, which appears to increase with the air-

exposure time, is due to the threshold voltage shifts. On the

contrary, the IOFF is authentically increased by extending the

air-exposure time, which would bring the poly-Si TFTs used

as active pull-up devices of CMOS SRAMs to malfunction.

The IOFF variation with the air-exposure time is presented in

Fig. 5. Drain voltage was �3 V in Fig. 5.

The change in microstructure, surface roughness and/or

interface states may be the cause of the variation in IOFF. The

TEM and AFM results of the poly-Si films used as the

active layers are shown in Figs. 6 and 7, respectively. The

air-exposure time of Fig. 6a,b is 1 h and 4 h, respectively.

No difference in grain size has been observed between the

two samples. The roughness of the poly-Si films is com-

pared by the AFM results. Fig. 7a,b are correspondent to

Fig. 6a,b. The surface roughness observed for the two

samples is 1.72 A and 1.74 A, respectively. From the results

Fig. 6. TEM micrographs of the poly-Si films, which have been used as

active layers of drain-offset poly-Si TFTs. Air-exposure time was: (a) 1

h and (b) 4 h.

of TEM and AFM, we could not find enough evidence for

the microstructure or morphology variation with respect to

the air-exposure time.

Fig. 8 shows the SIMS depth profiles of fluorine, oxygen

and carbon in the consecutive layers of poly-Si and SiO2

which have been employed for the active layer and gate

oxide, respectively. The solid circles are the result of the

poly-Si/SiO2 film prepared with the air-exposure time of 1

h and the solid lines are for the poly-Si/SiO2 film formed

with the air-exposure time of 4 h. A big difference in the

carbon concentration is observed in Fig. 8b. The longer is

the air-exposure time, the more carbon is detected in poly-

Si/SiO2 interface. It has been reported that the carbon-doped

Si has negative interface charges, rather than the normal

positive [13]. It is considered that the carbons originating

from the air in the clean room are adsorbed on the surface of

gate oxides during the air-exposure time. The carbons

incorporated into the poly-Si/SiO2 interface generate addi-

tional traps, which are the main cause of the turn-off current

increase in the air-exposed poly-Si TFTs. The turn-off

current in poly-Si TFTs is known to be proportional to the

trap density at the drain junction [4]. The fluorine atoms are

assumed to be bred in the poly-Si films by the BF2implantation and segregated into the neighboring gate oxide

during the post annealing [14]. The fluorine atoms are

reported to exhibit the positive effects on the properties of

poly-Si TFTs by passivating the traps in the grain bound-

aries [14]. It is considered that a cleaning step may eliminate

Fig. 8. SIMS depth profiles of: (a) fluorine and oxygen and (b) carbon in

consecutive layers of poly-Si and SiO2. The solid circles correspond to the

poly-Si/SiO2 film prepared with the air-exposure time of 1 h and the solid

lines correspond to the poly-Si/SiO2 film prepared with the air-exposure

time of 4 h.

I.C. Lee, T.Y. Ma / Thin Solid Films 461 (2004) 336–339 339

the leakage current problem caused by the carbon adsorbed

during the air-exposure time.

4. Conclusions

Bottom gate drain-offset poly-Si TFTs were fabricated. A

turn-off current variation with air-exposure time was mea-

sured. The turn-off current increased with increasing the air-

exposure-time. TEM and AFM results of poly-Si films used

as active layers did not show any difference in gain size and

morphology with respect to the air-exposure time. From the

SIMS depth profiles of the poly-Si TFTs, it is found that the

longer the air-exposure time is, the higher the concentration

of carbon in the poly-Si/SiO2 interface is. We conclude that

the carbon incorporated into the poly-Si/SiO2 interface is the

main cause of the turn-off current variation with the air-

exposure time.

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