Tutorial06 Solution

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Technische Universitt Mnchen

Chip Multicore ProcessorsTutorial 6

Institute for Integrated Systems

Theresienstr. 90

Building N1www.lis.ei.tum.de

S. Wallentowitz


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Institute for Integrated SystemsChip Multicore Processors Tutorial 6 2S. Wallentowitz

Task 6.1: Cache Misses

Explain the 3 Cs of cache misses. How do they relate?


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3 Cs Model

Compulsory :Very first access to a data blockCannot be avoided

Capacity :Restricted size leads to miss after replacementWould not have happened if cache was unlimited

Conflict :Miss occurs due to prior replacementWould not have happened with full-associative caches


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Example for Contribution of each of the Cs

(c) Rochester Institute of Technology


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Task 6.2: Multilevel Caches and separated instruction and

data caches

In this tutorial we focus on the impact of the cache hierarchy on theperformance of the system.

a) You have a simple system with a processor core, no caches and anexternal memory. The on-chip interconnect between the processor core and

the memory requires 3 + x cycles for the transfer of x data words. Thememory requires 46 cycles to access data. By using a benchmark you findthat on average each fifth instruction accesses data. Your processor has a

CPI of 1.8.

What is the CPI of your whole system?


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Simple System

Proc.Core Memory


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b)

Proc.Core Memory

You are using a direct-mapped cache of 32 kB and with cache blocks of 4words (each 32 bit). The cache is accessed in one clock cycle. For your

application you measure a miss rate of 5%. How does the CPI change?

Cache


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c)

Proc.Core

Impressed by the improvement you add a second instance of this cache.How does the CPI change?

Cache MemoryCache


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Local vs. Global Miss Rate


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d)

Alternatively, you can use two other caches, each of total 256 kB. One ofthe caches is 2-way associative and has an access time of 4 cycles. Theother cache is 4-way associative and has an access time of 6 cycles. The

global miss rate is 4% for the first cache and 3% for the second cache.

Which cache should be chosen?


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Proc.Core MemoryCache

256 kB2-way

4% global miss rate4 cycles

Cache

32 kBDirect-mapped

5% global miss rate1 cycle


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Proc.Core MemoryCache

256 kB4-way

3% global miss rate6 cycles

Cache

32 kBDirect-mapped

5% global miss rate1 cycle


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e)

Explain the meaning of spatial and temporal localityin the context of instructions and data.


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Locality of data


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Locality of instructions


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f)Based on your previous findings, exchange the level one cache with separatecaches for instructions and data. The miss rate for instructions is 3% and for

data 8%. Use the level 2 cache from d) and calculate the CPI value.

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