Ultra High Efficiency

Mixed Signal Processors

TECHNOLOGYShenzhen & Zurich

Problems in front of AI

How to continuouslyimprove computingefficiency，subjecting to Moore's law ?

1 How to get more effective data?

How to reducecomputing costs?

How to achieveon-chip learning,not just inference?

2

3 4

Technology

2

Top1 vs. operations, size parametersȣ

Algorithm Team

REEXEN Technology, devoted to mixed signal computing

Company Profile

Shenzhen OfficeFounded in Jun 2018

Zurich officeFounded in Dec 2017

Engineering, etc

Chip Design Team

80% R&D

40% hold doctor degree

Qualifications

Background

Papers

Huawei, IMEC, Xilinx, ARM, Qualcomm, ETH, Nanyang Technological University

ISSCC, JSSCC, TCAS, Frontiers in Neuromorphic.

Average Industry experience of over 10 years, with a number of mass production experience

Qualifications

Background

Papers

Industry experience of nearly 10 years

NIPS, SIGMOD, TODS, etc.

Tencent, Chinese academy of sciences, Imperial College London, Munich university of technology

3

Human brain has an average of 1011 neurons and can carry out complex processing and learning with power consumption of only:20 W

One game of AlphaGo costs thounsands dollars in electricity.

Power efficiency of most digital AI chips: 1-5tops /W

AlphaGO-TPU ClusterHuman Brain

Technology

4

Biological neurons

Analog computation, digital propagation, computation & storage are both done in neurons

Most AI chips

Storage and Computation Separated

StorageComputation

Digitalpropagation

Technology

5

Very High energy efficiency20-50Tops/WUltra-high energy efficiency10 times higher than current digitalaccelerators

Adjustable accuracyProgrammable bit precision

Low costOn chip storage, saving powerconsumption on DDR driver andDRAM

Unique mixed signal computing chip IP(Deep Neural Network)Deep Neural Network

Technology

Technology FeaturesGflops/Watt

100

101

102

103

104

105

106

2014 2016 2018 2020 2022 2024 2026

Digital AI Coreswith Approximate Computing

Analog AI Cores

Analog AI CoresWith Optimized Materials

IBM Research AI Hardware Center is developing a roadmap for 1,000ximprovement in AI compute performance efficiency over the next decade,with a pipeline of Digital AI Cores and Analog AI Cores

Industry trends usingexisting base technologiesfor deep learning computations

6

More than 90% are focusing ondigital NN accelerators

Project Technology

REEXEN Technology-devoted to mixed signal

computing

7

Project Technology

8

Reexen chip architecture

ADA: Analog- Digital Acceleration

To Ada Lovelace, the world's first computer programmer

Project Technology

Analog and analog-digital computers were there

Such analog computers were used,among other things,for NASA’s Mercury, Gemini, and Apollo programs.

Photo: NASA

Analog computer used 1912-1965.

Photo : Steven Fine

9

More efficient and less costly for most basic mathematicalcomputation because signal is continuous

Easier to realize the integration of data acquisition and dataprocessing as sensory information is analog

More effective to realize complex mathematical computationrelated to on chip learning

Project Technology

Advantages of analog computation

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E.g.

8 bit multiplier：Analog：4-10Digital：3000+

8 bit adder：Analog：one wireDigital：200+

Project Technology

Comparison of mixed s ignal computingvs. digital computing : mult ipl ier and adder

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Analog vs d ig i ta l c i rcu i t s :power consumption and area requirements to get the same SNR

Project Technology

12

Source: Hosticka, “Performance comparison of analog and digital circuits”

Difficulties of analog/mixed signal circuits design

Difficult to design Noise, nonlinearity and mismatch

Project Technology

13

Latency-vs-accuracy tradeoff of float vs. integer-only MobileNets on ImageNet using Snapdragon 821 big core

Source：Google Inc 2018 CVPR, “Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference”

D e e p N e u r a l N e t w o r k

Deep neural network: More tolerant for noise and low bit precision; At 8bit integer precision, nearly no accuracy drop comparing to float precision.

Project Technology

Top

1 A

ccur

acy

Latency (ms)

Float

8-bit

5 15 30 60 120

60

40

50

70

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Phase domain, time domain, voltage domain or current domain

Conclusion:• Noise is determined the fundamental physics law for all analog circuit with whatever domain.• Every doubling the power, the SNR is improved by 3 dB.

[B. Murmann, Asilomar 2015]

Mixed-signalEasy

HardScale with process

Phase domain: Kentaro Yoshioka VLSI 2018

Time domain: Anvesha Amravat ISSCC 2019

Appendix-Review of state-of-art NN accelerator

Bold line: Emin. Dashed line: Eop,dig for N = 16. Solid line: Eop,mixed for N =16. Asterisk: post-layout simulation of N = 16, B = 8 bit digital MAC withindependent, uniformly distributed inputs.

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FD-SOI provides choice between speed and power

Source: Coventor Blog

FD-SOI provides higher potential for System on Chip Integration

Source : Soitec

Perfect fit for wireless & ULP / ULL IoT clients in need of :

IoTMobility

Automotive5G & Radars

Best Power/Perf/Cost solution for

Ideal technology for Unique advantages in low power/ high reliability

Low-mid tier Baseband + AP 4G transceiver integration

On-demand processing performanceIntegrated RFEmbedded memoryCost effective

single chip solution with integrated PA <6GHz applications (transceivers) w/ 35-50% die shrink (vs 28 poly) for LTE, Wifi and other wireless applications

ADAS (<5W) for autonomous driving

High Speed Vision Processing Chip Series Based on ADAArchitecture

Efficient vision processing chip ADA100V

AI-assisted education

Augmented/virtual Reality

Driving assistance

Home security & monitoring

Applications Ultra high computing Efficiency: 25~50Tops/W

Mixed signal computing in memory

Reduced latency and support high - speed image/video processing

Reduced chip ad system temperature, improve reliability

Support AI processing by battery power

Features

Scene application

18

Vision processing chip application scenarios

Reducing latency to support high-speed image and video processing

Intelligent Processing for Battery Power Supply

Reduce the temperature of chips and systems to improve reliability

Scene application

19

Data source: CICC Data source: IDC

0.330.85

1.82

5.2

0

1

2

3

4

5

6

Video monitoring Autopilot

Global AI chip segment size（billion US dollars）

2017 2022E

99.8

310.5

230.5

457.5

0

100

200

300

400

500

Intelligent Speaker Audio-visual entertainment equipment

Global smart home devices shipments(million sets)

2018 2022E

Audio processing chip application scenariosUltra-low power voice processing chip ADA100S

Sub-micro watt voice activity detection for smart wake-up of devices

Key word spotting and speaker identification for smart control of wearable devices and home/car appliances.

Scene application

Features

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Chip features:

High efficiency Low cost Reduced latency

& bandwidth

Privacy Protection Flexibility &

on-chip learning

High integration

Technical Advantage

21

CLOUDCOMPUTING

EDGECOMPUTING

SENSOR-ENDCOMPUTING

Connect

intelligent devices

“True” wirelessly

TECHNOLOGYShenzhen & Zurich

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